JPS6037982U - Delay time correction circuit - Google Patents
Delay time correction circuitInfo
- Publication number
- JPS6037982U JPS6037982U JP12865683U JP12865683U JPS6037982U JP S6037982 U JPS6037982 U JP S6037982U JP 12865683 U JP12865683 U JP 12865683U JP 12865683 U JP12865683 U JP 12865683U JP S6037982 U JPS6037982 U JP S6037982U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- composite video
- video signal
- terminal
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Processing Of Color Television Signals (AREA)
- Networks Using Active Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のくし形フィルタのブロック図、第2図a
〜Cは第1図に示したくし形フィルタの動作を説明する
ための図、第3図A−Dは3水平走査期間の信号を第1
図に示した(し形フィルタに入力した場合の垂直方向へ
の遅延の経過を説明するための図、第4図は本考案にな
る遅延時間補正回路の一実施例のブロック図、第5図A
−Eは第4図に示した遅延時間補正回路を説明するため
の図である。
1・・・・・・複合映像信号入力端子、2・・・・・・
1水平走査期間(1/fH)だけ入力信号を遅延する遅
延線、3・・・・・・加算器、4・・・・・・減算器、
5・・・・・・加算器、6・・・・・・輝度(Y)信号
出力端子、7・・・・・・低減通過フィルタ、8・・・
・・・搬送色(C)信号出力端子、9・・・・・・反転
増幅器、10・・・・・・スイッチ。Figure 1 is a block diagram of a conventional comb filter, Figure 2a
~C are diagrams for explaining the operation of the comb filter shown in Figure 1, and Figures 3A to 3D are diagrams for explaining the operation of the comb filter shown in Figure 1.
Figure 4 is a block diagram of an embodiment of the delay time correction circuit according to the present invention; A
-E is a diagram for explaining the delay time correction circuit shown in FIG. 4. 1... Composite video signal input terminal, 2...
a delay line that delays an input signal by one horizontal scanning period (1/fH); 3... an adder; 4... a subtracter;
5... Adder, 6... Luminance (Y) signal output terminal, 7... Reduced pass filter, 8...
... Carrier color (C) signal output terminal, 9 ... Inverting amplifier, 10 ... Switch.
Claims (1)
して重畳されている複合映像信号が入力される複合映像
信号入力端子と、第1の入力端子が前記複合映像信号入
力端子に接続されている第1の加算器と、第1の入力端
子が前記複合映像信号入力端子に接続されている減算器
と、前記複合映像信号入力端子と前記第1の加算器の第
2の入力端子及び前記減算器の第2の入力端子との間に
介挿されている遅延回路と、第1の入力端子が前記第1
の加算器の出力端子に接続されている第2の加算器と、
前記第2の加算器の出力端子に接続されている第1の出
力端子と、前記減算器の出力端子に接続されている第2
の信号出力端子と、前記減算器の出力端子に接続されて
いる低域通過フィルタと、入力端子が前記低域通過フィ
ルタに接続されている反転増幅器と、第1の固定端子が
前記低域通過フィルタと前記反転増幅器の入力端子との
接続部に接続され第2の固定端子が前記反転増幅器の出
力端子に接続され可動接点が前記第2の加算器の第2の
入力端子に接続されているスイッチとからなり、前記複
合映像信号入力端子に入力される複合映像信号から搬送
色信号と輝度信号とを分離すると共に、前記複合映像信
号入力端子に入力される複合映像信号に対応して前記第
2の加算器から出力される信号の遅延時間を前記スイッ
チにより選択切換えするように構成した遅延時間補正回
路。A composite video signal input terminal into which a composite video signal in which a carrier color signal is superimposed in a luminance signal band in an interleaved relationship is input, and a first input terminal is connected to the composite video signal input terminal. a first adder; a subtracter whose first input terminal is connected to the composite video signal input terminal; the composite video signal input terminal and the second input terminal of the first adder; a delay circuit inserted between the first input terminal and the second input terminal of the first input terminal;
a second adder connected to the output terminal of the adder;
a first output terminal connected to the output terminal of the second adder; and a second output terminal connected to the output terminal of the subtracter.
a low-pass filter connected to the output terminal of the subtractor; an inverting amplifier having an input terminal connected to the low-pass filter; a first fixed terminal connected to the low-pass filter; A second fixed terminal is connected to a connection between the filter and the input terminal of the inverting amplifier, a second fixed terminal is connected to the output terminal of the inverting amplifier, and a movable contact is connected to a second input terminal of the second adder. The switch separates a carrier color signal and a luminance signal from the composite video signal input to the composite video signal input terminal, and separates the carrier color signal and luminance signal from the composite video signal input to the composite video signal input terminal, and separates the carrier color signal and the luminance signal from the composite video signal input to the composite video signal input terminal. A delay time correction circuit configured to selectively change the delay time of the signal output from the second adder using the switch.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12865683U JPS6037982U (en) | 1983-08-20 | 1983-08-20 | Delay time correction circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12865683U JPS6037982U (en) | 1983-08-20 | 1983-08-20 | Delay time correction circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6037982U true JPS6037982U (en) | 1985-03-15 |
Family
ID=30291788
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12865683U Pending JPS6037982U (en) | 1983-08-20 | 1983-08-20 | Delay time correction circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6037982U (en) |
-
1983
- 1983-08-20 JP JP12865683U patent/JPS6037982U/en active Pending
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