JPS62125779A - Video signal processor - Google Patents

Video signal processor

Info

Publication number
JPS62125779A
JPS62125779A JP60265220A JP26522085A JPS62125779A JP S62125779 A JPS62125779 A JP S62125779A JP 60265220 A JP60265220 A JP 60265220A JP 26522085 A JP26522085 A JP 26522085A JP S62125779 A JPS62125779 A JP S62125779A
Authority
JP
Japan
Prior art keywords
signal
circuit
output
comb filter
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60265220A
Other languages
Japanese (ja)
Inventor
Haruo Oota
晴夫 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60265220A priority Critical patent/JPS62125779A/en
Publication of JPS62125779A publication Critical patent/JPS62125779A/en
Pending legal-status Critical Current

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  • Color Television Systems (AREA)
  • Picture Signal Circuits (AREA)

Abstract

PURPOSE:To realize simultaneously the function of a vertical preemphasis and the function for a comb-line filter for removing chrominance signal component by using only one 1H delay circuit by applying a required processing for adding an input signal A and a signal B obtained by delaying a signal B by 1 horizontal scanning period. CONSTITUTION:The input signal from an input terminal 101 and the output signal of a 1H delay circuit 105 are added in an addition circuit 102 and the signal multiplied by a prescribed coefficient (d) in a coefficient circuit 103 and the input signal from the input terminal 101 are added. Further, after the output signal of the 1H delay circuit 105 is subtracted, the output is multiplied by 1/2 in a coefficient circuit 107 and becomes the output of a feedback type comb- line filter 100. Thereby, by using only 1H delay circuit, the function for the vertical non-linear type preemphasis is performed with respect to a luminance signal below about 3MHz of a horizontal frequency of a passing band of a low-pass filter 108 and the function for the comb-line filter is performed in above about 3MHz of the horizontal frequency.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ビデオテープレコーダなどの映像信号記録再
生装置に用いる映像信号処理装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing device used in a video signal recording and reproducing device such as a video tape recorder.

従来の技術 近年、一般に広く利用されている家庭用ビデオテープレ
コーダなどにおいて、記録再生にともなう雑音を低減す
るため、記録時に画像の垂直方向にプリエンファシスを
行い、再生時にディエンファシスを行うことが提案され
ている。
Conventional technology In recent years, it has been proposed to perform pre-emphasis in the vertical direction of the image during recording and de-emphasis during playback in order to reduce the noise associated with recording and playback in home video tape recorders, which are widely used in general. has been done.

以下図面を参照しながら、従来の垂直プリエンファシス
装置の一例について説明する。
An example of a conventional vertical pre-emphasis device will be described below with reference to the drawings.

第4図は、従来の垂直プリエンファシス装置の一例を示
す構成図である。第4図において、入力端子1には記録
されるべき輝度信号が入力される。
FIG. 4 is a configuration diagram showing an example of a conventional vertical pre-emphasis device. In FIG. 4, a luminance signal to be recorded is input to an input terminal 1.

入力された信号は加算回路2において、信号を1水平走
査期間(IH)遅延するIH遅延回路4によって遅延さ
れ、係数回路5において所定の係数を乗ぜられた信号と
加算される。加算回路2の出力信号はIH遅延回路4の
入力となるとともに、係数回路3を経て減算回路6に導
かれて入力端子1からの入力信号から減算される。減算
回路6によって得られた信号は、非線形入出力回路7に
よって振幅制限され係数回路8を経て加算回路9におい
て入力信号と加算され、出力端子10より出力される。
In the adder circuit 2, the input signal is delayed by an IH delay circuit 4 which delays the signal by one horizontal scanning period (IH), and is added to a signal multiplied by a predetermined coefficient in a coefficient circuit 5. The output signal of the adder circuit 2 is input to the IH delay circuit 4, and is led to the subtracter circuit 6 via the coefficient circuit 3, where it is subtracted from the input signal from the input terminal 1. The signal obtained by the subtraction circuit 6 is amplitude limited by a nonlinear input/output circuit 7, passes through a coefficient circuit 8, is added to the input signal in an addition circuit 9, and is outputted from an output terminal 10.

以上の結果、出力端子10より得られる信号は、小振幅
の信号の垂直周波数における高域成分が強調される垂直
非線形プリエンファシスされた信号となる。(例えば、
特開昭60−30285号公報)発明が解決しようとす
る問題点 ところで、このような垂直プリエンファシス装置に入力
信号される信号は、記録すべきカラー映像信号から色信
号を除去した輝度信号である。ところが近年のVTRに
おいては、輝度信号の水平解像度を維持し、かっ色信号
と輝度信号との間の妨害を減らすために、IH遅延回路
を用いたくし型フィルタによって色信号を除去したり、
ローパスフィルタによって色信号をある程度除去した後
くし型フィルタによって完全に色信号を除去した輝度信
号を得る構成とすることが多い。したがってこの場合に
は、ガラス遅延線やCCD、あるいはデジタルメモリー
などによる高価なIH遅延回路がくし型フィルタと垂直
プリエンファシス装置とで2つ必要となり、コストが上
がることはまぬがれないという問題点を有している。
As a result of the above, the signal obtained from the output terminal 10 becomes a vertically nonlinear pre-emphasized signal in which the high frequency component in the vertical frequency of the small amplitude signal is emphasized. (for example,
Problems to be Solved by the Invention Incidentally, the signal input to such a vertical pre-emphasis device is a luminance signal obtained by removing the color signal from the color video signal to be recorded. . However, in recent VTRs, in order to maintain the horizontal resolution of the luminance signal and reduce interference between the brown signal and the luminance signal, the color signal is removed by a comb filter using an IH delay circuit.
In many cases, a configuration is adopted in which a luminance signal is obtained by removing a certain amount of color signal with a low-pass filter and then removing the color signal completely with a comb filter. Therefore, in this case, two expensive IH delay circuits using glass delay lines, CCDs, digital memories, etc. are required for the comb filter and the vertical pre-emphasis device, which inevitably increases costs. ing.

本発明はこの様な点を考慮し、一つのIH遅延回路を用
いて、垂直プリエンファシスの機能と色信号を除去する
ためのくし型フィルタとを同時に実現する映像信号処理
装置を提供することを目的としている。
In consideration of these points, the present invention aims to provide a video signal processing device that simultaneously realizes a vertical pre-emphasis function and a comb filter for removing color signals using a single IH delay circuit. The purpose is

問題点を解決するための手段 本発明は上記問題点を解決するため、入力信号Aと、信
号Bを1水平走査期間遅延した信号Cとを加算して信号
りを得、前記信号りに所定の係数を乗じたのち前記信号
Aを加算して前記信号Bを得、前記信号Bと前記信号C
との差信号を1/2倍したものを出力とすることにより
垂直周波数の高域成分を抽出する帰還型くし型フィルタ
を備え、水平周波数の高域については前記帰還型くし型
フィルタによって抽出された垂直周波数の高域成分を抑
圧し、水平周波数の低域については前記帰還型くし型フ
ィルタによって抽出された垂直周波数の高域成分を強調
して出力するものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention adds the input signal A and the signal C, which is obtained by delaying the signal B by one horizontal scanning period, to obtain a signal, and adds a signal to the signal by a predetermined value. After multiplying by a coefficient, the signal A is added to obtain the signal B, and the signal B and the signal C are
A feedback comb filter is provided which extracts the high frequency component of the vertical frequency by outputting the difference signal multiplied by 1/2, and the high frequency component of the horizontal frequency is extracted by the feedback comb filter. The high frequency components of the vertical frequencies extracted by the feedback comb filter are emphasized and the high frequency components of the horizontal frequencies extracted by the feedback comb filter are outputted.

作用 これによって、本発明はただ一つのIH遅延回路を用い
て、OHzから3MHz程度までの輝度信号に対しては
垂直プリエンファシスとして機能し、また3MHz以上
の周波数の信号に対しては色信号成分を除去するくし型
フィルタとして機能する。
As a result, the present invention uses only one IH delay circuit to function as a vertical pre-emphasis for luminance signals from OHZ to about 3 MHz, and as a chrominance signal component for signals with frequencies above 3 MHz. It functions as a comb filter that removes.

すなわち、コストを上げることなく垂直プリエンファシ
スの機能と色信号を除去するためのくし型フィルタとを
同時に実現することができる。
That is, the vertical pre-emphasis function and the comb filter for removing color signals can be simultaneously realized without increasing costs.

実施例 以下本発明の実施例について説明する。第1図は本発明
の一実施例における映像信号処理装置の構成図である。
Examples Examples of the present invention will be described below. FIG. 1 is a block diagram of a video signal processing device in one embodiment of the present invention.

第1図において入力端子101には、記録すべきカラー
映像信号からローパスフィルタによって色信号をある程
度除去した信号か、もしくは色信号を除去していないカ
ラー映像信号が人力される。
In FIG. 1, an input terminal 101 receives a signal from which a color signal to be recorded has had its color signal removed to some extent by a low-pass filter, or a color image signal from which the color signal has not been removed.

破線で囲まれた100の部分は帰還型くし型フィルタを
構成しており、入力端子101からの入力信号と、IH
遅延回路105の出力信号とを加算回路102において
加算し、さらにこれを係数回路103において所定の係
数4倍したものと入力端子101からの入力信号とを加
算回路104において加算する。加算回路104の出力
は、IH遅延回路105の入力信号となるとともに減算
回路106に導かれ、IH遅延回路105の出力信号を
差し引かれたのち係数回路107において1/2倍され
て帰還型くし型フィルタ100の出力となる。これによ
り入力端子101から係数回路107に至る帰還型くし
型フィルタ100の周波数特性は、係数回路103にお
ける係数dを適当に設定することにより第2図に示すよ
うに垂直周波数131.25 (ay/ph)  (N
T S C方式の場合)付近の信号を抽出する特性とな
る。またこの特性を2次元周波数領域で表すならば、第
3図における領域Aと領域Bとを合せた領域の信号を抽
出する特性である。
The part 100 surrounded by the broken line constitutes a feedback comb filter, and the input signal from the input terminal 101 and the IH
The output signal of the delay circuit 105 is added in the adder circuit 102, and the resulting signal is multiplied by 4 by a predetermined coefficient in the coefficient circuit 103, and the input signal from the input terminal 101 is added in the adder circuit 104. The output of the adder circuit 104 becomes an input signal of the IH delay circuit 105 and is led to the subtracter circuit 106, where the output signal of the IH delay circuit 105 is subtracted, and then multiplied by 1/2 in the coefficient circuit 107 to form a feedback comb. This becomes the output of filter 100. As a result, by appropriately setting the coefficient d in the coefficient circuit 103, the frequency characteristic of the feedback comb filter 100 from the input terminal 101 to the coefficient circuit 107 can be changed to a vertical frequency of 131.25 (ay/ ph) (N
In the case of the TSC method), it has the characteristic of extracting nearby signals. Moreover, if this characteristic is expressed in a two-dimensional frequency domain, it is a characteristic that extracts a signal in the combined area of area A and area B in FIG. 3.

さて、帰還型くし型フィルタ100の出力はQ llz
〜3MI(Z程度を通過帯域とするローパスフィルタ1
08に導かれる。このとき、ローパスフィルタ108の
出力信号は第3図の領域Aの信号となる。一方、減算回
路109では入力端子101からの入力信号から帰還型
くし型フィルタ100の出力信号が差し引かれ、ローパ
スフィルタ108による遅延時間を補正するための遅延
回路1)0を経て加算回路1)1においてローパスフィ
ルタ108の出力と加算される。
Now, the output of the feedback comb filter 100 is Qllz
~3MI (Low pass filter 1 with pass band around Z
Guided to 08. At this time, the output signal of the low-pass filter 108 becomes a signal in area A in FIG. On the other hand, in the subtraction circuit 109, the output signal of the feedback comb filter 100 is subtracted from the input signal from the input terminal 101. It is added to the output of the low-pass filter 108 at the step .

これにより、減算回路109の出力は第3図における領
域Aと領域Bの周波数成分を抑圧した信号となり、また
加算回路1)1の出力は第3図における領域Bだけの周
波数成分を抑圧した信号となっている。ローパスフィル
タ108の出力信号、すなわち第3図の領域Aの信号は
、係数回路1)2においてエンファシス特性を決める所
定の係数0倍され、非線形入出力回路1)3で振幅制限
されて、加算回路1)4において第3図における領域B
の周波数成分を抑圧した信号である加算回路1)1の出
力との加算を行い、出力端子1)5より出力される。
As a result, the output of the subtraction circuit 109 becomes a signal in which the frequency components of region A and region B in FIG. It becomes. The output signal of the low-pass filter 108, that is, the signal in area A in FIG. 1) Area B in Figure 3 in 4
The signal is added to the output of the adder circuit 1) 1, which is a signal with the frequency component suppressed, and is output from the output terminal 1) 5.

以上の結果、本実施例の映像信号処理装置は、タタ一つ
のIH遅延回路を用いて、ローパスフィルタ108の通
過帯域である水平周波数3Mtlz程度以下の輝度信号
に対しては第3図の領域Aの信号を非線形に強調する垂
直非線形プリエンファシスとして機能し、また水平周波
数3 M Ilz程度以上においては第3図の領域Bの
成分を抑圧するくし型フィルタとして働いて、輝度信号
の水平解像度を劣化させることなく不要な色信号成分を
除去して色信号と輝度信号との間の妨害を低減すること
ができる。
As a result of the above, the video signal processing device of this embodiment uses the IH delay circuit of one tatami to process the luminance signal in the region A of FIG. It functions as a vertical nonlinear pre-emphasis that nonlinearly enhances the signal of the luminance signal, and also functions as a comb filter that suppresses the component of region B in Fig. 3 at horizontal frequencies of about 3M Ilz or higher, degrading the horizontal resolution of the luminance signal. It is possible to reduce interference between the color signal and the luminance signal by removing unnecessary color signal components without causing any interference.

発明の効果 以上述べたように本発明によれば、垂直プリエンファシ
スの機能と色信号成分を除去するくし型フィルタの機能
とを、ただ一つのIH遅延回路を用いて同時に実現する
ことができる。これにより、低コストで高性能なVTR
を得ることができる。
Effects of the Invention As described above, according to the present invention, the function of vertical pre-emphasis and the function of a comb filter for removing color signal components can be simultaneously realized using only one IH delay circuit. This allows for low-cost, high-performance VTRs.
can be obtained.

【図面の簡単な説明】 第1図は本発明の一実施例の映像信号処理装置の構成図
、第2図および第3図は本発明の一実施例の周波数領域
における動作説明の模式図、第4図は従来の垂直プリエ
ンファシス装面の一例を示す構成図である。 100・・・・・・帰還型くし型フィルタ、 105・
・・・・・I H遅延回i、108・・・・・・ローパ
スフィルタ、109. IIL1)4・・・・・・演算
回路、1)0・・・・・・遅延回路。 代理人の氏名 弁理士 中尾敏男 はか1名窮 2 図 利暑 ↑ !亘局浪数〔烙h]
[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a configuration diagram of a video signal processing device according to an embodiment of the present invention, FIGS. 2 and 3 are schematic diagrams illustrating the operation in the frequency domain of an embodiment of the present invention, FIG. 4 is a configuration diagram showing an example of a conventional vertical pre-emphasis mounting surface. 100... Feedback comb filter, 105.
...IH delay circuit i, 108...Low pass filter, 109. IIL1) 4... Arithmetic circuit, 1) 0... Delay circuit. Agent's name: Patent attorney Toshio Nakao Only one name left 2! Watarukyoku Rōkazu [烙h]

Claims (2)

【特許請求の範囲】[Claims] (1)入力信号Aと、信号Bを1水平走査期間遅延した
信号Cとを加算して信号Dを得、前記信号Dに所定の係
数を乗じたのち前記信号Aを加算して前記信号Bを得、
前記信号Bと前記信号Cとの差信号を1/2倍したもの
を出力とすることにより垂直周波数の高域成分を抽出す
る帰還型くし型フィルタを備え、水平周波数の高域につ
いては前記帰還型くし型フィルタによって抽出された垂
直周波数の高域成分を抑圧し、水平周波数の低域につい
ては前記帰還型くし型フィルタによって抽出された垂直
周波数の高域成分を強調して出力することを特徴とする
映像信号処理装置。
(1) Signal D is obtained by adding input signal A and signal C which is obtained by delaying signal B by one horizontal scanning period, and after multiplying said signal D by a predetermined coefficient, said signal A is added to said signal B. obtained,
A feedback comb filter is provided which extracts high frequency components of vertical frequencies by outputting a difference signal between the signal B and the signal C multiplied by 1/2, and the feedback comb filter extracts high frequency components of vertical frequencies. It is characterized by suppressing the high frequency components of the vertical frequency extracted by the feedback comb filter, and emphasizing and outputting the high frequency components of the vertical frequency extracted by the feedback comb filter for the low frequency frequency. A video signal processing device.
(2)帰還型くし型フィルタの入力信号をA、出力信号
をEとしたとき、前記信号Aから信号Eを差し引いて信
号Fを得る第一の演算回路と、前記信号Eを入力とし出
力信号Gを得るローパスフィルタと、前記信号Fを前記
ローパスフィルタよって定まる所定時間だけ遅延した信
号と前記信号Gとを加算して信号Hを得る第二の演算回
路と、前記信号Gを非線形処理して信号Iを得る非線形
入出力回路と、前記信号Hと前記信号Iとを加算する第
三の演算回路とを備えたことを特徴とする特許請求の範
囲第(1)項記載の映像信号処理装置。
(2) When the input signal of the feedback comb filter is A and the output signal is E, a first arithmetic circuit that subtracts the signal E from the signal A to obtain the signal F; and a first arithmetic circuit that receives the signal E and outputs the signal; a low-pass filter for obtaining signal G; a second arithmetic circuit for obtaining signal H by adding the signal G to a signal obtained by delaying the signal F by a predetermined time determined by the low-pass filter; A video signal processing device according to claim (1), comprising a nonlinear input/output circuit that obtains a signal I, and a third arithmetic circuit that adds the signal H and the signal I. .
JP60265220A 1985-11-26 1985-11-26 Video signal processor Pending JPS62125779A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60265220A JPS62125779A (en) 1985-11-26 1985-11-26 Video signal processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60265220A JPS62125779A (en) 1985-11-26 1985-11-26 Video signal processor

Publications (1)

Publication Number Publication Date
JPS62125779A true JPS62125779A (en) 1987-06-08

Family

ID=17414192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60265220A Pending JPS62125779A (en) 1985-11-26 1985-11-26 Video signal processor

Country Status (1)

Country Link
JP (1) JPS62125779A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0313068A (en) * 1989-06-09 1991-01-22 Victor Co Of Japan Ltd Noise reduction circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0313068A (en) * 1989-06-09 1991-01-22 Victor Co Of Japan Ltd Noise reduction circuit

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