JPS59169162U - Contour enhancement circuit - Google Patents

Contour enhancement circuit

Info

Publication number
JPS59169162U
JPS59169162U JP6211283U JP6211283U JPS59169162U JP S59169162 U JPS59169162 U JP S59169162U JP 6211283 U JP6211283 U JP 6211283U JP 6211283 U JP6211283 U JP 6211283U JP S59169162 U JPS59169162 U JP S59169162U
Authority
JP
Japan
Prior art keywords
enhancement circuit
contour enhancement
edge enhancement
output signals
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6211283U
Other languages
Japanese (ja)
Inventor
裕 白石
Original Assignee
日立電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立電子株式会社 filed Critical 日立電子株式会社
Priority to JP6211283U priority Critical patent/JPS59169162U/en
Publication of JPS59169162U publication Critical patent/JPS59169162U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は2線同時読出し方式の固体撮像装置の信号読出
し部分の構成を示す構成図、第2図は従来の輪郭強調回
路を含んだ固体テレビカメラの構成図、第3図は本考案
装置の一実施例のカメラ構成図である。 5:センサ、11,12:信号出力線、15:遅延回路
、16.21:加算回路、17. 23. 24:減算
回路、18:インバーク、19.20:アナログスイッ
チ。
Fig. 1 is a block diagram showing the configuration of the signal readout part of a solid-state imaging device using a two-wire simultaneous readout method, Fig. 2 is a block diagram of a solid-state television camera including a conventional contour enhancement circuit, and Fig. 3 is a block diagram of the device according to the present invention. FIG. 2 is a configuration diagram of a camera according to an embodiment. 5: Sensor, 11, 12: Signal output line, 15: Delay circuit, 16.21: Adder circuit, 17. 23. 24: Subtraction circuit, 18: Invert, 19.20: Analog switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 同時に出力する2つの走査線に相当する出力信号を互に
画素補間するよう混同し1走査線に相当する出力信号を
形成する2線同時読出し方式の固体7B(lt=素子の
前記2つの出力信号の差を、輪郭強調13号として使用
する固体撮像装置の輪郭強調回路において、該輪郭強調
信号を1フイールド毎に反転出力する手段と、該出力信
号のうち水平エラ、ジによる輪郭強調信号のみを取出す
手段を有することを特徴とする輪郭強調回路。
A two-line simultaneous readout type solid state 7B (lt = the two output signals of the element) which mixes the output signals corresponding to two scanning lines that are output simultaneously to form an output signal corresponding to one scanning line by mutual pixel interpolation. In the edge enhancement circuit of the solid-state imaging device used as edge enhancement No. 13, the difference between An outline emphasizing circuit characterized in that it has a means for extracting.
JP6211283U 1983-04-27 1983-04-27 Contour enhancement circuit Pending JPS59169162U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6211283U JPS59169162U (en) 1983-04-27 1983-04-27 Contour enhancement circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6211283U JPS59169162U (en) 1983-04-27 1983-04-27 Contour enhancement circuit

Publications (1)

Publication Number Publication Date
JPS59169162U true JPS59169162U (en) 1984-11-12

Family

ID=30192313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6211283U Pending JPS59169162U (en) 1983-04-27 1983-04-27 Contour enhancement circuit

Country Status (1)

Country Link
JP (1) JPS59169162U (en)

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