JPS6025280U - Video signal processing circuit - Google Patents
Video signal processing circuitInfo
- Publication number
- JPS6025280U JPS6025280U JP11685183U JP11685183U JPS6025280U JP S6025280 U JPS6025280 U JP S6025280U JP 11685183 U JP11685183 U JP 11685183U JP 11685183 U JP11685183 U JP 11685183U JP S6025280 U JPS6025280 U JP S6025280U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- video signal
- signal
- output
- input video
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Television Signal Processing For Recording (AREA)
- Picture Signal Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来回路の一例を示すブロック系統図、第２図
Ａ〜Ｅは夫々第１図の動作説明用タイムチャート、第３
図は本考案回路の一実施例を示すブロック系統図、第４
図Ａ〜Ｇは夫々第３図の動作説明用タイムチャードであ
る。
１．１０・・・映像信号入力端子、２，３，７，１１．
１３，１６・・・加算回路、４，１４・・・減算回路、
５，１２・・・ＩＨ遅延回路、６，１５・・・クリップ
回路、８，１８・・・映像信号出力端子、１７・・・係
数回路。Fig. 1 is a block system diagram showing an example of a conventional circuit, Figs. 2 A to E are time charts for explaining the operation of Fig. 1, and Fig. 3
The figure is a block system diagram showing one embodiment of the circuit of the present invention.
Figures A to G are time charts for explaining the operation of Figure 3, respectively. 1.10...Video signal input terminal, 2, 3, 7, 11.
13, 16... Addition circuit, 4, 14... Subtraction circuit,
5, 12... IH delay circuit, 6, 15... Clip circuit, 8, 18... Video signal output terminal, 17... Coefficient circuit.
Claims (1)
の自然数倍の期間遅延する遅延回路に供給し、該遅延回
路の入力映像信号と出力遅延信号とを夫々第２の加算回
路により加算すると共に減算回路により減算し、該減算
回路の出力信号のセンターレベル付近のノイズをり゛リ
ップ回路により除去して得た信号と該第２の加算回路の
出力信号とを夫々第３の加算回路により加算合成し、該
第３の加算回路の出力信号を該第１の加算回路へ帰還入
力して前記入力映像信号に加算合成すると共に出力映像
信号として取り出すよう構成した映像信号の処理回路。The input video signal is supplied through a first addition circuit to a delay circuit that delays the period by a natural number multiple of one horizontal scanning period, and the input video signal and output delayed signal of the delay circuit are respectively added by a second addition circuit. The signal obtained by removing the noise near the center level of the output signal of the subtraction circuit using a ripple circuit and the output signal of the second addition circuit are respectively subtracted by a subtraction circuit. A video signal processing circuit configured to add and combine the output signal of the third adder circuit, feed back the output signal of the third adder circuit to the first adder circuit, add and combine the input video signal with the input video signal, and take out the output signal as an output video signal.
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11685183U JPS6025280U (en) | 1983-07-27 | 1983-07-27 | Video signal processing circuit |
| CA000451092A CA1202413A (en) | 1983-04-07 | 1984-04-02 | Noise reduction circuit for a video signal |
| NLAANVRAGE8401045,A NL189538C (en) | 1983-04-07 | 1984-04-03 | NOISE REDUCTION CHAIN FOR A VIDEO SIGNAL. |
| DE19843412529 DE3412529A1 (en) | 1983-04-07 | 1984-04-04 | NOISE REDUCTION CIRCUIT FOR A VIDEO SIGNAL |
| US06/596,551 US4575760A (en) | 1983-04-07 | 1984-04-04 | Noise reduction circuit for a video signal |
| AU26450/84A AU558091B2 (en) | 1983-04-07 | 1984-04-05 | Video signal noise reduction |
| BR8401618A BR8401618A (en) | 1983-04-07 | 1984-04-06 | INTERFERENCE REDUCTION CIRCUIT FOR VIDEO SIGNAL |
| FR848405521A FR2544147B1 (en) | 1983-04-07 | 1984-04-06 | NOISE REDUCTION CIRCUIT FOR A VIDEO SIGNAL |
| GB08409187A GB2141303B (en) | 1983-04-07 | 1984-04-09 | Noise reduction circuit for a video signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11685183U JPS6025280U (en) | 1983-07-27 | 1983-07-27 | Video signal processing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6025280U true JPS6025280U (en) | 1985-02-20 |
| JPH0110052Y2 JPH0110052Y2 (en) | 1989-03-22 |
Family
ID=30269209
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11685183U Granted JPS6025280U (en) | 1983-04-07 | 1983-07-27 | Video signal processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6025280U (en) |
-
1983
- 1983-07-27 JP JP11685183U patent/JPS6025280U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0110052Y2 (en) | 1989-03-22 |
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