JPH0110052Y2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a video signal processing circuit, and in particular to a processing circuit that improves the signal-to-noise ratio of an input video signal by utilizing vertical correlation (line correlation) of the video signal. Regarding.

Prior Art FIG. 1 shows a block system diagram of an example of a conventional video signal processing circuit. In the figure, an input terminal 1 receives a video signal taken out from a television camera or a video signal played back from a VTR. Specifically, this video signal is a signal such as a luminance signal, a color difference signal, or a primary color signal. The input video signal is branched into three branches and supplied to adder circuits 2 and 3 and subtracter circuit 4, respectively. The output signal of adder circuit 2 is
After being delayed by one horizontal scanning period (1H) by the 1H delay circuit 5, the signal is supplied to the adder circuit 3, where it is added and synthesized with the input video signal. The output signal of the adder circuit 3 is fed back to the adder circuit 2 and added to the input video signal, while being supplied to the subtractor circuit 4 and subtracted from the input video signal.

Now, if the input video signal has a rectangular waveform as shown in FIG. 2A, and noise is superimposed on it, the output signal of the adder circuit 3 will be as shown in FIG. 2B, The output signal of the subtraction circuit 4 has a waveform obtained by differentiating the input video signal, as shown in FIG. The output signal of this subtraction circuit 4 is supplied to a clip circuit 6 having a known configuration, where it is clipped at a predetermined clip level set in advance, and as shown in FIG. 2D, the noise superimposed on the center level is removed. The result is a removed signal. The output signal of this clipping circuit 6 is supplied to an adder circuit 7, where it is added and synthesized with a signal having a waveform as shown in FIG. After being returned to a waveform signal, it is output to the output terminal 8.

Here, the video signal containing noise is delayed by 1H,
When added to a video signal that has not been delayed by 1H, the video signal component is doubled and the noise is multiplied by √2, which ultimately improves the signal-to-noise ratio (hereinafter also referred to as "S/N") by 3 dB. It is well known that this can be done. However, if this processing is simply performed, and there is almost no correlation between the video signals before and after the 1H delay (at 1H intervals), a correlation error will occur, resulting in a signal with a degraded vertical band.

Therefore, the conventional circuit shown in FIG. 1 has a cyclic filter configuration using a 1H delay circuit 5, and uses a clip circuit 6 to eliminate correlation errors that occur when there is no correlation between video signals before and after the 1H delay. The vertical band deterioration and S/N ratio are improved.

Problems to be solved by the invention However, in the above conventional circuit, the clip circuit 6
The input signal of is a signal as shown in FIG. Therefore, the above correlation error is reduced to the noise P- of the input video signal.
It was not possible to suppress the P value or lower, and it was not possible to further improve the S/N. In addition, since the output signal of the 1H delay circuit 5 is fed back, the pulse width of the output signal of the subtraction circuit 4 is larger than 1H (incidentally, the pulse width of the output signal of the subtraction circuit 4 shown in Fig. 2C is about 10H). ), for an input video signal having an edge portion as shown in FIG. The problem was that it was large.

Therefore, the object of the present invention is to provide a video signal processing circuit that solves the above problem by adding the output signal of the clip circuit with other signals and then feeding it back positively to the input stage of the delay circuit. .

Means for Solving the Problems The present invention supplies an input video signal through a first addition circuit to a delay circuit that delays a period of a natural number multiple of one horizontal scanning period, and outputs the input video signal of the delay circuit and the output delay. The signals are added by a second addition circuit and subtracted by a subtraction circuit, and the noise near the center level of the output signal of the subtraction circuit is removed by a clip circuit, and the resulting signal and the output of the second addition circuit are obtained. and the respective signals are added and synthesized by a third adder circuit, and the output signal of the third adder circuit is fed back to the first adder circuit to add and synthesize the input video signals and to take out the output video signal as an output video signal. An embodiment thereof will be described below with reference to FIGS. 3 and 4.

Embodiment FIG. 3 shows a block diagram of an embodiment of the circuit of the present invention. In the figure, a video signal input to an input terminal 10 is supplied through a first addition circuit 11 to a 1H delay circuit 12, a second addition circuit 13, and a subtraction circuit 14, respectively. The above input video signal is the same as the input video signal of the input terminal 1 described above.
Now, this input video signal is as shown in Figure 4A,
Assuming that the signal a is a rectangular waveform having edges, the signal delayed by 1H by the 1H delay circuit 12 and extracted is as shown by b in FIG. This delayed signal b is supplied to the adder circuit 13, where it is added and synthesized with the output signal of the adder circuit 11 as shown in FIG.
As shown by c, the signal component is doubled and the noise is √2.
The signal is said to be doubled.

At the same time, the delay signal b is sent to the subtraction circuit 14.
Here, subtraction with the output signal of the adder circuit 11 is performed, and as shown in FIG.
is converted into a pulse-like signal d. This signal d consists of a correlation error signal when there is no vertical correlation and a noise component that is √2 times the noise level in the input video signal a. Although noise is superimposed on this signal d throughout the period, the signal d is
The noise near the center level is removed by clipping. That is, the clip circuit 15 is configured to pass a signal component of a first level or higher, which is slightly higher than the center level, and a signal component, which is lower than a second level, which is slightly lower than the center level. , preventing noise from passing between the first level and the second level.

As a result, as shown in FIG. 4E, the clip circuit 15 outputs a signal e from which noise has been removed, that is, a signal e in which only the correlated error signal is extracted, at the center level excluding the pulse portion with a pulse width of 1H. It will be done. The third adder circuit 16 adds and synthesizes this signal e and the above-mentioned signal c, respectively, and outputs a signal f from which correlation errors above the noise P-P value have been removed, as shown in FIG. 4F. . This signal f is supplied to the coefficient circuit 17, where it is given a coefficient β, and then positively fed back to the adder circuit 11, where it is added with the input video signal a to produce a signal g as shown in FIG. 4G. be done. This signal g is supplied to a 1H delay circuit 12, an addition circuit 13, and a subtraction circuit 14, respectively.

Therefore, the signal taken out from the subtraction circuit 14 and supplied to the clip circuit 15 has an improved S/N ratio, and the clip level corresponds to the amount of S/N improvement of the circuit having the clip circuit 15 in the loop. Since it is possible to lower the correlation error, it is possible to reduce the correlation error to a value equal to or less than the noise P-P value of the input video signal a. Furthermore, the area where noise is not improved is only 1H from the edge portion of the input video signal, as shown by T ₁ and T ₂ in FIG. 4F, which corresponds to the pulse width of signal e, and therefore the pulse characteristics will not deteriorate either.

In this way, a video signal with improved S/N is extracted from the adder circuit 16 without deteriorating the pulse characteristics, and is supplied to the coefficient circuit 17 while being output to the output terminal 18.

Application Example Note that the present invention is not limited to the above embodiment, and the S/N improvement effect is worse than that of the embodiment, but instead of the 1H delay circuit 12, a natural number multiple of H of 2H or more is used. It is also possible to use a delay circuit with a delay time of periods.

Effects As mentioned above, according to the present invention, since the clip circuit is included in the loop, it is possible to improve the S/N without deteriorating the pulse characteristics, and it is possible to improve the S/N without deteriorating the pulse characteristics. This has the advantage that the clip level can be lowered to below the noise P-P value of the input video signal, thereby reducing errors without vertical correlation.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing an example of a conventional circuit, FIGS. 2A to 2E are time charts for explaining the operation of FIG. 1, respectively, and FIG. 4A to 4G are time charts for explaining the operation of FIG. 3, respectively. 1, 10...Video signal input terminal, 2, 3, 7,
11, 13, 16... Addition circuit, 4, 14... Subtraction circuit, 5, 12... 1H delay circuit, 6, 15...
...Clip circuit, 8, 18...Video signal output terminal, 17...Coefficient circuit.

Claims (1)

[Scope of utility model registration request] The input video signal is supplied through a first addition circuit to a delay circuit that delays the period by a natural number multiple of one horizontal scanning period, and the input video signal and output delayed signal of the delay circuit are respectively added by a second addition circuit. The signal obtained by removing the noise near the center level of the output signal of the subtraction circuit using a clip circuit and the output signal of the second addition circuit are respectively added and synthesized by a third addition circuit. and a video signal processing circuit configured to feed back the output signal of the third adder circuit to the first adder circuit, add and synthesize it with the input video signal, and take it out as an output video signal.