JPS59186474A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To reduce correlative errors and improve an SN ratio by 3dB by providing an adding circuit which adds a video signal to the delay video signal obtained by delaying said video signal by 1H (one horizontal scanning period), a subtracting circuit which performs subtraction, and a noise clipping circuit which clips noise components and extracts only correlative errors. CONSTITUTION:The video signal (a) is supplied to the adder 2 and also supplied to the adder 2 as a signal which is delayed by 1H through a 1H delay circuit 3. Then, the adder 2 sums up both signals (a) and (b) to obtain a signal (c). The video signal (b), on the other hand, is supplied to the subtracter 4 together with the video signal (a) and both signals are processed by subtraction to generate a signal (d). The signal (d) is supplied to the noise clipping circuit 5 to extract only a correlative error signal as a signal (e), which is supplied to an adder 6 together with the output signal (c) of the adder 2. The adder 6 adds the signal (c) and correlative error signal (e) together to raise the level of the leading edge of the signal (c) to a level twice as high as that of the original video signal (a) by the signal (e) and also cancel the trailing edge of the signal (c) by the signal (e).

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal processing circuit, and in particular, when there is no correlation between video signals before and after a 11" delay, correlation errors can be reduced,
Another object of the present invention is to provide a video signal processing circuit that can improve the S/N ratio by 3 dB.

A conventional video signal noise suppression circuit adds the video signal a shown in FIG. 1(A) and the video signal S shown in FIG. 1(B) which is delayed by 1H, so that the signal component is doubled and the noise component is J7
The configuration was such that a signal C shown in FIG. 3(C) with an improved signal-to-noise ratio of 3 df3 was obtained.

However, as is clear from the diagram (C), this conventional circuit
In the rising and falling parts of signal C, signals a and b appear at 1/2 of the overall level, so especially if there is no correlation between signal a and signal line, this part becomes a correlation error and the correct error occurs. There was a drawback that a reproduced image could not be obtained.

The present invention eliminates the above-mentioned drawbacks, and an embodiment thereof will be described below with reference to the drawings.

FIG. 2 shows a block system diagram of an embodiment of the video signal processing circuit according to the present invention. The video signal a shown in FIG. 1(A) that has entered the terminal 1 is supplied to the adder 2, and is also delayed by one day in the one-day delay circuit 3 and output as the signal shown in FIG. 1(B). and is supplied to the adder 2. Here, both signals a and b are added to form signal C shown in FIG. Signal C is
Double the signal component and add the noise component to the original signal a
It is a signal whose signal-to-noise ratio has been improved by three times.

On the other hand, the video signal S delayed by 1H is supplied to the subtracter 4 together with the video signal a, where both signals are subtracted.
) is the signal d shown in FIG. The signal d is the correlated error signal and 4
It consists of a noise component that is twice as large. The signal d is supplied to the noise clipping circuit 5, where only the correlated error signal is extracted and made into the signal e shown in FIG.

The adder 6 adds the signal C and the correlation error signal e, so that the rising part of the signal C is made twice the level of the original video signal a by the signal e, while the falling part of the signal C is It is canceled by the signal e. That is, the signal f can reduce the correlation error to less than the peak-to-peak value of the noise component, and has an improved signal-to-noise ratio of 3 dB.

The same applies even if the correlation means spans 2H, 31-1, . . . .

As described above, the video signal processing circuit according to the present invention processes a video signal and a delayed video signal that is delayed by 1H. a subtraction circuit that subtracts the video signal and the delayed video signal; a noise clip circuit that clips the noise component superimposed on the output level of the subtraction circuit to extract only the correlated error; and a noise clip circuit that extracts only the correlated error. Since the circuit consists of a circuit that adds the output of Peak of noise component
It has the advantage of being able to reduce the signal to below the peak value, obtain a signal with an improved SN ratio of 3 dB, and obtain a reproduced image of higher quality than conventional circuits.

[Brief explanation of drawings]

FIGS. 1A to 1F are signal waveform diagrams for explaining the operation of the circuit of the present invention, and FIG. 2 is a block system diagram of embodiments of the circuit of the present invention. 1...Video signal input terminal, 2, 6...Adder, 3.
...1 to 1 delay circuit, 4...subtractor, 5...noise clip circuit, 7...output terminal. 1st Toe 1- Fig. 2 7

Claims (1)

[Claims] An addition circuit that adds the video signal and a delayed video signal delayed by 11 inches, a subtraction circuit that subtracts the video signal and the delayed video signal, and noise superimposed on the output level of the subtraction circuit. A video signal processing circuit comprising: a noise clipping circuit that clips components to extract only correlated errors; and a circuit that adds the output of the noise clipping circuit and the pressure of the addition circuit.