KR880000529B1 - Noise reduction circuit for a video signal - Google Patents

Noise reduction circuit for a video signal Download PDF

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Publication number
KR880000529B1
KR880000529B1 KR1019840001729A KR840001729A KR880000529B1 KR 880000529 B1 KR880000529 B1 KR 880000529B1 KR 1019840001729 A KR1019840001729 A KR 1019840001729A KR 840001729 A KR840001729 A KR 840001729A KR 880000529 B1 KR880000529 B1 KR 880000529B1
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South Korea
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signal
circuit
video signal
noise
supplied
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KR1019840001729A
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Korean (ko)
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KR840008565A (en
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신따로 나까가끼
이찌로 네기시
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니뽕빅터 가부시끼가이샤
이노우에 도시야
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)

Abstract

The invention is concerned with the processing circuit of image signal which can reduce a correlation error and improve S/N ratio. The image signal (a) in terminal (1) is supplied to adder (2) and simultaneously delayed in 1H delay-circuit (3). The delayed image signal (b) and the image signal (a) is supplied to the subtractor (4) . As a result, the signal (d) which is supplied to a noise-clip circuit (5) is formed. The noise-clip circuit extracts only a correlation error signal and the signal (e) is formed. The signal (e) and the output signal (c) of an adder (2) is supplied to the adder (6). Therefore, in the final signal the noise and S/N ratio are improved.

Description

영상신호 처리회로Image signal processing circuit

제1(a)도 내지 제1(f)도는 본 발명 회로의 동작 설명용 신호 파형도.1 (a) to 1 (f) are signal waveform diagrams for explaining the operation of the circuit of the present invention.

제2도는 본 발명 회로의 일실시예의 블럭 계통도.2 is a block schematic diagram of one embodiment of a circuit of the invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 영상신호 입력단자 2, 6 : 기산기1: Video signal input terminal 2, 6: Calculator

3 : 제1H 지연회로 4 : 감산기3: 1H delay circuit 4: subtractor

5 : 노이즈 클립회로 7 : 출력단자5: Noise clip circuit 7: Output terminal

본 발명은 영상신호 처리회로에 관한 것으로 특히 1H 지연 전후의 영상신호에 상관이 없는 경우 상관오차를 감소할 수 있고 또한 SN비를 3db 개선할 수 있는 영상신호 처리회로를 제공하는 것을 목적으로 한다.The present invention relates to a video signal processing circuit, and in particular, to provide a video signal processing circuit which can reduce a correlation error and improve an SN ratio by 3db when there is no correlation between the video signals before and after 1H delay.

종래의 영상신호의 노이즈 억압회로는 제1(a)도에 나타내는 영상신호 a와 이것을 1H 지연한 제1(b)도에 나타내는 영상신호 b를 가산하고, 신호성분은 2배, 노이즈 성분은 □2배의 3db SN비를 개선시킨 제1(c)도에 나타내는 신호 C를 얻는 구성으로 되어 있었다. 그런데 이 종래 회로는 제1(c)도에 의해 명확하게된 바와같이, 신호 C의 입상부분 및 입하부분은 신호 a, b가 전체 레벨의 1/2 레벨로 나타내기 때문에 특히, 신호 a와 신호 b에 상관이 없는 경우 이 부분이 상관오차로 되어 바른 재생화상을 얻을 수 없는 결점이 있었다.The noise suppression circuit of the conventional video signal adds the video signal a shown in FIG. 1 (a) and the video signal b shown in FIG. 1 (b) with a delay of 1H. The signal component is doubled and the noise component is □. The signal C shown in FIG. 1 (c) which doubled the 3db SN ratio was obtained. However, in this conventional circuit, as is clear from FIG. 1 (c), since the standing part and the receiving part of the signal C represent the signals a and b at 1/2 level of the entire level, in particular, the signal a and the signal If it does not correlate with b, this part has a correlation error, and a correct reproduction image cannot be obtained.

본 발명은 상기 결점을 제거한 것으로 이하 도면과 함께 그 일시예에 관해서 설명한다.The present invention will be described below with reference to the accompanying drawings, in which the above-described drawbacks are eliminated.

제2도는 본 발명인 영상신호 처리회로의 일시예의 블럭계통도를 도시한다. 단자(1)에 들어온 제1(a)도에 나타내는 영상신호 a는 가산기(2)에 공급되는 동시에 1H 지연회로(3)에서 1H 지연되어 제1(b)도에 나타내는 신호 b로 되어 가산기(2)에 공급된다. 여기서 두 신호 a, b가 가산되어 제1(c)도 나타내는 신호 c로 된다. 신호 c는 본래의 신호 a에 대해서 신호 성분이 2배 노이즈 성분이 □2배 되어 SN비가 3db 개선된 신호이다.2 shows a block diagram of a temporary example of the video signal processing circuit of the present invention. The video signal a shown in FIG. 1 (a) entering the terminal 1 is supplied to the adder 2 and is delayed by 1H in the 1H delay circuit 3 to become the signal b shown in FIG. 2) is supplied. Here, two signals a and b are added to become a signal c also representing the first (c). The signal c is a signal whose signal component is twice the noise component by 2 times the original signal a and the SN ratio is improved by 3 db.

한편, 1H 지연된 영상신호 b는 영상신호 a와 함께 감산기(4)에 공급되어 여기서 양 신호가 감산되고, 제1(d)도에 나타내는 신호 d로 된다. 신호 d는 상관오차 신호와 □2배의 노이즈 성분으로 이루어진다.On the other hand, the 1H delayed video signal b is supplied to the subtractor 4 together with the video signal a, where both signals are subtracted to become the signal d shown in FIG. 1 (d). The signal d consists of a correlation error signal and a noise component twice as large.

신호 d는 노이즈 클립회로(5)에 공급되고, 여기서 상관오차 신호만 추출되어서 제1(e)도에 나타내는 신호 e로 되고, 가산기(2)의 출력신호 C와 함께 가산기(6)에 공급된다.The signal d is supplied to the noise clip circuit 5, where only the correlation error signal is extracted to be the signal e shown in FIG. 1 (e), and is supplied to the adder 6 together with the output signal C of the adder 2. FIG. .

가산기(6)에 있어서 신호 c와 상관오차 신호 e가 가산되고, 이것에 따라 신호 c의 입상부분은 신호 e에 따라 본래의 영상신호 a의 2배의 레벨로 되는 한편, 신호 c의 입하 부분은 신호 e에 따라 지워진다. 즉, 신호 f는 상관오차를 노이즈 성분의 피크 대 피크치 이하로 저감할 수 있으며, 그 밖에도 3db의 SN비를 개선한 신호로 된다.In the adder 6, the signal c and the correlation error signal e are added, whereby the winning part of the signal c becomes twice the level of the original video signal a according to the signal e, while the incoming part of the signal c Cleared according to signal e. That is, the signal f can reduce the correlation error below the peak-to-peak value of the noise component, and in addition, the signal f becomes an improved signal of SN ratio of 3db.

또한 상관수단은 2H, 3H, ...,에 대한 것에 있어서도 같다.The correlation means is also the same for 2H, 3H, ...,.

상술한 바와같이 본 발명에 따라 구성된 영상신호 처리회로는 영상신호와 이것을 1H 지연시킨 지연 영상신호를 가산하는 가산회로와, 영상신호와 지연 영상신호를 감산하는 감산회로와 감산회로의 출력중 제로 레벨에 중첩시키는 노이즈 성분을 클립하여 상관 오차만을 취출하는 노이즈 클립회로와, 노이즈 클립회로의 출력과 상기 가산회로의 출력을 가산하는 가산회로로써 구성하였기 때문에, 단순히 영상신호와 이것을 1H 지연시킨 신호를 가산한 만큼 종래 회로에 비해서 상관오차를 노이즈 성분의 피크 대 피크치 이하로 저감할 수 있으며, 더우기 3db의 SN비를 개선시킨 신호를 얻을 수 있으며, 종래 회로보다도 고품질의 재생화상을 얻을 수 있는 등의 장점을 갖고 있다.As described above, the video signal processing circuit constructed in accordance with the present invention includes an addition circuit for adding a video signal and a delayed video signal delayed by 1H, a zero level of output of a subtracting circuit and a subtracting circuit for subtracting the video signal and the delayed video signal. It consists of a noise clip circuit which clips noise components superimposed on the circuit and extracts only a correlation error, and an adder circuit that adds the output of the noise clip circuit and the output of the adder circuit. Compared with the conventional circuit, the correlation error can be reduced to less than the peak-to-peak value of the noise component. Furthermore, a signal having an improved SN ratio of 3 db can be obtained, and a higher quality reproduction image can be obtained than the conventional circuit. Have

Claims (1)

영상신호와 이것을 1H 지연시킨 지연 영상신호를 가산하는 가산회로(2)와, 상기 영상신호와 상기 지연 영상신호를 감산하는 감산회로(4)와 , 상기 감산회로의 출력중 제로 레벨에서 중첩된 노이즈 성분을 클립하여 상관오차만을 취출하는 노이즈 클립회로(5)와, 상기 노이즈 클립회로의 출력과 상기 가산회로의 출력을 가산하는 회로(6)로 이루어지는 것을 특징으로 하는 영상신호 처리회로.An addition circuit 2 for adding the video signal and the delayed video signal with a delay of 1H, a subtraction circuit 4 for subtracting the video signal and the delayed video signal, and noise superimposed at zero levels among the outputs of the subtraction circuit. And a noise clip circuit (5) which clips components to take out only correlation errors, and a circuit (6) which adds the output of the noise clip circuit and the output of the addition circuit.
KR1019840001729A 1983-04-07 1984-04-02 Noise reduction circuit for a video signal KR880000529B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP58061295A JPS59186474A (en) 1983-04-07 1983-04-07 Video signal processing circuit
JP61295 1983-04-07
JP58~61295 1983-04-07

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KR840008565A KR840008565A (en) 1984-12-15
KR880000529B1 true KR880000529B1 (en) 1988-04-09

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KR1019840001729A KR880000529B1 (en) 1983-04-07 1984-04-02 Noise reduction circuit for a video signal

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105906B2 (en) * 1986-05-28 1995-11-13 ソニー株式会社 Noise reduction device
JPS63304778A (en) * 1987-06-05 1988-12-13 Hitachi Denshi Ltd Video signal processor
JPH02142282A (en) * 1988-11-24 1990-05-31 Hitachi Denshi Ltd Video signal processor

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KR840008565A (en) 1984-12-15

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