JPS5939575U - noise reduction circuit - Google Patents

noise reduction circuit

Info

Publication number
JPS5939575U
JPS5939575U JP13374582U JP13374582U JPS5939575U JP S5939575 U JPS5939575 U JP S5939575U JP 13374582 U JP13374582 U JP 13374582U JP 13374582 U JP13374582 U JP 13374582U JP S5939575 U JPS5939575 U JP S5939575U
Authority
JP
Japan
Prior art keywords
output
noise signal
subtraction
limiter
large amplitude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13374582U
Other languages
Japanese (ja)
Inventor
成田 隆人
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP13374582U priority Critical patent/JPS5939575U/en
Publication of JPS5939575U publication Critical patent/JPS5939575U/en
Pending legal-status Critical Current

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Landscapes

  • Picture Signal Circuits (AREA)
  • Noise Elimination (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のノイズリダクション回路を示すブロック
図、第2図はその各部の信号を示す信号波形図、第3図
は本考案によるノイズリダクション回路の一実施例を示
すブロック図、第4図はその各部の信号を示す信号波形
図である。 1・・・ノイズリダクション回路、2・・・バイパスフ
ィルタ、3・・・ノイズ抽出回路、4・・・リミッタ、
5゛・・・遅延回路、6・・・減算回路、7・・・位相
進め回路、11・・・大振幅波形部補正回路、12・・
・バイパスフィルタ、13・・・リミッタ、14・・・
レベル調整回路、15・・・減算回路。
Fig. 1 is a block diagram showing a conventional noise reduction circuit, Fig. 2 is a signal waveform diagram showing signals of each part thereof, Fig. 3 is a block diagram showing an embodiment of the noise reduction circuit according to the present invention, Fig. 4 is a signal waveform diagram showing signals of each part. 1... Noise reduction circuit, 2... Bypass filter, 3... Noise extraction circuit, 4... Limiter,
5... Delay circuit, 6... Subtraction circuit, 7... Phase advance circuit, 11... Large amplitude waveform part correction circuit, 12...
・Bypass filter, 13...Limiter, 14...
Level adjustment circuit, 15... subtraction circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 映像信号を第1のバイパスフィルタ及び第1のリミッタ
を順次通過させることにより大振幅波形部を含む抽出ノ
イズ信号を得、この抽出ノイズ信号を減算入力として受
ける第1の減算回路において上記映像信号から減算する
ことによって上記映像信号のノイズ成分を除去するよう
になされたノイズリダクション回路において、上記映像
信号を受けかつ上記第1のバイパスフィルタのカットオ
フ周波数より低いカットオフ周波数をもつ第2のバイパ
スフィルタと、この第2のバイパスフィルタの出力を受
けてその出力に含まれる大振幅波形部の立上り時間を上
記抽出ノイズ信号の対応する大振幅波形部の立上り時間
幅とほぼ等しくするような振幅制限特性をもつ第2のリ
ミッタと、この第2のリミッタの出力を受けて当該出力
に含まれる大振幅波形部の振幅値を上記抽出ノイズ信号
の対応す゛る大振幅波形部の振幅値とほぼ等しくするよ
うに出力レベルを抑圧するレベル調整回路と、上記抽出
ノイズ信号から上記レベル調整回路の出力を減算して当
該減算出力を上記第1の減算回路への上記減算入力とし
て送出する第2の減算回路とを具えることを特徴とする
ノイズリダクション回路。
A video signal is sequentially passed through a first bypass filter and a first limiter to obtain an extracted noise signal including a large amplitude waveform portion, and a first subtraction circuit that receives this extracted noise signal as a subtraction input extracts the extracted noise signal from the video signal. a second bypass filter that receives the video signal and has a cutoff frequency lower than the cutoff frequency of the first bypass filter; and an amplitude limiting characteristic that receives the output of the second bypass filter and makes the rise time of the large amplitude waveform part contained in the output almost equal to the rise time width of the corresponding large amplitude waveform part of the extracted noise signal. a second limiter having a second limiter, and receiving an output of the second limiter so as to make the amplitude value of a large amplitude waveform portion included in the output approximately equal to the amplitude value of the corresponding large amplitude waveform portion of the extracted noise signal. a level adjustment circuit that suppresses the output level of the noise signal; and a second subtraction circuit that subtracts the output of the level adjustment circuit from the extracted noise signal and sends the subtraction output as the subtraction input to the first subtraction circuit. A noise reduction circuit characterized by comprising:
JP13374582U 1982-09-02 1982-09-02 noise reduction circuit Pending JPS5939575U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13374582U JPS5939575U (en) 1982-09-02 1982-09-02 noise reduction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13374582U JPS5939575U (en) 1982-09-02 1982-09-02 noise reduction circuit

Publications (1)

Publication Number Publication Date
JPS5939575U true JPS5939575U (en) 1984-03-13

Family

ID=30301586

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13374582U Pending JPS5939575U (en) 1982-09-02 1982-09-02 noise reduction circuit

Country Status (1)

Country Link
JP (1) JPS5939575U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60143028A (en) * 1983-12-29 1985-07-29 Matsushita Electric Ind Co Ltd Noise reducing device
DE3819725A1 (en) * 1987-06-09 1989-01-05 Sony Corp CIRCUIT FOR ELIMINATING A NOISE SIGNAL

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60143028A (en) * 1983-12-29 1985-07-29 Matsushita Electric Ind Co Ltd Noise reducing device
DE3819725A1 (en) * 1987-06-09 1989-01-05 Sony Corp CIRCUIT FOR ELIMINATING A NOISE SIGNAL

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