JPS60143028A - Noise reducing device - Google Patents

Abstract

PURPOSE:To eliminate phase shift in quick response to the change at an edge where a signal DC level is changed suddenly by appling a prescribed conversion when an output amplitude of an FIR filter exceeds a prescribed value. CONSTITUTION:A rectangular water signal A from an input terminal 1 is inputted to the FIR filter 2, its output B is compared with prescribed values +Vd, -Vd decided at the inside of an amplitude processing circuit 3 and an output C of the comparator circuit 4 is outputted to a switch 5. When the output B of the filter 2 exceeds the prescribed values +Vd, -Vd, the output is outputted while being replaced with the prescribed values +Vd, -Vd. When the output B is a value within the range of the +Vd and -Vd, the output B is outputted as it is. A subtraction circuit 7 substracts an output D of the amplitude processing circuit 3 from the input signal A matched with the time by a delay circuit 6 and gives the result to an output terminal 8. As a result, a signal eliminating a low level high frequency noise from the input signal A is outputted to the output terminal 8.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention reduces noise from digital television signals used in magnetic recording and reproducing devices, television devices, video disc devices, etc., and improves S/N. The present invention relates to a noise reduction device that can perform

Conventional configuration and its problems Conventionally, a noise reduction device for reducing noise such as in television signals and improving S/N has been using a high-pass filter 1 composed of a capacitor and a resistor as shown in Fig. 1. (hereinafter referred to as HPF 1), a limiter 3 constituted by an amplifier 2 and two diodes, and a subtraction circuit 4 that subtracts the output signal of the limiter 3 from the input signal input to the HPF 1. Below, in the configuration of the conventional noise reduction device shown in FIG. 1, the operation of each part when a rectangular wave signal with low-level high-frequency noise shown in FIG. 2A is input is shown in the operation waveform diagram shown in FIG. Explain using.

First, when the rectangular wave signal shown in Figure 2 A is input as an input signal, the HPFl shown in Figure 1 responds to the sudden rise or fall of the input signal A due to the time constant determined by the constituting capacitor and resistor. produces a response in which the amplitude level of the output is gradually attenuated as shown in FIG. 2B. The amplifier 2 amplifies the amplitude of this signal and guides it to the limiter 3. Shi2kashi HP
In the rising and falling signals appearing at the output B of Fl, the amplitude of the signal obtained by amplifying the output B of the HPF 1 by the amplifier 2 is set to a certain value (hereinafter referred to as limiter level) determined by the diode constituting the limiter 3 in FIG. If it exceeds the amplitude, the limiter 3 limits the amplitude and suppresses the amplitude to the limiter level.

Therefore, the output of the limiter 3 outputs the limiter level during the period when the output of the amplifier 2 exceeds the limiter level after the rise and fall of the output B of the HPFl, and then gradually attenuates due to the time constant of the HPFl. This signal becomes the output C of the limiter 3 in FIG. The subtraction circuit 4 subtracts the output C of the limiter 3 from the input signal A, and outputs an output signal from which low-level high-frequency noise has been removed as the output signal of the noise reduction device shown in FIG.

However, as can be seen from the output signal in Fig. 2, the configuration of the conventional noise reduction device shown in Fig. 1 removes low-level high-frequency noise; For signals with edges where the DC level suddenly changes, such as rising edge 9 or falling edge, the DC level at the edge is changed by the limiter level determined in limiter 3, and then the input Since the convergence of the output signal to the same DC level as the signal A is carried out gradually with a time constant determined by HPFl, the convergence time is also very long and there is a drawback that immediate response is lacking. for example,
If you want to remove IMHz noise in the configuration of the noise reduction device shown in Figure 1, the time constant of HPFl should be set to about 300 n5.
Must be set to ec. At this time, assuming that the limiter level with respect to the maximum amplitude of the input signal is about 120 dB, the period during which the amplitude of the output signal of HPF1 exceeds the limiter level is nearly 1 μsec. After that, the HP is further attenuated by about 10 dB from the limiter level.
Approximately 300 n5e is required to eliminate the influence of the DC component of the Fl output signal on the DC level of the signal to be noise reduced.
c is required. As mentioned above, in the noise reduction device shown in Figure 1,
The response at the edge portion where the DC level of the input signal changes suddenly requires a long convergence time of nearly 1.37 tsec. For this reason, there has been a problem in reducing noise in television signals, etc., as it becomes a factor that deteriorates the resolution of the television signals.

Purpose of the Invention The present invention is an attempt to solve these conventional problems, and the effect of improving the S/N of the signal is equivalent to that of the conventional noise reduction device described above, and furthermore, the DC level of the signal suddenly changes. The present invention provides an extremely effective noise reduction device that can quickly respond to changes in edge portions and can be used in digital signal processing that handles digital signals.

Structure of the Invention The present invention provides an FIR filter having a predetermined band, and an FIR filter when the amplitude of the FIR filter output exceeds a certain value.
Noise reduction comprising an amplitude processing circuit that applies a predetermined conversion to a filter output, a delay circuit that delays the FIR filter input signal for a predetermined period, and a subtraction circuit that subtracts the output of the amplitude processing circuit from the output of the delay circuit. 1. The device not only removes low-level high-frequency noise and is effective in improving the S/N ratio, but also can immediately respond to the DC level of the input signal even at edge portions where the DC level changes suddenly. Further, if the FIR filter has a linear phase and the input signal and the FIR filter output are time-aligned using a delay circuit, the phase shift of the signal can be eliminated. Further, the amplitude processing circuit applies a predetermined conversion to the FIR filter output in periods before and after the period in which the amplitude of the FIR filter output exceeds a certain value, so that the output signal of the noise reduction device has a loss with respect to its input signal. It is also possible to eliminate the unnaturalness of the waveform due to the influence of the noise reduction device.

Description of examples Embodiments of the present invention will be described with reference to the drawings.

FIG. 3 shows an embodiment of the noise reduction device of the present invention.
The figure shows operating waveforms in each part of the noise reduction device shown in FIG. 3. First, a rectangular wave signal containing low-level high-frequency noise as shown in FIG. 4A is input as an input signal from the input terminal in FIG. 31.

FIG. 3 shows an FIR filter (a filter with a finite impulse response) having a predetermined band such as a high-pass filter, a band-pass filter, or a comb-shaped filter that blocks direct current components. 2 outputs the output B of the FIR filter 2 in response to the input signal A.

The amplitude processing circuit 3 replaces the output B of the FIR filter 2 with the constant value when it exceeds a certain value determined inside the amplitude processing circuit 3. A comparator circuit 4 that compares the amplitude of the output with a constant value, and an FI
It is comprised of a switch 5 that switches between the R filter output and the constant value and outputs it as an amplitude processing circuit output.

Now, the constant value determined inside the amplitude processing circuit 3 is +
Vd, if it is a negative value -Vd, the FI
When the output B of the R filter 2 is input, the comparator circuit 4
Output B of IR filter 2 is compared with +Vd and GO d, and output C of comparator circuit 4 is output to switch 5. The switch 6 uses the output signal C of the comparator circuit 4 to set the output B of the FIR filter 2 to +Vd if +Vd is larger than +Vd by β, and to set F if the value is within the range of +Vd and -Vd.
The output B of the IR filter 2 is output as is, or -Vd is output if the value is smaller than -Vd, resulting in the output of the amplitude processing circuit 3 shown in FIG. Further, the delay circuit 6 is arranged such that the output signal of the amplitude processing circuit 3 with respect to the input signal A is the same as that of the FIR filter and the amplitude processing circuit 3.
When the input signal A is delayed by the amplitude processing circuit 3, the input signal A is delayed by the delayed time and the input signal A is time-aligned with the output of the amplitude processing circuit 3. Then, the subtraction circuit 7 subtracts the output of the amplitude processing circuit 3 from the input signal A time-aligned by the delay circuit 6 as described above, and sends the result to the output terminal 8. As a result of the above, a signal obtained by removing low-level high-frequency noise from the input signal A is outputted to the output terminal 8 as the output signal E of the noise reduction device.

However, here, the FIR filter 2 blocks the DC component,
Because it is a filter with a finite impulse response, its output does not take the form of the output B of FIR filter 2, where the response at the edge portion where the DC level changes suddenly gradually decays over time, but rather over a finite period of time. Convergence occurs within. Therefore, in the output signal E, the waveform deformation of the edge portion of the signal only appears during the above-mentioned time period, and the low level high frequency noise is removed while the DC level of the signal matches the input signal. Now, in the configuration of the FIR filter 2 shown in Fig. 3, if the unit time interval delay of the discrete signal is expressed by Z- and z2 using Z transformation, then the deformation of the signal waveform in the output signal E is the unit time delay of the discrete signal. If the interval is 1 period, the frequency is 2.
Period 9. (2 clocks), and after that time it matches the DC level of the input signal.

Here, if the frequency of the noise to be reduced is 1 MHz, the clock frequency needs to be 4 MHz, and the waveform deformation is 2 clocks or 50 onsec, resulting in a short response time.

In the above-mentioned noise reduction device shown in FIG. 3, the FIR filter 2 is a linear phase FIR filter 9 that exhibits a characteristic of linear phase in which the delay time of the output signal is constant for input signals over the entire frequency band. An embodiment of the noise reduction device is shown in FIG. 1, 3-8 in FIG. 5 are completely equivalent to FIG. 3, 1, 3-8, respectively. Also, Figure 6 shows the 5th
The figure shows the operating wave numbers in each part of the noise reduction device.
6A is a rectangular wave signal that is equivalent to the input signal A in FIG. 4 and contains low-level high-frequency noise. The noise reduction device shown in Fig. 5 will be explained below using the operating waveforms shown in Fig. 6.
The configuration of the linear phase FIR filter 9 in FIG. 5 is assumed to be -(1-Z). When the input signal shown in FIG. 6A is input to the input terminal 1 in FIG. 6, the linear phase FIR filter 9 outputs the output F of the linear phase FIR filter 9 shown in FIG. 6F. The comparison circuit 4 in the amplitude processing circuit 3 receives this output F from +Vd, -Vd.
The output G of the comparator circuit 4 is output. And the sui nochi 6 is connected to the output F of the linear phase FIR filter 9 and +V
d and -Vd, the output G of the comparator circuit 4 is used to output the output H of the switch 5. Next, the subtraction circuit 7 subtracts the output H of the switch 5 from the input signal A to remove the low level high frequency noise of the input signal A. However, at this time, the phase of the input signal A and the output H of the switch 5 are adjusted between the input signal A and the output H of the switch 5.
If the configuration is shown as <-(1-"2)2 as described above, the input signal A is delayed by two clocks by the delay circuit 6, that is, in the configuration of z-2, and is input to the subtraction circuit 7. As a result, the output signal I is output from the output terminal 8. Here, the waveform deformation of the edge portion of the output signal I with respect to the input signal A is for a period of 2 clocks before and after the edge, for a total of 4 clocks. spans over.

The frequency of the noise targeted by this noise reduction device is I
In terms of MHz, 4 clocks equals 1μSeC, but
Comparing this output signal I with the output signal E shown in FIG. 4 above, we get
The waveforms immediately after the rising edge and falling edge of the signal are exactly the same, but the waveform immediately before that edge is symmetrical with respect to the DC level in the output signal I, and this signal It is possible to eliminate the phase shift caused by the deformation of the waveform at the edge portion of the waveform and perform phase matching.

This makes it possible to reduce noise in the edge portion of the signal and even in the signal over the entire frequency band without causing a phase shift in the signal.

FIG. 7 shows an embodiment of an amplitude processing circuit used in the noise reduction device of the present invention. The comparator circuit in FIG. 74 is completely equivalent to the comparator circuit 4 of the noise reduction device in FIGS. 3 and 5. FIG. 7 and 10 are input terminals for signals input to this amplitude processing circuit, 11 is an output terminal for the output signal of the amplitude processing circuit.

12 switches receive the detection signal from the comparator circuit 4,
When the value of the input signal input from the input terminal 10 is within the range of +Vd and -Vd, the input signal from the input terminal 10, which is one input of the switch 12, is output to the output terminal 11. However, when it is greater than +Vd or less than -Vd, it operates to output the zero value which is the other input of the switch 12 to the output terminal 11. This amplitude processing circuit operates as described above. Instead of outputting +Vd and -Vd during the period in which the input signal to the amplitude processing circuit exceeds +Vd or -Vd, as in the amplitude processing circuit 3 of the noise reduction device shown in Figs. 3 and 5, respectively. By outputting a zero value, the loss of the input signal input to the noise reduction device during that period is eliminated.

Now, let us consider a noise reduction device in which the amplitude processing circuit 3 in FIG. 3 is configured as a seventh mouth amplitude processing circuit in the configuration of the noise reduction device in FIG. 3 described above. FIG. 8 shows the input/output signals in this noise reduction device and the operating waveforms in each part of the seventh amplitude processing circuit at that time. now,
When the input signal shown in FIG. 8A is input as the input signal of the noise reduction device, the input terminal 10 of the seventh amplitude processing circuit
The signal shown in FIG. 8J is input to . And comparison circuit 4
outputs the output K of the comparison circuit 4. The signals shown in FIG. 8 J and above are the operating waveforms of the noise reduction device shown in FIG.
Is it equivalent to B and C in the figure, respectively? Then, the switch 12 of the seventh amplitude processing circuit switches between the input signal I of the amplitude processing circuit input terminal 1o and the zero value using the output K of the comparator circuit 4 and outputs it. Therefore, the output of the amplitude processing circuit is as shown in the output signal of the amplitude processing circuit output terminal 11 in FIG. As a result, the noise reduction device can output signals such as the output signal M without changing the DC level of the rising and falling edge portions of the signal with respect to the input signal A, thereby eliminating signal loss. .

In addition, in the amplitude processing circuit shown in FIG. 7, a predetermined conversion is performed on the amplitude of the signal output from the switch 12 even in the periods before and after the period in which the input signal input from the input terminal 10 exceeds →-Vd or -Vd. In order to provide continuity to the signal and eliminate unnaturalness, the comparison circuit FIG. 9 shows an embodiment of an amplitude processing circuit provided with a gain control circuit 13 that converts the amplitude of the output of the switch 12 using the output of the switch 12 and outputs the output of the limiter. In addition, Fig. 9 4゜10.11.
12 are completely equivalent to 4.10 and 11.12 in FIG. 7, respectively. Further, the operation of the noise reduction device when the amplitude processing circuit 3 in the configuration of the noise reduction device shown in FIG. 3 is changed to the configuration of the amplitude processing circuit shown in FIG. 9 will be explained using the operation waveform diagram in FIG. 1o. ! .

When the input signal N shown in FIG. 10 is input as an input signal to the noise reduction device, the signal shown in FIG. 1o is input to the input terminal 10 of the amplitude processing circuit shown in FIG.

P in FIG. 10 is the output of the comparator circuit 4 which compares the input signal 0 at the input terminal 1o with +Vd and -Vd, and Q is the output of the comparator circuit 4 which compares the input signal 0 at the input terminal 10 with the zero value. This is the output of the switch 12 which switches between and outputs. The gain control circuit 13 knows the period during which the amplitude of the input signal 0 at the input terminal 1o exceeds +vd or -Vd from the output P of the comparator circuit 4, and adjusts the amplitude of the output Q of the switch 12 for the period before and after that period. , outputs the output R of the output terminal 11 to the output terminal 11. As a result, an output signal S is output as an output signal of the noise reduction device. This output signal S
As shown in FIG. 9, discontinuity in the output signal that occurs when the switch 12 is switched can be eliminated by configuring the amplitude processing circuit shown in FIG. 9 in the noise reduction device.

Finally, in the noise reduction apparatus of the present invention shown in FIGS. 3 and 5, the delay circuit 6 delays the input signal input from the input terminal 1 by a predetermined time, so that the same signal as the output of the delay circuit 6 is output. It is clear that if the signal can be taken out from inside the FIR filter 2 in FIG. 3 or the linear phase FIR filter 9 in FIG. 5, that signal can be used as the output of the delay circuit 6. It is also clear that if the output of the amplitude processing circuit 3 or the amplitude processing circuit of FIGS. 7 and 8, which is one input of the subtraction circuit 7, is inverted, the subtraction circuit 7 can be used as an addition circuit.

Effects of the Invention As described above, the noise reduction device of the present invention includes an FIR filter having a predetermined band, an amplitude processing circuit that applies a predetermined conversion to the output of the FIR filter, and an amplitude processing circuit that converts the input signal of the FIR filter for a predetermined period. By providing a delay circuit that delays and a subtraction circuit that subtracts the output of the amplitude processing circuit from the output of the delay circuit, it is possible to reduce Not only can it remove high frequency noise, it can quickly respond to the DC level even at the edges where the DC level of the input signal changes suddenly, but it also reduces signal loss to the input signal and reduces deep noise. It is possible to eliminate the influence and eliminate the unnaturalness of the waveform.

Furthermore, by using the FIR filter as a linear phase FIR filter, it is possible to reduce noise without causing a phase shift even for input signals covering the entire frequency band,
Its practical effects are significant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional noise reduction device, FIG. 2 is an operation waveform diagram of each part in the noise reduction device of FIG. 1, and FIGS. 3 and 5 are noise reduction devices in an embodiment of the present invention. , FIG. 4 is an operating waveform diagram of each part of the noise reduction device of FIG. 3, FIG. 6 is an operating waveform diagram of each part of the noise reduction device of FIG. 5, and FIGS. An example of the amplitude processing circuit of a noise reduction device
), FIG. 8 is an operation waveform diagram of each part of the amplitude processing circuit shown in FIG. FIG. 2...FIR filter, 3...amplitude processing circuit, 4...comparison circuit, 5.12...
Switch, 6・°°°°. Delay (b) path, 7... Subtraction circuit, 9...
Linear phase FIR filter, 13...Gain control circuit. Name of agent: Patent attorney Toshio Nakao and one other name
1 Figure 2 Figure 3, ?ゝ2 Melting 4 Figure 5 Cause 3 2 Figure 6 Figure 7 Garden 8 Figure

Claims (4)

[Claims] (1) FI between an FIR filter having a predetermined band and
an amplitude processing circuit that applies a predetermined conversion to the FIR filter output when the amplitude of the R filter output exceeds a certain value;
A noise reduction device comprising: a delay circuit that delays an input signal of an IR filter for a predetermined period; and a subtraction circuit that subtracts the output of the amplitude processing circuit from the output of the delay circuit. (2) The noise reduction device according to claim 1, wherein the FIR filter is a linear phase FIR filter. (3) The amplitude processing circuit comprises a comparison circuit that compares the amplitude processing circuit input signal with a constant value, and a switch that switches between the amplitude processing circuit input signal and a predetermined value based on the output of the comparison circuit. The noise reduction device according to item 1 or 2. (4) A comparison circuit in which the amplitude processing circuit compares the amplitude processing circuit input signal with a constant value, a switch that switches between the amplitude processing circuit input signal and a predetermined value based on the output of the comparison circuit, and this switch. 3. The noise reduction device according to claim 1, further comprising a gain control circuit that performs a predetermined conversion on the amplitude of the output of the switch in periods before and after a period in which the switch is switched to a predetermined value.