JPS62269477A - Noise eliminator - Google Patents

Noise eliminator

Info

Publication number
JPS62269477A
JPS62269477A JP61112935A JP11293586A JPS62269477A JP S62269477 A JPS62269477 A JP S62269477A JP 61112935 A JP61112935 A JP 61112935A JP 11293586 A JP11293586 A JP 11293586A JP S62269477 A JPS62269477 A JP S62269477A
Authority
JP
Japan
Prior art keywords
signal
circuit
level
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61112935A
Other languages
Japanese (ja)
Inventor
Shoichi Nishino
正一 西野
Seiichi Hashimoto
清一 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61112935A priority Critical patent/JPS62269477A/en
Publication of JPS62269477A publication Critical patent/JPS62269477A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the omission of a signal in the signal of large level from generating, and to increase a noise eliminating effect at an edge part, by providing a non-linear circuit which compresses a signal level to a non-linear shape when the signal level outputted from a differential circuit is large, corresponding to the signal level. CONSTITUTION:The titled device is constituted so that a non-linear circuit 16 which outputs a signal almost in proportion to the signal level when it is small, but compresses the signal level to the nonlinear shape corresponding to the level when the signal is large, is provided between a differential circuit 13 which takes out a change part per prescribed time in an input signal, and a feedback loop consisting of a delay circuit 17, a multiplier 18, and an adder circuit 19. In this case, a factor P to compress the signal of the non-linear circuit 16 keeps a constant value B when the signal level in the high pass component of the signal inputted to the non-linear circuit 16, is small, and the signal in proportion to an input signal level is outputted. But at the time of inputting the signal of large level to the non-linear circuit 16, the signal is outputted after limiting the amplitude of the signal, therefore, no distortion is generated in the signal.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はVTRやビデオディスク装置等に応用して、ビ
デオ信号に含まれる微小な雑音成分を軽減するビデオ信
号の雑音除去装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal noise removal device that is applied to VTRs, video disc devices, etc. and reduces minute noise components contained in video signals.

従来の技術 第4図に従来の雑音除去装置のブロック図を示す。1は
標本化周期Tでディジタル化されたビデオ信号の入力端
子、2は入力端子1から入力されたビデオ信号の標本化
周期Tのn倍(nは正の整数)の時間当りの変化分を取
り出す差分回路で、この差分回路は遅延時間nTを有す
る遅延回路3と、遅延回路3の入力信号からその出力信
号を減じる減算回路4で構成される。6は遅延回路3と
同じ遅延時間nTを有する遅延回路、6は遅延回路5出
力に値Aを乗じる乗算回路、了は乗算回路6出力を前記
差分回路2出力に加えて前記遅延回路已に導く加算回路
、8は加算回路γ出力に乗数Bを乗じる乗算回路、9は
乗算回路8出力の振幅を制限する振幅制限回路、10は
入力端子1より入力した信号から振幅制限回路9出力を
差し引く減算回路、11は出力端子で減算回路10出力
を雑音が軽減されたビデオ信−づを出力する。
BACKGROUND OF THE INVENTION FIG. 4 shows a block diagram of a conventional noise removal device. 1 is the input terminal of the video signal digitized with the sampling period T, and 2 is the change per time of n times the sampling period T (n is a positive integer) of the video signal input from the input terminal 1. This difference circuit is composed of a delay circuit 3 having a delay time nT, and a subtraction circuit 4 that subtracts the output signal from the input signal of the delay circuit 3. 6 is a delay circuit having the same delay time nT as delay circuit 3; 6 is a multiplication circuit that multiplies the output of delay circuit 5 by a value A; An adder circuit, 8 is a multiplier circuit that multiplies the output of the adder circuit γ by a multiplier B, 9 is an amplitude limiter circuit that limits the amplitude of the output of the multiplier circuit 8, and 10 is a subtractor that subtracts the output of the amplitude limiter circuit 9 from the signal input from the input terminal 1. A circuit 11 is an output terminal which outputs the output of the subtraction circuit 10 as a video signal with reduced noise.

以」二のように構成された従来例の雑音除去特性につい
て、離散システムを表わす2変換式を用いて説明する。
The noise removal characteristics of the conventional example configured as described below will be explained using a two-conversion equation representing a discrete system.

捷ず、第4図の遅延回路3および遅延回路5の遅延時間
T(n=1)として説明する。以上の」:うにしたとき
、入力端子1に入力される信号に対する振幅制限回路9
に入力される信−づの伝達関数H(z)d:゛ と表わされる。上式H(2)は高域通過フィルタ(HP
F)の特性を持っているので、振幅制限回路9へは高域
成分のみが入力される。よってその高域成分の振幅が小
さい時d振幅制限回路9はその斗1信月を通すので、減
算回路10によってビデオ信号の微小身高域成分が除去
される。しかし、振幅制限回路9に人力される高域成分
の振幅が大きい場合には、振幅制限された信号が減算回
路10に導かれるので、入力ビデオ信号から除去される
ことはない。以上のような特性は、ビデオ信号に重畳さ
れている微小信号レベルの高域雑音のみを軽減し、信号
とみなすべき信号レベルの大きな高域成分については振
幅制限回路9により振幅制限されるので信号欠除を発生
させない。
The delay time T (n=1) of the delay circuit 3 and the delay circuit 5 shown in FIG. 4 will be explained. "Amplitude limiting circuit 9 for the signal input to input terminal 1 when
The transfer function of the signals input to is expressed as H(z)d:゛. The above equation H(2) is a high-pass filter (HP
F), only high-frequency components are input to the amplitude limiting circuit 9. Therefore, when the amplitude of the high frequency component is small, the d amplitude limiting circuit 9 passes the signal, so the subtraction circuit 10 removes the minute high frequency component of the video signal. However, when the amplitude of the high frequency component inputted to the amplitude limiting circuit 9 is large, the amplitude limited signal is guided to the subtracting circuit 10, so that it is not removed from the input video signal. The characteristics described above reduce only the high-frequency noise of minute signal level superimposed on the video signal, and the amplitude of high-frequency components of large signal level that should be considered as signals is limited by the amplitude limiting circuit 9, so that the signal is Do not cause deletions.

以−にのように構成された従来の雑音除去装置において
、以下第5図の動作波形図を用いて説明する。ここでは
簡単のため入力信号として、第6図aに示すように1=
0でレベルUに変化するステップ信けを用い、これに微
小レベルの高周波の雑音が重畳しているものとする。こ
の信号aが入力端子1に入力されると、差分回路2出力
は第5図すのJ−うなインパルス信号に雑音が重畳され
た信号を出力する。この信号すが遅延回路6、乗算回路
6、および加算回路7で構成されるフィードバックルー
プを通って、振幅制限回路9には第5図Cに示すような
ある時定数(この場合、乗算回路70乗数Aで決丑る)
で信号レベル0に収束する信号に雑音が重畳された信号
が入力される。振幅制御回路9ば、前記信号Cに対して
所定の信号レベル(今、BVとする)を越える部分につ
いて振幅制限を加えるので、その出力は、信号Cにおい
6・、− て、時刻1=Qからtltでのル1間レベルBVでフラ
ットな信号になる。このフラットな部分の時間幅は、入
力信号の変化レベル(U)とフィー ドパツクループの
時定数(A)によって決定される。以上の振幅制御回路
9の出力信号を前記入力信号aから減算回路10で減じ
て、出力端子11からは第6図dに示すような時刻t1
以降において微小な高周波の雑音が除去された信号が出
力される。
The conventional noise removal apparatus configured as described above will be explained below using the operating waveform diagram of FIG. Here, for simplicity, as an input signal, 1=
It is assumed that a step confidence that changes from 0 to level U is used, and that minute level high frequency noise is superimposed on this. When this signal a is input to the input terminal 1, the output of the differential circuit 2 outputs a signal in which noise is superimposed on the J-like impulse signal shown in FIG. This signal passes through a feedback loop composed of a delay circuit 6, a multiplier circuit 6, and an adder circuit 7, and then is input to the amplitude limiting circuit 9 by a certain time constant (in this case, the multiplier circuit 70) as shown in FIG. (Determined by multiplier A)
A signal in which noise is superimposed on a signal that converges to a signal level of 0 is input. The amplitude control circuit 9 applies an amplitude limit to the portion of the signal C that exceeds a predetermined signal level (now assumed to be BV), so its output is 6. It becomes a flat signal at level BV between 1 and tlt. The time width of this flat portion is determined by the change level (U) of the input signal and the time constant (A) of the feed pack loop. The above output signal of the amplitude control circuit 9 is subtracted from the input signal a by the subtraction circuit 10, and the output signal from the output terminal 11 is output at time t1 as shown in FIG. 6d.
Thereafter, a signal from which minute high-frequency noise has been removed is output.

発明が解決1−ようとする問題点 しかしながら」−記のような構成では、振幅制限回路9
によって振幅制限される期間(1−=O−tl)におい
てはフラットな信号となるため第5図dの」:うにその
期間の雑音は除去されない。しかも振幅制限レベルBV
たけ入力信号aから除去しエツジ部分の波形ひずみを発
生させて、この部分のS/Nを悪くしていた。また、振
幅制限回路9141力のフラットな部分を短くしようと
すれば、前述しだフィートバックループの時定数Aを小
さくすれば」=いが、時定数Aを小さくすれば前記(1
)式のHPF特性によって信号が通過する帯域がせオく
なってし捷う。捷た逆に通過帯域を広げて少しでも低域
側の雑音成分を軽減(〜で雑音除去の効果を」二けるた
めには前記時定数Aは大きくした方がよい。しかしそれ
では振幅制限回路9出力のフラット部分の期間が長くな
り、信号のエツジ部分に及ぼす影響が大きく、出力信号
がひずみやすくなるため、設計が非常に困難になるとい
う問題点を有していた。
Problems to be Solved by the Invention 1-However, in the configuration as described in "-", the amplitude limiting circuit 9
During the period where the amplitude is limited by (1-=O-tl), the signal becomes flat, so the noise during that period is not removed as shown in d of FIG. Moreover, the amplitude limit level BV
By removing this signal from the input signal a, waveform distortion occurs in the edge portion, thereby worsening the S/N ratio in this portion. Also, if you want to shorten the flat part of the amplitude limiting circuit 9141 force, you can reduce the time constant A of the feedback loop as described above.
) The band through which the signal passes becomes narrower and distorted due to the HPF characteristics of the equation. On the contrary, it is better to increase the time constant A in order to widen the passband and reduce the noise component on the low frequency side even a little (~). This has the problem that the period of the flat portion of the output becomes long, which has a large effect on the edge portion of the signal, and the output signal becomes easily distorted, making the design extremely difficult.

本発明はかかる点にかんがみ、第5図aのステップ信号
のような大レベルの信号には信号の欠除が発生せず、エ
ツジ部分の雑音除去効果も大きく、低域の雑音まで除去
しても波形のひずみが極めて小さいビデオ信号の雑音除
去装置を提供することを目的とする。
In view of these points, the present invention does not cause signal deletion in high-level signals such as the step signal shown in FIG. Another object of the present invention is to provide a video signal noise removal device with extremely small waveform distortion.

問題点を解決するための手段 本発明は入力信号の所定の時間当りの変化分を取り出す
差分回路と、差分回路出力の信号レベルが小さい時には
略比例するが信号レベルが大きい時にはその信号レベル
に応じて非線形に圧縮する非線形回路と、信号を上記所
定の時間遅延する遅延回路と、遅延回路出力に所定の値
を乗じる乗算回路と、乗算回路出力を前記非線形回路出
力に加えて前記遅延[回路に導く加算回路と、加算回路
出力を前記差分回路に入力した信号から差し引く減算N
路とを備えた雑音除去装置である。
Means for Solving the Problems The present invention includes a differential circuit that extracts a change in an input signal per predetermined time, and a differential circuit that outputs a signal that is approximately proportional to the signal level when the signal level is small, but is proportional to the signal level when the signal level is large. a delay circuit that delays the signal by the predetermined time; a multiplier circuit that multiplies the output of the delay circuit by a predetermined value; and a subtraction N that subtracts the adder circuit output from the signal input to the difference circuit.
This is a noise removal device equipped with a.

作   用 本発明は前証しだ構成に」=す、遅延回路、第1の乗算
回路、おJ−び加算回路で構成されるフィードバックル
ープへ入力される信号の振幅が制限されるために、大レ
ベルの信号に対しても信号の欠除が発生せずエツジ部分
捷で雑音除去効果があり、かつ低周波領域捷で雑音除去
を行なっても波形のひずみが少ない雑音除去を行なう。
The present invention has the configuration shown in the foregoing.Since the amplitude of the signal input to the feedback loop consisting of the delay circuit, the first multiplier circuit, and the addition circuit is limited, To perform noise removal with no signal deletion even for high-level signals, by edge partial cutting, and with less waveform distortion even when noise removal is performed by low frequency area cutting.

実施例 第1図は本発明の実施例における雑音除去装置のブロッ
ク図である。同図において、12は標本化周期Tでディ
ジタル化されたビデオ信号の入力端子、13は入力端T
−12から入力されたビデオ信号の標本化周期Tのn倍
の時間当りの変化分を取り出す差分回路で、遅延時間n
Tを有する遅延回路14と、遅延回路14の入力信号か
らその出力信号を減じる減算回路16とで構成される。
Embodiment FIG. 1 is a block diagram of a noise removal device in an embodiment of the present invention. In the figure, 12 is an input terminal for a video signal digitized with a sampling period T, and 13 is an input terminal T.
-12 is a difference circuit that extracts the change per time n times the sampling period T of the input video signal, and has a delay time n
The delay circuit 14 includes a delay circuit 14 having T, and a subtraction circuit 16 that subtracts the output signal from the input signal of the delay circuit 14.

16は差分回路13出力の信号レベルが小さい時には略
比例するが信号レベルが大きい時にはその信号レベルに
応じて非線形に圧縮する非線形回路、17は前記遅延回
路14と同じ遅延時間nTを有する遅延回路、18は遅
延回路17出力に所定の値を乗じる乗算回路、19は乗
算回路18出力を前記非線形回路16出力に加えて前記
遅延回路17に導く加算回路、20は入力端子12より
入力した信号から加算回路19出力を差し引く減算回路
、21は出力端子で減算回路20出力を雑音が軽減され
たビデオ信号として出力する。
16 is a nonlinear circuit that compresses the output of the differential circuit 13 substantially in proportion when the signal level is small, but nonlinearly compresses the signal level when the signal level is large; 17 is a delay circuit having the same delay time nT as the delay circuit 14; 18 is a multiplier circuit that multiplies the output of the delay circuit 17 by a predetermined value; 19 is an adder circuit that adds the output of the multiplier circuit 18 to the output of the nonlinear circuit 16 and leads it to the delay circuit 17; and 20 is an adder that adds signals input from the input terminal 12. A subtraction circuit 21 subtracts the output of the circuit 19, and an output terminal 21 outputs the output of the subtraction circuit 20 as a video signal with reduced noise.

また、差分回路13は簡単のため遅延回路14の遅延時
間がT(n=1)として、入力信号の1単位時間T当り
の変化分を取り出すものとし、そして遅延回路1γも捷
た信号を1単位時間T遅延するものとする。捷た乗算回
路18が信号に乗じる乗数をAとし、非線形回路16が
信号を非線形に圧縮する係数をPとする。第2図に非線
形回路16の入出力関係の一例を同図の実線で示す。非
線形回路16の人力をV□、出力をvoとすれば、係数
p fr使って■。−P・■、である。ディジタル信号
処理ではFtOMを使って任意のPを得ることができる
。第2図において破線で示す特性はPの他の例であって
、実線で示した折線近似でもある。
Further, for simplicity, the difference circuit 13 is assumed to take out the change per unit time T of the input signal, assuming that the delay time of the delay circuit 14 is T (n=1), and the delay circuit 1γ also outputs the signal which has been switched. It is assumed that there is a delay of unit time T. Let A be the multiplier by which the multiplier circuit 18 multiplies the signal, and P be the coefficient by which the nonlinear circuit 16 nonlinearly compresses the signal. An example of the input/output relationship of the nonlinear circuit 16 is shown in FIG. 2 by the solid line in the figure. If the human power of the nonlinear circuit 16 is V□ and the output is vo, use the coefficient p fr.■. -P・■. In digital signal processing, an arbitrary P can be obtained using FtOM. The characteristic shown by the broken line in FIG. 2 is another example of P, and is also a broken line approximation shown by the solid line.

この破線で示す特性は乗算回路捷たは加減算回路および
スイッチ回路を用いて簡単に得ることができる。以下、
この破線で示す折線特性を用いて説明する。折線特性は
入力V工が■1≦Vの時、係数PはBであってその出力
V。はV。−B、Viとなり、捷た■□〉■においては
■。−B・■のように一定値BVに振幅制限・される。
The characteristic shown by this broken line can be easily obtained using a multiplication circuit, an addition/subtraction circuit, and a switch circuit. below,
This will be explained using the broken line characteristic shown by this broken line. The broken line characteristic is that when the input V is 1≦V, the coefficient P is B and its output V. is V. -B, Vi, and in the switched ■□〉■, ■. The amplitude is limited to a constant value BV like -B・■.

以上のように構成された本実施例の雑音除去装置の動作
について、以下、離散時間システムを表わす2変換式と
、各部の動作波形図を用いて説明する。
The operation of the noise removal apparatus of this embodiment configured as described above will be described below using a two-conversion equation representing a discrete time system and operation waveform diagrams of each part.

捷ず、非線形回路16の信号を圧縮する係数をPとして
本実施例の伝達関数”(Z)は10゜ である。ここで非線形回路16に入力される信号、つ1
り差分回路13出力の入力端子12への入力信号に対す
る伝達関数1〜z−1はそれ自身HPFの特性を示す。
The transfer function "(Z) of this embodiment is 10°, where P is the coefficient for compressing the signal of the nonlinear circuit 16 without switching. Here, the signal input to the nonlinear circuit 16,
The transfer functions 1 to z-1 of the output of the differential circuit 13 to the input signal to the input terminal 12 themselves exhibit the characteristics of the HPF.

よって非線形回路16へは入力信号の高域成分のみが入
力される。この高域成分の信号レベルが小さい時には、
第2図に示すように係数Pは一定値Bで入力信号レベル
に比例した信号を出力する。前記(2)式において係数
Pが一定値Bならば(2)式の右辺第2項は前述(1)
式のH(7,)と同じ(HPFの特性を示すので、入力
端子12へ入力される入力信号の高域のみを減衰させる
特性を有している。しかし、非線形回路16に大レベル
の信号が入力されれば第2図のように信号の振幅を制限
して出力するので、入力信号から減じられない。以上よ
り、本実施例の雑音除去効果はビデオ信号に重畳されて
いる微小レベルの高周波の雑音を除去するが、信号とみ
なすべき大レベルの信号に対しては非線形回路16によ
って振幅が制限されるので信号にひずみを発生させない
Therefore, only the high frequency components of the input signal are input to the nonlinear circuit 16. When the signal level of this high frequency component is small,
As shown in FIG. 2, the coefficient P has a constant value B and outputs a signal proportional to the input signal level. If the coefficient P in the above equation (2) is a constant value B, the second term on the right side of the equation (2) will be the same as the above (1).
Same as H(7,) in the equation (it shows the characteristics of HPF, so it has the characteristic of attenuating only the high frequency range of the input signal input to the input terminal 12. However, if the nonlinear circuit 16 is input, the amplitude of the signal is limited and output as shown in Fig. 2, so that it is not subtracted from the input signal.From the above, the noise removal effect of this embodiment is effective in reducing the minute level superimposed on the video signal. Although high-frequency noise is removed, the nonlinear circuit 16 limits the amplitude of high-level signals that should be considered signals, so that no distortion occurs in the signals.

次に本実施例の雑音除去装置に第2図aで示す信号が入
力された場合の動作を同図の波形図を用いて説明する。
Next, the operation when the signal shown in FIG. 2a is input to the noise removal apparatus of this embodiment will be explained using the waveform diagram of the same figure.

第2図aは、従来の技術の項で説明に′使った第5図a
と同じで、時刻1=0で十分大きなレベルUに変化する
ステップ信号に微小レベルの高周波の雑音が重畳された
信号である。この信号aが入力端子12に入力されると
差分回路13出力にJ:第2図すのようなインパルス信
号に雑音が重畳された信号(前述の第6図すと同じ)が
出力される。信号すを非線形回路16は時刻j=Qで信
QレベルVを越えるインパルス状の信号をレベルBVに
圧縮し、他の微小レベルの信号を8倍1〜だ信号を後段
の遅延回路17、乗算回路18、およぎ加算回路19で
構成するフィードバックループに導いている。この時の
フィードバックループの出ブハつ1り加算回路19出力
は第3図eに示すように、信号レベルBVから時定数(
乗算回路18の乗数Aで決する)で信号レベル0に収束
する信号に雑音が重畳された信号となる。第3間借号f
は減算回路2oによって信号aから信号eが差し引かれ
た信号で出力端子21より出力される本実施例の雑音除
去装置の出力信号である。本実施例の出力信号fは、前
記従来の雑音除去装置の出力信号第5図dと比較しても
わかるように、信号のエツジ部分での信号欠除がなく、
大レベルの変化のあるエツジ間除重で微小レベルの高周
波雑音が除去できる。これは、入力信号から減算回路2
oによって減じられる信号eが時刻t−○では信号レベ
ルBVであって、その時刻(1=0)以降信号レベルO
に収束していく。これに対し、前記従来例では第6間借
号Cのように時刻を一〇では信号レベルはBUであって
、時刻1 =0以降信号レベルOにするため、入力信号
から減じられる信号は第4図振幅制限回路9に」:って
振幅制限され時刻t1tでの期間がフラットになるから
である。また本実施例では、以上の1=うなフラノ]・
な部分がないので、より低い周波数の雑音についても除
去効果を上げるために前記乗算回路18の乗数Aを大き
くしてもエツジ部分の波形ひずみが少なく、エツジ間除
重で雑音除去効果が」−げられる。
Figure 2a is the same as Figure 5a used for explanation in the prior art section.
Similarly, it is a signal in which minute level high frequency noise is superimposed on a step signal that changes to a sufficiently large level U at time 1=0. When this signal a is input to the input terminal 12, the differential circuit 13 outputs J: a signal in which noise is superimposed on an impulse signal as shown in FIG. 2 (same as shown in FIG. 6 described above). The signal non-linear circuit 16 compresses the impulse-like signal exceeding the signal Q level V at time j=Q to the level BV, and multiplies the other minute level signals by 8 times 1 to 1. The delay circuit 17 in the subsequent stage multiplies the signal. It leads to a feedback loop composed of a circuit 18 and an addition circuit 19. At this time, the output of the feedback loop from the one-by-one adder circuit 19 changes from the signal level BV to the time constant (
The result is a signal in which noise is superimposed on a signal that converges to a signal level of 0 (determined by the multiplier A of the multiplier circuit 18). 3rd lease f
is a signal obtained by subtracting the signal e from the signal a by the subtraction circuit 2o, and is the output signal of the noise removal device of this embodiment, which is output from the output terminal 21. As can be seen by comparing the output signal f of the present embodiment with the output signal of the conventional noise canceling device in FIG.
Edge-to-edge unloading with large level changes can remove minute level high frequency noise. This is the subtraction circuit 2 from the input signal.
The signal e subtracted by o is at the signal level BV at time t-○, and after that time (1=0) the signal e is at the signal level O.
It converges to. On the other hand, in the conventional example, the signal level is BU when the time is 10, as in the sixth period C, and the signal level is O after time 1 = 0, so the signal subtracted from the input signal is BU. This is because the amplitude is limited by the amplitude limiting circuit 9 in the figure, and the period at time t1t becomes flat. In addition, in this example, the above 1 = eel flanno]
Since there is no edge part, even if the multiplier A of the multiplier circuit 18 is increased in order to increase the removal effect even for lower frequency noise, the waveform distortion in the edge part is small, and the noise removal effect is improved by edge-to-edge weighting. can be lost.

以−1−のように本実施例によれば、信号レベルが小さ
い時には略比例するが、信号レベルが大きい時にはその
信号レベルに応じて非線形に圧縮する非線形回路を、入
力信号の所定の時間当りの変化分を取り出す差分回路と
、遅延回路・乗算回路お」:び加算回路で構成されるフ
ィードバックル−ヘプとの間に設けて雑音成分を取り出
すよ、う;7て雑音除去装置を構成するととにより、大
レベルで変化する入力信号に対しても、そのエツジ部分
の信号の欠除、すなわちエツジ部分のS/N劣化が発生
せずエツジ間際1でもS/N改善効果があり、かつ低周
波帯域の雑音まで除去しても波形ひずみを少なくするこ
とができる。
As described in -1- above, according to this embodiment, when the signal level is small, the nonlinear circuit compresses the input signal substantially proportionally, but when the signal level is large, the nonlinear circuit compresses the signal nonlinearly according to the signal level. A noise removal device is constructed by providing a differential circuit for extracting the change in the noise component and a feedback loop composed of a delay circuit, a multiplier circuit, and an addition circuit to extract the noise component. Therefore, even for an input signal that changes at a large level, there is no signal deletion at the edge, that is, no S/N deterioration at the edge, and the S/N improvement effect is achieved even at the very edge 1, and the signal is low. Even if noise in the frequency band is removed, waveform distortion can be reduced.

最後に、前記非線形回路16の入出力特性の一例を第2
図実線と破線で示したが、実線の非線形特性が不可欠な
ものでなく破線の折線近似特性でもよい。しかI−人力
レベルの変化に対し、圧縮するレベルが急激に変わるの
で第2図実線で示した様14・ な特性が望捷しい。
Finally, an example of the input/output characteristics of the nonlinear circuit 16 is shown in the second section.
Although the solid line and the broken line are shown in the figure, the nonlinear characteristic shown by the solid line is not essential, and the broken line approximate characteristic may be used. However, the compression level changes rapidly in response to changes in the human power level, so characteristics like the one shown by the solid line in Figure 2 are desirable.

発明の詳細 な説明したように、本発明によれば、大レベルの信号が
入力されても、エツジ部分での信号の欠除すなわちS/
N劣化が発生せず、エツジ間際まで雑音除去効果があり
、さらに低周波帯域の雑音1で除去しても波形のひずみ
が極めて少ないビデオ信号の雑音除去装置を提供するこ
とができ、その実用的効果は大きい。
As described in detail, according to the present invention, even if a high-level signal is input, signal deletion at the edge portion, that is, S/
It is possible to provide a video signal noise removal device that does not cause N degradation, has a noise removal effect right up to the edge, and has extremely low waveform distortion even when removing noise in the low frequency band. The effect is great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明における実施例の雑音除去装置のブロッ
ク図、第2図は同実施例を構成している非線形回路の入
出力関係図、第3図は同実施例の動作波形図、第4図は
従来の雑音除去装置のブロック図、第5図は第4図従来
例の動作波形図である0 12・・・・・入力端子、13・・・差分回路、14゜
17・・・・・遅延回路、16.20・・・・・減算回
路、16・・・・・・非線形回路、18・・・・・・乗
算回路、19・・・・・・加算回路、21・・・・・出
力端子。
FIG. 1 is a block diagram of a noise removal device according to an embodiment of the present invention, FIG. 2 is an input/output relationship diagram of a nonlinear circuit constituting the embodiment, and FIG. 3 is an operation waveform diagram of the embodiment. Fig. 4 is a block diagram of a conventional noise removal device, and Fig. 5 is an operating waveform diagram of the conventional example shown in Fig. 4. ... Delay circuit, 16.20 ... Subtraction circuit, 16 ... Nonlinear circuit, 18 ... Multiplication circuit, 19 ... Addition circuit, 21 ... ...Output terminal.

Claims (1)

【特許請求の範囲】[Claims] 入力信号の所定の時間当りの変化分を取り出す差分回路
と、この差分回路出力の信号レベルが小さい時には略比
例するが信号レベルが大きい時にはその信号レベルに応
じて非線形に圧縮する非線形回路と、信号を上記所定の
時間遅延させる遅延回路と、遅延回路出力に所定の値を
乗じる乗算回路と、乗算回路出力を前記非線形回路出力
に加えて前記遅延回路に導く加算回路と、この加算回路
出力を前記差分回路に入力した信号から差し引く減算回
路とを備えたことを特徴とする雑音除去装置。
A difference circuit extracts the change in the input signal per predetermined time, a nonlinear circuit compresses the signal approximately proportionally when the signal level of the difference circuit output is small, but nonlinearly according to the signal level when the signal level is large; a delay circuit that delays the above-described predetermined time; a multiplier circuit that multiplies the output of the delay circuit by a predetermined value; an adder circuit that adds the output of the multiplier circuit to the output of the nonlinear circuit and leads it to the delay circuit; A noise removal device comprising: a subtraction circuit that subtracts from a signal input to a difference circuit.
JP61112935A 1986-05-16 1986-05-16 Noise eliminator Pending JPS62269477A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61112935A JPS62269477A (en) 1986-05-16 1986-05-16 Noise eliminator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61112935A JPS62269477A (en) 1986-05-16 1986-05-16 Noise eliminator

Publications (1)

Publication Number Publication Date
JPS62269477A true JPS62269477A (en) 1987-11-21

Family

ID=14599174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61112935A Pending JPS62269477A (en) 1986-05-16 1986-05-16 Noise eliminator

Country Status (1)

Country Link
JP (1) JPS62269477A (en)

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