JPH06105861B2 - Non-linear signal processor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a non-linear signal processing device applied to a video tape recorder (hereinafter abbreviated as VTR), a video disc, or the like.

Conventional technology One of the non-linear signal processing devices is to enhance the high frequency range only when there is a large energy component in the high frequency range in order to secure the S / N ratio in the high frequency range by enhancing the high frequency range of the video signal. There is a non-linear emphasis that lowers the adverse effect of excessive emphasis. FIG. 8 shows a model diagram of a non-linear emphasis circuit. 1 is a first connection body in which a capacitor 2 and a resistor 3 are connected in parallel, 4 is a second connection body in which a resistor 8 is connected in parallel to a connection body in which a capacitor 7 is serially connected to two diodes 5 and 6 which are connected in anti-parallel Body, 9
Is an input terminal and 10 is an output terminal. Reference numeral 11 is an amplifier for adjusting the level of the output signal. In the above configuration, the capacitors 2 and 7 have capacitances C ₁ and C ₂ , respectively, and the resistors 3 and 8 have resistances R ₁ and R ₂ , respectively. At this time, C ₁ , C ₂ , R ₁ and R ₂ have a relationship of C ₁ R ₁ = C ₂ R ₂ . Next, since the current that flows in the anti-parallel connection body of the two diodes 5 and 6 changes depending on the voltage applied to both ends of the diode, the anti-parallel connection body of the diodes 5 and 6 changes from conducting state to infinity by the voltage applied to both ends. It is regarded as a variable resistance, and its resistance value is Pd. The amplifier 11 uses the reciprocal R ₁ + R ₂ / R ₂ of the coefficient R ₂ / R ₁ + R ₂ divided by the resistors 3 and 8 as the amplification coefficient in order to make the signal levels of the input signal and the output signal the same.

The operation of the above configuration will be described. First, when the signal level of the input signal applied to the input terminal 9 is sufficiently low, the voltage across the anti-parallel connection body of the diodes 5 and 6 is also small, so almost no current flows, and its internal resistance Rd is infinite. Become. As a result, the second connecting body 4 becomes equivalent to the configuration having only the resistor 8, and the example of FIG. 8 shows an emphasis characteristic that emphasizes a high frequency band like the gain characteristic of FIG. 9A. However, when the signal level of the input signal increases, the diode 5,
The voltage across both ends of the anti-parallel connection body of 6 also increases, and the current begins to flow. As a result, if the signal level of the input signal becomes sufficiently large, the current flowing through the antiparallel connection body of the diodes 5 and 6 becomes large, and the internal resistance thereof becomes conductive. Therefore, the second connection body 4 is equivalent to a parallel connection body of the resistor 8 and the capacitor 7. Here, the impedance of the second connection body 4 and the first connection body 1 is C ₁ R ₁ = C ₂ R _{2 described above.}
, The gain characteristics become constant as shown in FIG. 9B.

The above description will be given using the Laplace transform equation representing a continuous time system. Now, transfer function H (s) of the example of FIG.
If C ₁ , C ₂ , R ₁ , R ₂ and Rd are used, the following equation is obtained.

Here, X, T, and Td are defined as follows.

X = R ₁ / R ₂ (2) T = C ₁ R ₁ = C ₂ R ₂ (3) Td = C ₂ Rd (4) If the above X, T, Td are used, H ( s) is given by the following equation.

Or Now, the resistance Rd becomes infinite when the signal level of the input signal is sufficiently small, so that Td also becomes infinite according to the equation (4). Therefore, if Td is infinite in Eq. (6), then H (s)
Is as follows.

Since the second term on the right side of the equation (7) is a high pass filter, H (s) represents an emphasis characteristic that emphasizes high frequencies.
Next, when the signal level of the input signal is sufficiently high, the resistance Rd
Is zero in the conducting state, Td is also zero according to the equation (4). If Td is zero in the equation (6), H (s) = 1 (8) and the gain characteristic is flat. Becomes

As described above, the non-linear emphasis shown in FIG. 8 has a characteristic that the signal is emphasized in the high frequency range when the signal level of the input signal is low, but the degree of high frequency emphasis is reduced as the signal level of the input signal increases. It is used for VTRs and video discs to improve the S / N ratio in the high frequency range while preventing the harmful effects of excessive emphasis.

Problems to be Solved by the Invention However, in the above configuration, the flat gain characteristic as shown in FIG. 9B is a response to an input signal having an infinite signal level, and the maximum of the actual input signal is Higher frequencies are emphasized to some extent for signals at the level. Moreover, as the amount of emphasis on the input signal at a small level increases, the amount of emphasis on the input signal at the maximum level also increases, and as a result, the amount of the signal that is excessively emphasized is clipped in the subsequent stage of the nonlinear emphasis. It has a drawback that it causes an adverse effect that the loss amount increases.

In view of this point, the present invention provides a sufficient amount of emphasis for a small level input signal, but sufficiently reduces the amount of emphasis for a large level input signal to obtain a flat gain characteristic and prevent the adverse effects due to excessive emphasis, and It is an object of the present invention to provide a non-linear signal processing device which can be realized by a digital signal processing technique which is excellent in terms of integration and stability in making the device into an IC.

Means for Solving the Problems The present invention provides a differential circuit for extracting an input signal and a variation per unit time, and a signal compressed by a certain compression ratio when the amplitude of the output of the differential circuit becomes small. However, a nonlinear circuit that outputs a signal compressed at a compression ratio higher than the constant compression ratio as the amplitude becomes larger or larger, and outputs a sufficiently small or zero when the amplitude becomes larger, A delay circuit that delays the output of the non-linear circuit for a predetermined time, an adder circuit that adds the output of the delay circuit and the output of the difference circuit to the non-linear circuit, and a multiplier circuit that multiplies the output of the non-linear circuit by a predetermined value. And an adder circuit that adds the output of the multiplier circuit to the signal input to the difference circuit.

Action The present invention has the above-described configuration, in which a nonlinearly compressed signal corresponding to the amplitude level of the input signal is added to the input signal in a closed loop including a nonlinear circuit that nonlinearly compresses the time change of the input signal. The characteristic of non-linear emphasis that reduces the emphasis amount for a large signal level signal can be realized by using the digital signal processing technology which is excellent in terms of integration degree and stability in IC integration.

First Embodiment FIG. 1 is a block diagram of a non-linear signal processing device according to a first embodiment of the present invention. In FIG. 1, 12 is an input terminal for a video signal digitized with a sampling period Δ, 13
Is a difference circuit for extracting the change amount of the signal per time that is n times the sampling cycle Δ (n is an integer).
The delay circuit 14 delays a signal during Δ, and the subtraction circuit 15 subtracts the delay circuit 14 output from the delay circuit 14 input.
Reference numeral 16 is a non-linear circuit that non-linearly compresses the amplitude according to the amplitude of the signal, 17 is a delay circuit that delays the output of the non-linear circuit 16 by nΔ, and 18 is added to the output of the differential circuit 13 and the output of the delay circuit 17 and leads to the non-linear circuit 16. An adder circuit 19 is a multiplier circuit that multiplies the output of the non-linear circuit 16 by a predetermined value, and 20 is an adder circuit that adds the output of the multiplier circuit 19 to the input signal obtained from the input terminal and guides it to the output terminal 21. FIG. 2 is an input / output relationship diagram of the non-linear circuit 16, showing the relationship of the output V with respect to the non-linear circuit 16 input U. When the amplitude of U is small (U ₀ or less), the compression ratio is constant. The compression characteristic is such that V becomes zero when the amplitude of U increases and exceeds the amplitude U ₁ when compressed. The operation of the present embodiment configured as described above will be described below.

First, P is a nonlinear multiplier that determines the input / output relationship of the nonlinear circuit 16, Q is a multiplier by which the multiplication circuit 19 multiplies the signal, and the delay time of the signals of the delay circuit 14 and the delay circuit 17 is one sampling period Δ. In this case, the transfer function E (z) of this embodiment is expressed by the following equation.

Here, the nonlinear multiplier P is a constant value a when the amplitude of the input U is smaller than U _{0 according} to the input / output relation of the nonlinear circuit 16 in FIG. 2, but P becomes smaller than a as it becomes larger than U _0. And becomes zero for inputs with amplitudes greater than U ₁ . Further, the amplitude of the input U when the amplitude of the output of the non-linear circuit 16 becomes maximum is U _2, and the amplitude of the output V is V ₂ . However, since the second term on the right side of the equation (9) has the characteristic of HPF as long as 0 <P ≦ 1, the equation (9) has the characteristic of the non-linear emphasis that nonlinearly emphasizes the high frequency range depending on the signal level. It represents.

In the present embodiment having the above characteristics, the input terminal 12
At time t = nΔ <0, the signal level is zero, and time t = nΔ
The operation when a step signal whose signal level is Us when ≧ 0 is input will be described. Difference circuit for the above step symbols
The 13 outputs are Us at time t = 0 and zero at time t ≠ 0.
The output of the non-linear circuit 16 when the output of the difference circuit 13 is obtained will be described with respect to the magnitude of the signal level Us.

Since the output of the differential circuit 13 is zero at t <0, the output of the non-linear circuit 16 is also zero, and the output of the delay circuit 17 is zero at t ≦ 0. Therefore, the input of the nonlinear circuit 16 is zero at t <0,
It is Us at t = 0. Further, since the output of the differential circuit 13 is zero at t> 0, the input of the non-linear circuit 16 becomes equal to the output of the delay circuit 17 and is a signal delayed by the time Δ of the non-linear circuit 16 output.

Here, when Us <U ₀ , the output of the nonlinear circuit 16 is t = 0 and a
・ Us, and thereafter, at t = nΔ> 0 (n is a positive integer), an ^{+ 1} · Us. Since the value of a is a <1 in terms of system stability, the output of the non-linear circuit 16 has a characteristic of being attenuated a times at each time Δ, and the time constant at that time is determined by a.

Next, when U ₀ <Us <U ₁ , the nonlinear circuit 16 output is Us at t = 0.
Is attenuated P times by the multiplier P, and it can be seen from FIG. 2 that P <a. Therefore, the amount of attenuation is larger and the convergence time is shorter than when Us <U ₀ . Then, after the output of the nonlinear circuit 16 becomes smaller than the signal level U ₀ ,
Similar to the case of Us <U _0, the characteristic is such that it is attenuated by a times for each time Δ.

Finally, when Us> U ₁ , the nonlinear circuit 16 output is t
It becomes zero at = 0. Therefore, even at t> 0, the nonlinear circuit
Since only zero is input to 16, the nonlinear circuit 16 output is also zero.

As described above, the characteristic feature of this embodiment, which has the non-linear circuit 16 having the input / output relationship as shown in FIG. 2, is the emphasis characteristic emphasized in the high frequency range for a minute level signal. As the signal level increases, the amount of emphasis is compressed, and signals with a higher signal level are hardly emphasized in the high frequency range. This feature is the non-linear emphasis characteristic used for signal processing of VTRs and video discs. (For large signal level, the amount of emphasis is compressed to improve the S / N in the high range while preventing the adverse effects of excessive emphasis. It can be said that the characteristics are more suitable than the characteristics described in the above-mentioned conventional technique.

That is, the non-linear emphasis characteristic has a frequency characteristic in which a high level is emphasized as shown in FIG. 9A for a minute level signal, but for a large signal level signal by a clipping device or the like placed after the non-linear emphasis. In order that the amount of emphasis is not clipped as an excessive component, a non-emphasized characteristic as shown in B of FIG. 9 is also necessary. However, in the above conventional technique,
An infinite signal level is required to obtain the characteristics shown in FIG. B, and in reality, even a signal having the maximum amplitude as an input signal is emphasized in a high frequency range and becomes an excessive emphasis. Is. In this embodiment, the point is that the nonlinear circuit
By setting the input / output relationship of 16 as shown in FIG. 2, it is possible to prevent excessive emphasis by adjusting U ₁ in the figure according to the dynamic range of the input signal.

As described above, according to this embodiment, the time change of the signal obtained by the difference circuit 13 is nonlinearly compressed by the signal level in the closed loop configuration including the nonlinear circuit 16 having the input / output relationship as shown in FIG. By adding it to the input signal by the adder circuit 20, it is possible to realize a characteristic that more effectively prevents excessive emphasis than the conventional non-linear characteristic by the digital signal processing technique.

FIG. 3 is a block diagram of a non-linear signal processing device showing a second embodiment of the present invention. The configuration of FIG. 3 is obtained by providing an amplitude limiting circuit 22 as shown in FIG. 3 to the difference circuit 13 in FIG. 1 showing the configuration of the first embodiment. In FIG. 3, the amplitude limiting circuit 22 limits the signal level of the output of the subtracting circuit 15, and can reduce the input / output dynamic range of the adding circuit 18 and the input dynamic range of the non-linear circuit 16 in the subsequent stage. . The operation will be described below.

From FIG. 2, the maximum signal level of the output V of the nonlinear circuit 16 is
Since it is V ₂ , the maximum output of the delay circuit 17 is also V ₂ .
Further, from FIG. 2, the signal level of the input U of the nonlinear circuit 16 is
When U exceeds ₁ , the output V becomes zero, so the output of the adder circuit 18 which is the output of the delay circuit 17 and the output of the difference circuit 13 is the signal level.
When U ₁ is exceeded, the output of the nonlinear circuit 16 is always zero. Since the maximum level of the output of the delay circuit 17 is V ₂ , the output of the non-linear circuit 16 is always zero when the signal level of the output of the differential circuit 13 exceeds U ₁ + V ₂ . Therefore, the output dynamic range of the difference circuit 13 is not required to be U ₁ + V ₂ or more.

As described above, according to the present embodiment, by providing the amplitude limiting circuit 22 in the difference circuit 13, the input / output dynamic range of the adder circuit 18, and especially the input dynamic range of the nonlinear circuit 16 can be reduced without changing the characteristics. Because you can
The device can be realized with a very small circuit scale.

FIG. 4 is a block diagram of a non-linear signal processing device showing a third embodiment of the present invention. In the configuration of this embodiment, in the configuration shown in FIG. 1, the nonlinear circuit 16 and the multiplication circuit 19 have two or more different compressions such as 16a, 16b, ... As shown in FIG. One of the characteristics can be switched and selected, and the multiplication circuit 19 also has 19a, 19b,
It is possible to switch and select one of two or more different multipliers like ……. The operation will be described below.

The transfer function E (z) of the first embodiment of FIG. 1 has already been described in the equation (9). From the equation (9), it can be seen that E (z) representing the characteristic of non-linear emphasis is determined by the nonlinear multiplier P of the nonlinear circuit 16 and the multiplier Q of the multiplication circuit 19. Therefore, it is effective that one compression characteristic and a multiplier can be selected from two or more compression characteristics (P) and a multiplier (Q) as in the present embodiment because it can be easily executed without changing the configuration of the device. . In particular, when the signal processing unit is integrated into an IC in a VTR or the like, if the characteristics of the non-linear emphasis or the sampling period must be changed because the video signal system is changed between NTSC and PAL, the same configuration and the same IC non-linear circuit 16, multiplication circuit 19
It is very effective in terms of circuit scale because it can be used by simply switching.

Further, in the difference circuit 13 of the present embodiment, the difference circuit of FIG.
Providing the amplitude limiting circuit 22 like 13 is effective because it can reduce the circuit scale of the adding circuit 18 and the non-linear circuit 16 (16a, 16b, ...) In the subsequent stage, which is effective in the second embodiment. Since it is equivalent to the one explained, it is not explained here.

FIG. 5 is a block diagram of a non-linear signal processing device showing the embodiment of FIG. 4 of the present invention. In the figure, the same components as those in FIG. 4 are designated by the same reference numerals and their description is omitted.
The difference is the arithmetic operation circuit 23, which has an addition function (addition circuit 23a) for adding the input signal obtained from the input terminal 12 and the output of the multiplication circuit 19 and a subtraction function (subtraction circuit 23b) for subtracting the output of the multiplication circuit 19 from the input signal. ) Has two functions, the output can be selected by switching these two functions. Further, the nonlinear circuit 16 and the multiplication circuit 19 need to have two respective characteristics and multipliers, such as 16a and 16b and 19a and 19b. The operation will be described below.

First, the nonlinear multiplier of the nonlinear circuit 16a is P, and the nonlinear circuit 1
The nonlinear multiplier of 6b is P ', the multiplier of the multiplication circuit 19a is Q, and the multiplier of the multiplication circuit 19b is Q'. The input / output relationship of the non-linear circuits 16a and 16b is as shown in FIG. When P, P ′ and Q, Q ′ are determined as described above, the output of the non-linear circuit 16 is set to the 16a side in FIG.
If the output of the multiplication circuit 19 is selected on the side of 19a and the output of the arithmetic operation circuit 23 is selected on the side of the addition circuit 23a, the characteristic of the present embodiment is the non-linear emphasis of the equation (9) described in the first embodiment. It becomes exactly the same as the characteristic E (z) and operates as non-linear emphasis. Next, if the output of the nonlinear circuit 16 is selected to the 16b side, the output of the multiplication circuit 19 is selected to the 19b side, and the output of the arithmetic operation circuit 23 is selected to the subtraction circuit 23b side, the characteristics (D (z)) of this embodiment are obtained. ) Is as follows.

Now, in the above configuration, a characteristic of non-linear de-emphasis, which is an inverse characteristic of the characteristic E (z) of the non-linear emphasis, will be viewed. Non-linear de-emphasis operates to restore the original signal of the signal emphasized by non-linear de-emphasis, and its characteristic is 1 /
It is represented by E (z). This 1 / E (z) is given by the following equation from the equation (9).

From the above, P ', Q' If the non-linear circuit 16b and the multiplying circuit 19b are set so that the following equation (10) to (13) is obtained, D (z) = 1 / E (z) (14) (Z) shows the characteristic of non-linear de-emphasis.

From the above description, the nonlinear circuit 16 can select two compression characteristics of P and P ', the multiplication circuit 19 can select two multipliers of Q and Q', and the arithmetic operation circuit 23 can select two functions of addition and subtraction. This is effective in that the characteristics of non-linear emphasis and non-linear de-emphasis can be obtained by switching the output of each circuit without changing the configuration of the device. Especially, when a signal processing unit such as a VTR is integrated into an IC, non-linear emphasis / non-linear de-emphasis can be realized with the same configuration, which is very effective in terms of circuit scale.

In the differential circuit 13 of the present embodiment as well, by providing the amplitude limiting circuit 22 as shown in FIG. 3, it is possible to reduce the circuit scale of the adding circuit 18 and the nonlinear circuit 16 (16a, 16b) in the subsequent stage. This is equivalent to the second embodiment. Further, if the non-linear circuit 16 and the multiplication circuit 19 can select two or more compression characteristics and multipliers as shown in FIG. It is also possible to realize the characteristics of emphasis with the same configuration.

In the above description, the present invention has been described as non-linear emphasis / de-emphasis. However, the non-linear de-emphasis is first made by the present inventors by appropriately selecting the nonlinear multiplier P ′ and the multiplier Q ′ in the equation (10). Japanese Patent Application Sho 59
It can also be used as a noise eliminator as proposed in −277106, and at this time, non-linear emphasis can be considered as its inverse correction. As a noise eliminator,
Although a minute level of high frequency component is removed as a noise component,
A high-level high-frequency component such as an edge portion of a signal has almost no attenuation, so that waveform distortion is extremely small, and there is a noise removal effect even between edges. If the nonlinear signal processing device of the present invention is used as the inverse correction, there is almost no emphasis amount at a large level, so that the inverse correction effect can be enhanced without increasing the signal loss due to clipping.

As described above, the characteristic of the non-linear circuit 16 of the non-linear signal processing device of the present invention is set so that the output is zero with respect to a large signal level as shown in FIG. 2, so that the adverse effects due to excessive emphasis can be effectively prevented. However, the characteristic of the non-linear circuit 16 does not necessarily have the input / output relationship as shown in FIG.
As shown in FIG. 6, the compression ratio may be constant up to a constant input level, and the output may be zero at higher levels, or the linear approximation of the characteristics shown in FIG. 7 may be performed as shown in FIG. The input / output relationship can be easily configured with a multiplication circuit, an addition / subtraction circuit, a switch circuit, and the like. However, in the characteristics shown in FIGS. 6 and 7, the output of the nonlinear circuit 16 changes abruptly with respect to the level change of the input signal, and the output is unnatural. It can be said that the input / output relationship as shown in FIG. 2 is desirable.

EFFECTS OF THE INVENTION As described above, according to the present invention, a digital signal processing technique is used which is capable of preventing the adverse effects of excessive emphasis on a signal of a large signal level and being excellent in the degree of integration and stability in IC integration. Since it can be realized by the above, its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a non-linear signal processing device according to an embodiment of the present invention, and FIG. 2 is a relational diagram showing the input / output relationship of a non-linear circuit constituting the non-linear signal processing device of the present invention.
FIGS. 3, 4 and 5 are block diagrams of a non-linear signal processing apparatus according to another embodiment of the present invention, and FIGS. 6 and 7 show non-linear circuits constituting the non-linear signal processing apparatus of the present invention. FIG. 8 is a relational diagram showing other input / output relations, FIG. 8 is a circuit model diagram of non-linear emphasis which is one of conventional nonlinear signal processing devices, and FIG. 9 is a gain characteristic diagram of the device shown in FIG. 13 ... Difference circuit, 14, 17 ... Delay circuit, 15 ... Subtraction circuit, 16 ... Non-linear circuit, 18, 20 ... Addition circuit, 22 ... Amplitude limiting circuit, 23 ... Arithmetic operation circuit.

Claims (6)

[Claims] 1. A differential circuit for extracting a variation of an input signal per predetermined time, and a signal compressed by a certain compression ratio when the amplitude of the output of the differential circuit is small, but the amplitude is large. And a non-linear circuit that outputs a signal compressed with a compression ratio greater than the above-mentioned fixed compression ratio as it becomes larger, and outputs a sufficiently small value or zero when the amplitude becomes larger, and the output of this non-linear circuit. A delay circuit for delaying for a predetermined time, an adder circuit for adding the output of the delay circuit and the output of the difference circuit to the nonlinear circuit,
A multiplication circuit for multiplying the output of the non-linear circuit by a predetermined value;
A nonlinear signal processing device, comprising: an adder circuit for adding the output of the multiplier circuit to the signal input to the difference circuit. 2. The non-linear circuit has two or more different compression characteristics, and the multiplication circuit has two or more different multipliers so that the different compression characteristics of the non-linear circuit and the multiplication circuit of the non-linear circuit. The nonlinear signal processing device according to claim 1, wherein different multipliers can be arbitrarily switched. 3. A difference circuit extracts a change amount of a signal per a predetermined time, and when the amplitude of the change amount is equal to or more than a predetermined value, the change amount is limited and output. The non-linear signal processing device according to claim 1 or 2. 4. A differential circuit for extracting a change amount of an input signal per predetermined time, and a signal compressed by a certain compression ratio when the amplitude of the output of the differential circuit becomes small, but the amplitude becomes large. And a non-linear circuit that outputs a signal compressed with a compression ratio greater than the above-mentioned fixed compression ratio as it becomes larger, and outputs a sufficiently small value or zero when the amplitude becomes larger, and the output of this non-linear circuit. A delay circuit for delaying for a predetermined time, an adder circuit for adding the output of the delay circuit and the output of the difference circuit to the nonlinear circuit,
A multiplication circuit for multiplying the output of the non-linear circuit by a predetermined value;
An arithmetic operation circuit for arithmetically operating the output of the multiplication circuit and the signal input to the difference circuit is provided, and the nonlinear circuit has two different compression characteristics for compressing the signal and depends on the two compression characteristics. The output can be arbitrarily switched, the multiplication circuit can arbitrarily switch the output by the two multipliers with two different multipliers, and the arithmetic operation circuit inputs the output of the multiplication circuit and the difference circuit. A nonlinear signal processing device, characterized in that an addition function for adding a signal and a subtraction function for subtracting the output of the multiplication circuit from the signal input to the difference circuit can be arbitrarily switched between the two functions. 5. Among two compression characteristics of a non-linear circuit, two multipliers of a multiplication circuit, and two functions of an arithmetic operation circuit,
One of the characteristics of the device when the compression characteristic, the multiplier, and the function are combined, and the other characteristic of the device when the compression characteristic, the multiplier, and the function are combined are opposite to each other. The non-linear signal processing device according to claim 4. 6. A difference circuit extracts a change amount of a signal per a predetermined time, and limits the amplitude of the change amount when the amplitude of the change amount is equal to or more than a predetermined value. The nonlinear signal processing device according to claim 4 or 5, wherein: