JPS60163749U

JPS60163749U - Molded dual inline package cage

Info

Publication number: JPS60163749U
Application number: JP3875885U
Authority: JP
Inventors: ロバート　マーク　ステイツト
Original assignee: バアー‐ブラウン　リサーチ　コーポレーシヨン
Priority date: 1979-08-30
Filing date: 1985-03-18
Publication date: 1985-10-30

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１Ａ図及び第１Ｂ図は各々本考案の前提となるモール
ド式デュアルインラインパッケージを示す（半導体又は
集積回路チップなしで）上面図及び側面図、第２図は第
１Ａ図の２−２線に沿ったＤＩＰパッケージの断面側面
図であり、半導体又は集積回路チップを一緒に示した図
、第３図は第２図に類似しているが、両側に空胴を有す
るパッケージの例を示す図、第４図は第３図に類似して
いるが両側に空胴を有するＤＰＩを示す図であり、下部
空胴にエポキシを充填したところを示した図、第５図は
本考案の一実施例としてのＤＩＰを示した図であり、下
部空胴に基体及びエポキシを装填し　　　　′たところ
を示した図、そして第６図は第３図に類似しているが、
両側に空胴を有する別の例を示した図であり、下部空胴
に基体を実質的に装填したところを示した図である。２・・・筐体、４・・・外部導電性リード、６・・・内
部導電性リード、８・・・空胴、１０・・・支持プレー
ト（リードフレームフラグ）、１２・・・半導体又は集
積回路チップ、１６・・・カバー、１８・・・下部空胴
、２０・・・カバー、２２・・・第２の半導体又は集積
回路チップ、２６・・・エポキシ樹脂、２８・・・絶縁
材基体。　　　゛ｌｌ　　　　　　　　１１ｉＬ−一一一一」ｉ1A and 1B are a top view and a side view, respectively, of a molded dual-in-line package (without a semiconductor or integrated circuit chip) that is the premise of the present invention, and FIG. 2 is a line 2-2 in FIG. FIG. 3 is a cross-sectional side view of a DIP package taken along the side, together with a semiconductor or integrated circuit chip; FIG. 3 is similar to FIG. 2, but shows an example of a package with cavities on both sides; Figure 4 is a diagram similar to Figure 3, but showing a DPI with cavities on both sides, with the lower cavity filled with epoxy; Figure 5 is an embodiment of the present invention; Figure 6 is similar to Figure 3, but shows the lower cavity loaded with substrate and epoxy;
FIG. 7 shows another example with cavities on both sides, the lower cavity being substantially loaded with a substrate; 2... Housing, 4... External conductive lead, 6... Internal conductive lead, 8... Cavity, 10... Support plate (lead frame flag), 12... Semiconductor or Integrated circuit chip, 16... Cover, 18... Lower cavity, 20... Cover, 22... Second semiconductor or integrated circuit chip, 26... Epoxy resin, 28... Insulating material Base.゛ll 11 iL-１１１１”i

Claims

[Scope of utility model registration request]

In a molded dual in-line part housing having at least one circuit made of at least one semiconductor chip and having a first and second main surface,
at least one cavity in the first major surface, a first plurality of external conductive leads, and a second cavity connected to the first plurality of leads and accessible from within the at least one cavity. a plurality of can conductive leads; and support means within said housing and forming a lower surface of said at least one cavity, said lower surface having said at least one circuit mounted thereon; The means comprises a ceramic substrate on which a passive circuit is arranged, and at least one of the above
one circuit electrically connected to the second plurality of leads, and further comprising a first cover means for sealing the at least one circuit in the at least one cavity. package.