JPS60162325A - Multiplex control circuit - Google Patents

Abstract

PURPOSE:To obtain a simple and small multiplex control circuit by combining an exclusive OR circuit, a shift register and a latch circuit. CONSTITUTION:Phenomenon data 1-n are multiplexed with time division by AND circuits 3(1)-3(n) and supplied to an input terminal at one side of an EOR circuit 7 via an inverter circuit 4. While the n-th output of a shift register circuit 8 of (n) bits is connected to an input terminal of the other side of the circuit 7. The output of the circuit 8 is connected to the input of an n-bit latch circuit 9, and the contents of the circuit 8 are latched by the circuit 9 when the n-th input is completely supplied to the circuit 8. Thus it is possible to obtain a simple and small multiplex control circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a multiplex control circuit that monitors whether or not an event occurs from a plurality of circuits. The present invention relates to a control circuit for inverting data corresponding to the plurality of circuits.

(b) Background of the technology Information sent from multiple terminals through multiple lines is collected via multiple corresponding circuits.

In a system where a certain amount of information is stored in a plurality of corresponding storage elements, converted, and transferred through a digital transmission line, how to determine whether a certain amount of information is stored and can be transferred. , constantly monitor changes in events in multiple circuits (for example, changes in whether or not information is sent to the relevant circuit), and if there is a change in events, display the previous display data for that circuit. Transfer a certain amount of information by reversing it (for example, by reversing the display data of “θ” to display data of “1”, display data of 1, for example, 0” indicates the end of information transfer or the transfer is not possible) , information can be transferred for display data of “1”)
do.

Although the above-mentioned circuits have already been realized with various circuit configurations, there is a demand for practical use of more efficient circuit configurations that utilize the latest circuit technology 9, especially the latest integrated circuits.

(c) Problems with the prior art Next, with reference to two drawings, we will explain a prior art technique that monitors the occurrence of events from multiple circuits and inverts the data corresponding to the circuits each time the event occurs. do.

FIG. 1 is a conventional multiplex control circuit diagram, in which (A) shows a circuit diagram of Example 10, and (B) shows a circuit diagram of Example 2.

In the figure, 1 (1) to 1 (n), 5 (1) to
5(n) is an AND circuit, and 2(1) to 2(n) are flip-flop circuits (hereinafter abbreviated as F and F circuits).

3 (1) to 3 (n) are NAND circuits (hereinafter NAN
(abbreviated as D circuit), 4 represents an inverter circuit, and 6 represents a selection circuit, respectively.

FIG. 1 shows a multiple control circuit of n circuits, and FIG. 1(A) shows an F circuit that receives the occurrence of an event from each circuit with an individual clock pulse, and is installed corresponding to each circuit.

This is a method of inverting F circuits (2<1) to 2(n)), and Figure 1 (B) aggregates the occurrence of events from each circuit in a time-sharing manner, and in the 2-inversion circuit, the events corresponding to each circuit are This is a method of inverting the F and F circuits [2(1) to 2(n)] installed corresponding to each circuit using a clock pulse generated at a time position.

In the above two conventional methods, different clock pulses are used for each circuit, so as the number of target circuits increases, the number of control circuits such as F and F circuits (2<1) to 2 (n)) increases. There was a drawback.

(d) Object of the Invention The object of the present invention is to provide a novel multiplex control circuit that eliminates the above-mentioned drawbacks, and particularly to realize a multiplex control circuit that is compact and can have a simple circuit configuration.

(e) Structure of the Invention The present invention is a multiplex control circuit that monitors the occurrence of an event from a plurality of circuits and inverts data corresponding to the circuit each time the event occurs.

receiving the occurrence of the event from the plurality of circuits in a time-sharing manner;
An n-bit latch circuit is provided which inputs the input to the shift register via the exclusive OR circuit, returns the final output of the shift register to the exclusive OR circuit, and holds n outputs of the shift register. This can be achieved using a multiplex control circuit, which is characterized by its small size and simple circuit configuration.

(f) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 2 shows an embodiment of a multiplex control circuit diagram according to the present invention.

In the figure, 7 is an exclusive OR circuit (hereinafter abbreviated as EOR circuit), 8 is a shift register circuit, 9 is a latch circuit, and 10 is an inverter circuit. Note that the same symbols as in FIG. 1 indicate the same contents.

In this embodiment, a NAND circuit 3 (1) to 3 is installed corresponding to a line and monitors event changes in the corresponding line and outputs event changes in a time-sharing manner in response to clock pulses from a selection circuit 6.
(n), NAND circuit 3 (
1) to 3 (n) Inverter circuit 4 which changes the polarity of the output and outputs it to the EOR circuit 7. N from common clock pulse
AND circuit 3 A selection circuit 6 that selectively outputs clock pulses shifted at regular intervals corresponding to (1) to 3 (n)
．． Is it an EOR circuit that can obtain an output “1” only when there is one state “1” among the two input terminals (the input terminal for the output signal of the n-th terminal of the inverter circuit 4 and the shift register circuit 8)? , E.O.
A shift register circuit 81 stores outputs corresponding to the circuits of the R circuit 7 while sequentially shifting them in accordance with clock pulses; a launch circuit 91 holding outputs of the shift register circuits 8 corresponding to the circuits; a selection circuit 6; The inverter circuit 1o changes the polarity of the n-th clock pulse and outputs it to the latch circuit 9.

Next, the operation of this embodiment will be explained.

Event data from each circuit (corresponding to NAND circuits 3(1) to 3(n)) is selected by pulses from the selection circuit 6, which is sequentially supplied to each circuit at regular intervals, and is sent to the oven collector gate circuit (NAND circuit 3(n)). 3 (1)~3(
n)), and is supplied to one input terminal of the EOR circuit 7 via the inverter circuit 4 via one line.

The other input terminal of the FOR circuit 7 is connected to the n-th output of the n-bit shift register circuit 8. This allows f! When event data (for example, state "1") of the i-th circuit (NAND circuit 3(i)) is supplied to one input terminal of the OR circuit 7, the EOR circuit 7
The other input terminal of the circuit is configured so that the previous event data of the i-th circuit (NAND circuit 3(i)) is supplied. For example, if the previous event data is in the state "0" and the state "1" is supplied as new event data, the EOR circuit 7 will store the state "1" in the i-th state.

Also, if the state “0” is supplied as new event data, [
! The OR circuit 7 stores the state "0" in the i-th state.

The output of the shift register circuit 8 is sent to an n-bit launch circuit 9.
connected to human power, and the nth input is the shift register circuit 8
When the input is completed, the nth clock pulse of the selection circuit 6 is inputted via the inverter circuit 10 so that the contents of the shift register circuit 8 are launched into the latch circuit 9.

(g) Effects of the Invention According to the present invention as described above, it is possible to provide a multiplex control circuit that is economical, reliable, small, and capable of a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 shows a conventional multiplex control circuit diagram, and FIG. 2 shows an embodiment of the multiplex control circuit diagram according to the present invention. In the figure, 1 (1) to 1 (n), 5 (1,)
~5 (n) is an AND circuit, 2 (1) ~2 (n)
is F. F circuit, 3 (1) to 3 (n) are NAND circuits, 4
, 10 is an inverter circuit, 6 is a selection circuit, 7 is an EOR circuit, 8 is a shift register circuit, and 9 is a latch circuit.

Claims (1)

[Claims] Monitoring the occurrence of events from a plurality of circuits. A multiplex control circuit that inverts data corresponding to the circuit each time the event occurs, and receives the occurrence of the event from the plurality of circuits in a time-division manner, and transfers the data to the shift register via an exclusive OR circuit. Enter. A multiple control circuit comprising an n-bit latch circuit that returns the final output of the shift register to the exclusive OR circuit and holds n outputs of the shift register.