SU1332384A2 - Buffer storage unit - Google Patents

Abstract

The invention relates to computing and digital automation and can be used to interface computing devices of various speeds between co. battle and input-output devices in the interfaces of computing systems and (L with co 1 hE CO 00

Description

logic analyzers. The purpose of the invention is to expand the area of application through asynchronous writing and reading of data. The device contains serially connected information registers 1, each of which is controlled by signals from the bit outputs of the reverse shift register 2 control and signals from the subsequent register, indicating whether it stores information or not. The device works in two modes. In the first mode, the First In Enter mode - the first one enters data coming in from the signals from inputs 14 to the first register and automatically moves in the direction of the last one to the first occupied register data. The reading is performed from the last register by the read signals input to input 15.

one

The invention relates to computing and digital automation, can be used for interfacing computing devices of various speeds between themselves and input-output devices in computer systems and logic analyzers and is an improvement of the device by author. - St. No. 1138835.

The aim of the invention is to expand the field of application of the device by allowing asynchronous writing and reading of data.

Figure 1 shows the scheme of the buffer storage device; 2 is a time diagram of the operation when the signals of the Loading device are received one by one by the device, while the Loading and Unloading signals and the Unloading signal are received simultaneously; FIG. 3 is a timing diagram of the operation when a signal arrives. Discharging until the end of the signal. Loading and performing these operations in turn; figure 4 is an example of the implementation of the information register.

The buffer device contains information registers 1, the reversible shift shift register 2 of the control, the first second mode of operation — buffer mode — sets the depth of buffering at inputs 22 of the code of the depth of buffering using a signal at input 13. Data is recorded into the first register by signals at input 14. With each by signal, the entire data array is shifted towards the last register. The reading is made from the last register by signals 15. With the read-like signal from the read, the entire data array shifts towards the last register. Elements 5, 6, 23, and 24, elements 3, 4, 27, and 28, elements 7, 8, 29, and 30, delay elements 33 and 34, and triggers 31 and 32 provide the possibility of independent synchronous handling in write and read modes. data. 4 il. 1 tab

the second and second elements are OR 3 and 4, the first and second elements are AND 5 and 6, the first and second elements are NOT 8, the group of information inputs 9, the control output 10 of the device, the output 11 of the load signal of the device, the first information input 12 of the device, input 13 write the buffer depth code, write signal input 14, read signal input 15, group of information outputs 16, write response signal output 17, device release signal 18 output, second device information informa- tion 19, input 20, initial setting; output 21 of the answer signal when reading, gr ppu inputs 22 code-depth buffering, the third, fourth, fifth and sixth elements And 23 - 26, the third and fourth elements OR 27 and 28, the fourth and third elements NOT 29 and 30, the first and second triggers 31 and 32 and the first and the second elements 33 and 34 of the delay.

5 The group of information inputs 9 (Fig. 1) was the input of the sequence of connected information registers 1, and the group of information outputs 16 - the output of the chain of information registers 1. The first synchronization input of each, kro3

The latter, information register 1, is connected to the control output of the next information register, and the last one in the chain is connected to the inverse output of trigger 32. These links serve to propagate the information advance signal along the chain of information registers 1 (when reading data) . The second synchronization input of each information register 1 is connected to the output of the corresponding bit of the reverse shift register 2 of the control.

Using these communications, control register 2 sets the operation mode of each information register 1: transmission of information at logical O at the second synchronization inputs of information registers 1 or recording (latching) of current information when logical one appears at these inputs 1. If there is a logical level 1 At the second synchronization input of the information registers, the recording of information from the inputs of the registers is permitted on the negative edge of the signal at the first synchronization input. The control output of the first information register 1 in the chain is the control output 10 of the device.

The outputs of the first and last bits of control register 2 are, respectively, the output 11 of the device load signal and the output 18 of the device release signal and serve to indicate the load of the device. The first and second inputs of the mode setting of the control register 2 control its operation, which is determined in accordance with the table.

The first and second inputs of the control register mode 2 control are connected respectively to the element outputs.

ten

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Commands OR 3 and 4, the first inputs of which are connected to input 13 of the entry for the code of the buffering depth, which allows register 2 to be set to parallel write code from input 22 (the fifth input of control 2). The signal paths to the second inputs of the OR elements 3 and 4 from the outputs of the flip-flops 31 and 32 through the elements NOT 7 and 8 and AND 5 and 6 ensure that no more than one single signal is fed to the first and second inputs of the control register 2 for any combinations of signals on the outputs triggers 31 and 32.

With the simultaneous receipt of single signals from the outputs of the flip-flops 31 and 32 and with a zero signal on. at input 13 Ma, the first and second inputs of control register 2 are received, which corresponds to the No operation mode (table). The third and fourth inputs of control register 2 are connected respectively to the first 12 and second 19 25 information inputs of the device and serve for sequential input to control 2 register 1 (right through input 19) or O (to the left through input 12). . .

The fifth, double and seventh inputs of the reverse shift register 2 control are the inputs of the parallel recording of information, synchronization and initial register setup, respectively, and are connected to the group 22 of the device buffering depth code inputs, the output of the delay element 34 and the initial setup input 20.

Triggers 31 and 32 are designed to fix the signs of respectively writing and reading data for the duration of the corresponding operations.

The delay element 33, the output of which is connected to the trigger inputs of the triggers, forms the time interval T1 necessary to provide the preset time for the triggers.

The delay element 34 forms the time interval T2, which provides the time for presetting the signals at the inputs of the register mode setting 2 with respect to the signal at its synchronization input, and together with the delay element 33, the time required for the information to pass through all information registers in the recording mode, and required to propagate the advance signal in30

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formations in reading mode through all registers, starting with the last one, i.e. the time required for rewriting information in each of the information registers 1 (promotion information in the device one step to the right). The last two conditions provide a guaranteed recording of information or its promotion for all information registers with any degree of filling of the buffer storage device.

Elements 23 and 24 through the element OR 27 and the element 33 of the delay provide the formation of the synchronization signal at the inputs of the flip-flops 31 and 32 when it enters, any of the inputs 14 and 15 of the device signals Load30

3S

ka / Unloading

the signals at the outputs of the element are HE 29 and 30 and the output 18 of the device, or when the signals at the inputs 14 and 15 of the device are removed and the prohibitive signal levels are removed. The OR 28 element provides the formation of a logical 1 signal at the input of the delay element 34 when any of the flip-flops 31 or 32 is switched to the logical 1.

Elements 25 and 26 provide the formation of response signals according to the coincidence of the presence of signs, respectively, of writing and reading at the outputs of the flip-flops 31 and 32 and the signal at the output of the delay element 34, which ensures the generation of response signals only 1 after the corresponding operation is performed by the device.

The buffer storage device operates in two modes: the First mode entered and the first one left with filling, starting with the output information register, and the information was advanced as it was being read and the buffer mode with programmable buffering depth.

When the device I is operating in the First-In mode, the first one has entered. went to the input 13 of the buffering depth code entry and the first information input 12 is fed a zero signal, a. on the second information input 19 - single.

The operation of the device begins with the input to input 20 of the initial installation of a short signal of logic O, after which a signal of logical 1 is set at this input. At the same time, all of the bit outputs of the register

The low level signal at the first bit of the output of register 2 is inverted by the element HE 29 and enables

and enable levels .x, Q

element and 23.

The low level signal from the last bit output of register 2 prevents the discharge signal from passing through AND 24.

The device is ready to write data, the write and read signals must be supplied to the corresponding inputs of the device at a logical level of I. The sequence of signals is illustrated by time diagrams (Figures 2 and 3).

The recording signal is applied to the input 14 of the device not earlier than the corresponding supply. information per group of 9 information inputs. devices. When information arrives at a group of 9 information inputs of the device, the chain of information registers 1 translates it into a group of 16 outputs.

The logical 1 signal at the device input 14 permits the recording of logical 1 to the trigger 31. Since the remaining inputs of the AND 23 element have a logic level of 1, the download signal enters through the AND 23 elements, OR 27 to the input of the delay element 33. The delayed signal writes logical 1 to the trigger 31, the trigger remembers the indication of the load operation. The signal of logical 1 through the elements And 5, ШШ 3 arrives at the first input of the register mode 2 setting, which corresponds (table) to the left shift mode of the control register 2.

SIGNSHS logical 1 from the output of the trigger .31 enters. Through the element OR 28 and the element 34 of the input delay

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2, logical signals O must be set, allowing information to pass through all information registers 1. In the initial state, the input 20 of the device must have a logical level 1, inputs 14 and 15 and outputs 17 and 21 must have a zero level O, while Triggers 31 and 32 are set to zero, the outputs of the elements And 23 and 24 and OR 27 and 28, the elements 33 and 34 of the delay should be the level of logic O, and 15 outputs of the elements 29 and 30 - the level of logic 1.

The low level signal at the first bit of the output of register 2 is inverted by the element HE 29 and enables

register synchronization 2. Register 2 shifts logical 1 from input 19 to the last digit, thereby switching the last information register to the record (latching) mode. At the same time, the logical I output signal of the delay element 34 permits the output of response signals and the logic signal 1 from the output of the trigger 31 is fed to the input 17 of the response during recording. The signal of logical 1 from the output of cell element 34 is furthermore inverted by the element NOT 30 and prohibits the passage of the signal through element 23, the output of which generates a signal, logical O, which causes the appearance of logical o at the output of element OR 27, and at intervals time T1 - at the output of the element 33 of the delay.

After the response signal appears when recording at output 17, the recording signal of loading at input 14 can be. take off

When the recording signal is reset, the trigger 31 is set to the initial state and, accordingly, at the output of the element OR 28 and at a time interval T2, the logical O is set at the output of the delay element 34, and the logical output

Hill

I. .

The latter provides a resolution level at the inputs of elements 23 and 24.

Since the last bit output of the control register 2 after the download operation for wils logic level 1, then at two and three inputs of the elements 23 and 24 there is a logical level I that allows the signal to pass from both input 14 and input 15. So after the first write operation, the device is ready both to write the next information word and to read the written information word.

Data recording can be continued by repeating the described procedure until all registers are filled. For each subsequent record, logical 1 is shifted in register 2 by one step to the left, alternately filled once

The rows of register 2 and latch in the information registers 1 corresponding to these bits.

20

IQ 5 records from

A full load of the buffer corresponds to the presence of memorized information in each of the information registers 1. At the same time, on all of the bit outputs. In the register control 2, a logic level I is present. The logic level 1 from the first bit output enters the load signal of the device BSRSOD 11 and, through the element NOT 29, blocks the execution of subsequent write operations (the signal O from the output of the element NOT 29 prevents the signal from passing

input 14 through the elements AND 23 i OR 27 ,. element 33 of the input delay trigger trigger 31). The write response signal in this case, in response to the receipt of a load recording signal, is not issued until the release of the first information register 1.

When a reading signal arrives at input 15, it allows writing logic 1. into trigger 32 and arriving at one of the inputs of element AND 24. If by this time point at the other inputs of element AND 24 there is a logic level 1, then the signal

0 unloading through the element OR 27 is fed to the input of the element 33 of the delay. The delayed signal records logical 1 to trigger 32. A level difference at the inverse output of trigger 32 arriving at the first synchronization input of the last information register 1 initiates recording of information from the output of the previous register into this register and a new information comes to the group 16 outputs of the device (if it is written before reading in the previous register).

five

0

The signal from the first synchronization input of the last information register 1 is transmitted to its control output and, accordingly, to the first synchronization input of the previous information register 1 connected to it. Spread this way along the chain from the last to the first information register, this signal performs a sequential rewrite information in each information register from the previous one. After passing the signal through all information registers 1, at the second synchronization input of which there is a logic level 1, information in

91

The device will be shifted to the din step toward the exit 16.

The logical 1 signal from the direct output of the trigger 32 is fed through the OR element 28 to the input of the delay element 34 and AND 6, OR 4 elements to the second input of the control register mode 2, which corresponds (table) to the right shift control register 2. Through the delay element 34, the logical 1 signal arrives at the synchronization input of control register 2 and sequentially shifts the code at its bit outputs one step to the right. The leftmost (figure 1) bit output of register 2, which had a logic level 1, switches in O, and the corresponding information register switches to transmission of information.

At the same time, the signal of logical 1 from the output of the delay element 34 allows the passage of the signal of logical 1 from the direct output of the trigger 32 through the element 26 to the output 21 of the response when reading and through the element 30 does not prohibit the passage of the signal through the elements 23 and 24 at the output of the element 24 , respectively, a logical O appears at the output of the OR element 27, and after a time interval T1 a logical o appears at the output of the output of the delay element 33.

After the occurrence of the unloading acknowledgment signal at the output 21, the unloading signal at the input 15 can be removed, after which the trigger 32 returns to its original state, the outputs of the OR element 28 and a logical time is set at the output of the element 34 , and the output element is NOT 30 - logical 1.

The latter provides: I allow -: a level at the inputs of elements And 23 and 24. The device is ready for the next operation.

Read operation M5) zhet. repeat until the last bit of the output of control register 2 has a logic level O, i.e. until the last information register is switched to the information passing mode. In this case, the logic level O from the last bit output of the control register 2 will go to the output 18 of the device

ten

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It will also prohibit the passage of the following readout unloading signals through the .EI element 24 until the last information register is written to the last information register 1, i.e. until at the corresponding output of the control register 2 there is a LESS1 logical level 1. The read response signal when the read signal arrives at the fully freed device will not be output until at least one information word is loaded.

In the proposed device, the signals of loading and unloading can come independently from each other at arbitrary points in time.

If the second time from the read and write signals on the inputs to the device inputs is until the moment of recording the signs of the operation in the triggers 31 and 32, i.e. before the appearance of the logical 1 signal at the output of delay element 33 25, the logic level 1 is written to both triggers only if the device is not fully loaded and not completely unloaded. In the reverse cases, only one operation is performed — read or write, respectively. Since the signal of logical 1 is interlocked by the elements HE7 and 8 and I5 and 6, then the combination 00 is set at the inputs of the job of the register mode 2 control — there is no operation (table).

The synchronization signal from the output of delay element 34 does not change the state of control register 2. The device will shift the recorded information by one bit and both response signals will be issued. The newly received information will be written to the leftmost (LF) information register, at the second synchronization input of which there is a logic level 1, and on the group of 16 outputs there will be a change of information.

If the second time from the write and read signals on the inputs of the device after the recording of the indication of the operation in the triggers 31 and 32, then the first one performs the operation whose signal arrived at the input of the device first. Since the synchronization signal arrives at the trigger inputs through the element OR 27, repeated recording into the triggers cannot occur until the signal at the outputs is reset.

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elements And 23 and 24, which is carried out at the end of the first of the operations, i.e. the formation of a corresponding response signal and, accordingly, a logical O signal at the output of the HE element 30.

The execution of the second operation is allowed after the removal of the signal of the first operation, respectively, the appearance of the logical 1 at the output of the element 30.

To organize the operation of the device in the buffer mode with a programmable buffering depth, it is necessary to use the connected inputs 14 and 15 as the control input.

It is first necessary to write to the control register 2 the buffer depth code from the group of inputs 22, for which a logical signal 1 is sent to the device 13, and then the logic 1 is connected to the connected inputs 14 and 15. After writing the buffer depth code at input 13 level is set again

logical o.

I-

Claims (1)

Invention Formula Buffer memory auth. St. No. 1138835, characterized in that, in order to expand the field of application by allowing asynchronous writing and reading of data, it contains the first and second triggers, the first and second delay elements, the third, fourth, fifth and sixth elements AND, the third and fourth elements OR, and the third and fourth elements are NOT, and the output of the first trigger is connected to the input of the first element NOT, to the first input of the third the first element of the fifth element AND, the output of which is the output of the recording response signal, the direct output of the second trigger is connected to the input of the second element NOT, to the second input of the fourth element OR, and to the first input of the sixth element AND, the output of which is the output of the reading response signal, in-. The output of the second trigger is connected to the control input of the last information register, the output of the fourth element OR is connected to the input of the second support element, the output of which is connected to the synchronous input of the reverse shift control register, to the second inputs of the second and sixth elements And to the third element NOT whose output is connected to the second inputs of the third and fourth elements AND, the first inputs of which are connected to the reset inputs of the first and second flip-flops respectively and are respectively the input the recording signal and the input signal of the device reading, the third input of the third element I is connected to the output of the fourth element NOT, the input of which is connected to the output of the first bit of the reversing shift control register, the third input of the fourth element I is connected to the output of the last bit of the roar: control shift register, v (moves of the third and fourth elements AND are connected to the inputs of the third OR element, the output of which is connected to the input of the first delay element, the output of which is connected to the C inputs of the first and volts cerned flops, D-inputs of which are connected to the bus / unit logic device signal. 5M.  ". Sh (n-i) JL 16  Rig. g P, .Z (lp) i {n-1f) - (llp) thirty Editor L. Gratilllo Compiled by S. Shustenko Tehred L. Serdyukova Proofreader C, Shekmar Order 3839/48 Circulation 589 Subscription INSIGHTS of the USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 FSGL