JPS60180338A - Parallel serial converting system - Google Patents

Abstract

PURPOSE:To improve the power consumption efficiency by shifting sequentially a shift register when a parallel signal of plural bits is set to the shift register and outputting selectively sequentially series signals outputted from the shift register. CONSTITUTION:Signals D1-D8 are set simultaneously to the shift register 1 by a set pulse S, signals D9-D16 are set to a shift register 2 similarly and signals D17-D24 are set to a shift register 3. The signals D1-D24 in 24-bit are set to the shift registers 1-3 while being split as parallel data in this way. A pulse P of a period T is generated from a pulse generating section 5, the pulse P is fed to the shift register 1 via a contact of a switch section 6 and fed to an octal counter 7. Since the shift register 1 is shifted sequentially by the pulse P, the signals D1-Dn are extracted serially from the output terminal A and fed to an input terminal (a) of a matrix circuit 4. Thus, the signals D1-D8 are outputted serially from the output terminal Z of the matrix circuit 4 and fed to a display section 8.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a parallel-to-serial conversion method for converting parallel data into direct data.

(b) Prior art and problems When displaying the image signal in the image memory in a bitmap display, the drawing method signal is extracted in units of predetermined (5) bits, converted into a serial tooth signal, and then displayed on the display. supply to As methods for parallel-to-serial conversion of this image signal, there is a first method that uses a shift register, and a first method that uses a shift register. After setting the N-bit image signal in a register, the image signal in the register is converted into a serial image using a multiplexer. There is a second method of converting the signal into a signal. The first method requires high-speed circuit elements constituting the soft register, and the second method has the drawback of requiring high-speed circuit elements for the registers and multiplexers.

(Ca Purpose of the Invention The present invention has been made to solve the above-mentioned drawbacks,
The purpose of this invention is to provide a parallel-to-serial conversion method that improves the power consumption efficiency of conversion circuits.

(dl Structure of the Invention The present invention provides a system for converting a parallel signal composed of N tips into a serial signal of N bits. Divide the cent 1 into the n shift registers in parallel.
- means for sequentially driving the n shift registers, a selection circuit for sequentially selecting and outputting the output signals of the n shift registers, and a control means for sequentially driving the n shift registers;
When parallel bit signals are set in the n soft registers, the n shift registers are sequentially soft-operated, and the l1fA output from the 01-fixed shift register is
This is a parallel-to-serial conversion method characterized by sequentially selecting and outputting serial signals. As described above, the present invention provides a plurality of soft registers to which N-bit parallel signals are set (
11 shift registers are provided, and output signals from the n shift registers (
By sequentially selecting and extracting serial signals (serial signals), low-speed circuit elements can be used in the selection circuit.

EXAMPLES OF THE INVENTION The present invention will now be described with reference to the drawings. The drawing is a block diagram illustrating an embodiment of the present invention.

The embodiment is an example in which a 24-bit parallel signal CDr~1)24) is converted into a serial signal. In the present invention, three shift registers (8 bits) (1), (2) and (3) are provided, and the output signals thereof are converted into serial signals using a matrix circuit (4). In the drawing, signals D1 to D are set to the shift register 1 all at once by a set pulse (period: T/2) S, and similarly, signals D and 6 are set to the shift register 2, and signals DI7 to D2 are set to the shift register 1. ．． is set in shift register 3. In this way, the 24-bit signals D1 to D7. ．． is divided and set in shift registers 1 to 3 as parallel data. Pa! A pulse P having a period T is emitted from the 4/s generating section 5, and this pulse P is sent to the shift register 1 via the contact (a) of the switching section 6, and is also sent to the octal counter 7. Shift register l becomes 1@? due to pulse P? By being softened to
Signals R, D, are taken out in series from the output terminal A and sent to the input terminal a of the matrix circuit 4. Therefore, from the output terminal Z of the matrix (b) path 4, the signal
~D8 are serially output n and sent to the display section 8. On the other hand, the counter 7 is an octal counter that counts the number of pulses P, and when it counts out, it outputs a control pulse E115.This control pulse E advances the ternary counter 9 by one step, so the matrix circuit 40 input terminal is selected and connected to its output terminal Z.
] Since the control pulse E connects the t, l part 6 to the contact center), the pulse P of the pulse generating part 5>L;) is sent to the soft resistor cedar. Along with this, shift register 2
There is a signal from the output terminal IB. -D16 is output directly and sent to the matrix circuit 40 input terminal.

Therefore, from the output terminal Z of the matrix circuit 4, the signals 1, 1, 6 are output in series and sent to the display section 8.

When the counter 7 counts out again, the control pulse E
is sent to the counter 9 and the switching section, so
The connection between the input terminal C of the bus circuit 40 and its output terminal yj is 2.
1. At the same time, a pulse P is sent to the shift register 3. Accordingly, the output terminal C of the shift register 3 outputs signals D1 to D2. are taken out in series and sent to the input terminal C of the matrix circuit 40 as a serial signal to the display section 8. As is clear from the above, the matrix circuit 4 and counter 9 in the drawings can use lower speed circuit elements than in the past.

(f) Effects of the Invention As described above, the conversion method according to the present invention can use a circuit element that operates at a relatively low speed in the matrix section which is the conversion component, so the device becomes inexpensive and
It has the advantage of reducing power consumption.

[Brief explanation of drawings]

The drawing is a block diagram illustrating an embodiment of the present invention,
The symbols used in the figure are as indicated by the arrows. J, 2.3 is a shift register, 4 is a matrix circuit, 5
1 is a pulse generating section, 6 is a switching section, 7 is an octal counter, 8 is a display section, 9 is a ternary counter, A, B. C, Z are output terminals, D, J), , D, , Halo ID17
ID24 is a signal, E is a control pulse, P is a pulse, 8 is a set pulse, T is a period, a, b, and C are input terminals, and 41 ports. C is the mouth indicating the point of contact

Claims (1)

[Claims] means for dividing a parallel signal composed of a plurality of bits into serial signals and sending them in parallel to each of the soft registers 6c; a selection circuit for sequentially selecting and outputting the output signals of the soft registers; control means for sequentially driving the registers, and when the plurality of bits of parallel signals are set in the shift register, the shift registers are sequentially shifted, and serial signals to be outputted from the shift registers are sequentially selected and output. A parallel-to-serial conversion method that is characterized by