RU61489U1 - MULTI-CHANNEL DIGITAL ANALOG CONVERTER - Google Patents

Abstract

The utility model relates to automation and telemechanics, in particular to devices for displaying digital information with analog devices, for example, LEDs with brightness controlled by the average flowing current.

A multi-channel digital-to-analog converter (MCP) contains an information receiving unit, a pulse generator, a recording process control unit, a memory unit, and a control signal generator. The block contains a multiplexer, the first, second, and third pulse counters. MCP also contains a block for generating output signals and a trigger. A communication line is connected to the first input of the information receiving unit, and the first output of the pulse generator is connected to its second input, the second output of which is connected to the input of the first pulse counter and to the second input of the output signal generating unit. The output of the information receiving unit is connected to the input of the memory control unit, the output of which is connected to the first input of the memory unit, the output of which is connected to the first input of the output signal generating unit. The first, second, third, fourth, fifth and sixth outputs of the first pulse counter are connected via a bus to the second, address, input of the memory unit; the first, second and third outputs of the third pulse counter are also connected via a bus to the second address input of the memory unit, and also, respectively, to the ninth, tenth and eleventh inputs of the multiplexer, the output of which is connected to the input of the third counter

impulses; the first, second, third, fourth, fifth outputs of the second pulse counter are connected, respectively, to the fourth, fifth, sixth, seventh, eighth inputs of the multiplexer, and the first input of the second pulse counter is connected to the seventh output of the first pulse counter. MCP contains an additional multiplexer included in the shaper, while its first, second and third inputs are connected, respectively, with the fourth, fifth, sixth outputs of the first pulse counter; the fourth, fifth and sixth inputs of the multiplexer are connected, respectively, to the first, second, third output of the third pulse counter, and the output is connected to the first input of the trigger, the second input of which is connected to the seventh output of the first pulse counter and to the third input of the output signal generating unit; the trigger output is connected to the fourth input of the output signal generating unit; the input of the third pulse counter is connected to the second input of the second pulse counter, and the first, second, third inputs of the multiplexer are connected to its fourth input.

As a result, the performance of a multi-channel digital-to-analog converter is improved. In this case, the total time of digital-to-analog conversion compared with the prototype is significantly reduced.

Description

The utility model relates to automation and telemechanics, in particular, to devices for displaying digital information with analog devices, for example, LEDs with a brightness controlled by the average flowing current.

A device is known for multi-channel digital-to-analog conversion, which contains a control unit for recording input digital information into electronic memory and a block for generating width-modulated signals common to all channels, which, with the help of a decoder, controls output triggers and through them output current drivers, SU 1046927. However, the number of wires for control of output triggers in this case grows linearly with the number of channels, so with a large number of channels, the complexity of the device is unreasonably age It is, and overall system performance dramatically decreases.

The closest in technical essence to the proposed one is a multi-channel digital-to-analog converter containing an information receiving unit, a pulse generator, a recording process control unit, a memory unit, a control signal generator containing a multiplexer and first, second, and third pulse counters, a trigger, and an output signal generating unit while a communication line is connected to the first input of the information receiving unit, and to its second input

the first output of the pulse generator is connected, the second output of which is connected to the input of the first pulse counter and to the second input of the output signal generating unit, the output of the information receiving unit is connected to the input of the memory control unit, the output of which is connected to the first input of the memory unit, the output of which is connected to the first input unit for generating output signals, the first, second, third, fourth, fifth and sixth outputs of the first pulse counter are connected via a bus to the second, address, input of the memory unit, first, sec the second and third outputs of the third pulse counter are connected via bus to the second address input of the memory control unit and, accordingly, to the ninth, tenth and eleventh inputs of the multiplexer, the output of which is connected to the input of the third pulse counter, the first, second, third, fourth, fifth outputs of the second the pulse counter is connected, respectively, with the fourth, fifth, sixth, seventh, eighth inputs of the multiplexer, and the first input of the second pulse counter is connected to the seventh output of the first pulse counter, SU 1709527.

For the scheme described above, the total time of the digital-to-analog conversion of the device is determined by the product of the capacity of the first two counters. For example, with a typical clock frequency of a 10 MHz pulse generator, it will take 1.6 ms of time to convert a 64-channel 8-bit signal. Moreover, the conversion time increases linearly depending on the number of channels. To manage bulletin boards

even with small sizes of 128 × 128 pixels, the conversion time will be more than 0.5 s, which determines the lack of speed of the device.

The basis of this utility model is the solution to the problem of increasing the speed of a multi-channel digital-to-analog converter.

The essence of the utility model is illustrated by the drawing, which shows a schematic diagram of the device.

The multi-channel digital-to-analog converter (MCP) contains an information receiving unit 1, a pulse generator 2, a recording process control unit 3, a memory unit 4, a control signal generator 5. Block 5 contains a multiplexer 6, the first 7, second 8, and third 9 pulse counters. The MCP also contains an output signal generating unit 10 and a trigger 11. A communication line is connected to the first input of the information receiving unit 1, and a first output of the pulse generator 2 is connected to its second input, the second output of which is connected to the input of the first 7 pulse counter and to the second input of the block 10 formation of output signals. The output of the information receiving unit 1 is connected to the input of the memory control unit, the output of which is connected to the first input of the memory unit 4, the output of which is connected to the first input of the output signal generating unit 10. The first, second, third, fourth, fifth and sixth outputs of the first 7 pulse counter are connected via bus 13 to the second, address, input of the memory unit 4; the first, second and third outputs of the third pulse counter 9 are also connected via bus 13 to the second

the address input of the memory unit 4, and also, respectively, with the ninth, tenth and eleventh inputs of the multiplexer 6, the output of which is connected to the input of the third pulse counter 9; the first, second, third, fourth, fifth outputs of the second counter 8 pulses are connected, respectively, with the fourth, fifth, sixth, seventh, eighth inputs of the multiplexer 6, and the first input of the second counter 8 pulses is connected to the seventh output of the first counter 7 pulses.

The MCP contains an additional multiplexer 12, which is included in the former 5, while its first, second and third inputs are connected, respectively, with the fourth, fifth, sixth outputs of the first 7 pulse counter; the fourth, fifth and sixth inputs of the additional multiplexer 12 are connected, respectively, with the first, second, third output of the third counter 9 pulses, and the output is connected with the first input of the trigger 11, the second input of which is connected to the seventh output of the first counter 7 pulses and with the third input of the block 10 formation of output signals; the trigger output 11 is connected to the fourth input of the output signal generating unit 10; the input of the third counter 9 pulses is connected to the second input of the second 8 pulse counter, and the first, second, third inputs of the multiplexer 6 are connected to its fourth input.

Blocks 2, 4, 6, 7, 8, 9, 11, and 12 are implemented on the AT91SAM7S digital universal microcontroller. Blocks 1 and 3 are implemented on the FT245 chip. Block 10 is implemented on the TV62706 chip.

A multi-channel digital-to-analog converter operates as follows.

Information comes from the communication line to input 1 of block 1. Clock 2 from block 2 is fed to input 2 of block 1. According to clock pulses from block 2, data from block 1 is transferred to block 3, from where they go to input 1 of memory block 4. From memory block 4 information is fed to input 1 of the output block 10 of the formation of the output signals. Block 10 contains current keys and directly controls the indicators.

Block 5 controls the reading of memory block 4 with the conversion of digital codes into sets of weighted time intervals, and also controls block 10. The pulses from block 2 go to the counting input of the first counter 7. Counter 7 works strictly cyclically, sequentially addressing information about one of the bits of the digital code defined by the counter 9, in the memory block 4. This information is continuously, with a clock frequency of the generator 2, moves to the shift register in block 10, and after the shift of the information about the last, senior channel, a signal is generated and the counter 7 overflows at its output 7. This signal increments the counter 8 with its trailing edge and rewrites the continuously changing information from the outputs of the shift register of block 10 to the parallel register, affecting its input 3. In the parallel register, it is fixed until the end of the next cycle of the counter 7 during which information on the next bit of the digital code will be prepared for recording in the shift register. For work cycles

counter 7, corresponding to the output of information about the lower 4 bits of the digital code, the increment of the counter 9 will occur immediately after the state of the counter 8 changes simultaneously with the last reset of the pulse from the output of the multiplexer 6. Thus, the total time of the cycles of the output of information about the 4 lower bits the same and corresponds to one cycle of the counter 7.

However, the duration of weighted time intervals at the output of block 10 is determined not only by the time of recording information in the registers of this block, but also by the duration of positive pulses generated at the output of trigger 11. For the least significant bit of the digital code, trigger 11 will be reset via an additional multiplexer 12 to a positive level of the 4th digit of counter 7, which corresponds to the generation by the counter 7 of the 8th channel address from 64. This determines the pulse duration equal to 1/8 of the total channel switching cycle by counter 7 .

When counter 9 reaches code 4, the interaction of the three counters changes. In this case, after the end of one cycle of counter 7, counter 8 is no longer immediately reset to '0', but waits for the end of the next cycle of counter 7. And only after that counter 8 increases the code of counter 9 through multiplexer 6 and resets itself to '0'. At the same time, the same information about the 5th information bit is output to the shift registers of block 10 during 2 cycles of operation of counter 7, and the information in the parallel register does not change during 2 periods of operation of counter 7.

Quite similarly, a doubling of weighted time intervals occurs for all older binary information bits.

The capacity of counter 8, which forms weighted time intervals, is reduced compared with the prototype (in the proposed example, by three bits from 8 to 5), and the corresponding part of the least significant bits (three) of multiplexer 6 are connected to the least significant bits of counter 8. The number of discarded bits of counter 8 corresponds to the number used information inputs of the second multiplexer 12 and determines the magnitude of the increase in speed. In this case, the total time of digital-to-analog conversion compared with the prototype is significantly reduced.

For example, with a typical clock frequency of a 10 MHz pulse generator, it will take 0.2 ms of time to convert a 64-channel 8-bit signal, which is 7.5 times faster than in the prototype. For the control conditions of the information board 128 × 128, we obtain quite acceptable values of the conversion time equal to 23 ms. The maximum acceleration with 8-bit conversion accuracy can reach 32 times.

Claims (1)

A multichannel digital-to-analog converter containing an information receiving unit, a pulse generator, a recording process control unit, a memory unit, a control signal generator, comprising a multiplexer and first, second, and third pulse counters, a trigger and generating output signals, with the first input of the information receiving unit a communication line is connected, and the first output of the pulse generator is connected to its second input, the second output of which is connected to the input of the first pulse counter and to the second input of the forming unit of output signals, the output of the information receiving unit is connected to the input of the memory control unit, the output of which is connected to the first input of the memory unit, the output of which is connected to the first input of the output signal generating unit, the first, second, third, fourth, fifth and sixth outputs of the first pulse counter connected via a bus to the second, address, input of the memory unit, the first, second and third outputs of the third pulse counter are connected via a bus to the second address input of the memory control unit and, respectively, the ninth, tenth and eleventh inputs of the multiplexer, the output of which is connected to the input of the third pulse counter, the first, second, third, fourth, fourth, fifth outputs of the second pulse counter are connected respectively to the fourth, fifth, sixth, seventh, eighth inputs of the multiplexer, and the first input of the second counter pulse is connected to the seventh output of the first pulse counter, characterized in that an additional multiplexer is introduced into it, while its first, second and third inputs are connected respectively to the fourth, fifth, sixth the outputs of the first pulse counter, the fourth, fifth and sixth inputs are connected respectively to the first, second, third output of the third pulse counter, and the output is connected to the first input of the trigger, the second input of which is connected to the seventh output of the first pulse counter and with the third input of the output generating unit signals, the trigger output is connected to the fourth input of the output signal generating unit, the input of the third pulse counter is connected to the second input of the second pulse counter, and the first, second, third inputs are multip lexors are connected to its fourth entrance.