JPS60158689A - Semiconductor light-emitting device - Google Patents

Abstract

PURPOSE:To reduce reactive currents displaced from an active layer, and to improve luminous efficiency by forming layers having a conduction type reverse to a current stopping layer in the current stopping layer to a sandwich shape while being separated from double hetero-junction structure. CONSTITUTION:An N<+> type InP layer 11A and a P type InP layer 12A are grown on an N type InP substrate 1, and a V-shaped striped groove is formed. A P type region is shaped through diffusion, and an N type InP clad layer 15, an InGaAs active layer 16, a P type InP clad layer 17 and a P type InGaAsP contact layer 18 are formed through an epitaxial growth method. A P side electrode 19 and an N side electrode 20 are shaped, thus completing the titled light- emitting device through cleavage. Accordingly, a reverse bias junction is formed in a current interrupting layer, and reactive currents flowing while being displaced from the active layer are reduced, thereby improving luminous efficiency.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a structure for improving the luminous efficiency and temperature characteristics of a semiconductor light emitting device, particularly a semiconductor light emitting device having a buried active region.

(b) Background of the Technology In a system that uses light as an information signal medium such as optical communication, the semiconductor light emitting device t1. The system has been improved by improving the characteristics such as single fundamental zero-order transverse mode oscillation, single longitudinal mode oscillation, improved linearity of current-optical output characteristics, improved quantum efficiency, and increased output power. Conventional technology and problems Many structures have already been provided for semiconductor issuing devices, one of which is the VSB (V-grooved 5-u
bstrate Buried doubAe het
FIG. 1 is a side view showing an example of a VSB v-za. In the figure, 1 is a nm indium-phosphorus compound (I
nP) substrate, 2 is a pffiInPtic flow blocking layer, 4 is a striped groove, 5 is an n-type InP cladding layer, 5a is an n-type In layer grown at the same time as the cladding layer 5, 6 is a non-doped indium-gallium arsenic layer, Phosphorus compound (InGa
AsP) active layer, I grown simultaneously with 6alC active layer 6
nGaAsP/L 7 is pWInP cladding layer, 8 is p
A jnGaAsP contact layer, 9 represents a p-side electrode, and 10 represents an n-side electrode.

In the conventional type 1'sB laser, since the side surface of the stripe di44 is (111)B, the cladding layer 5
, the double heterojunction structure of active N6 and cladding layer 7 is easy to grow, the shape and dimensions of active IfII6 are stable, and the inner surface of the groove is a crystal plane, making it extremely smooth. It also has the advantages of characteristics such as no diffuse reflection of light from this part and a smooth light intensity distribution.

I, n, and nt shown in FIG. 1 can be mentioned as current paths in the conventional example of the VSB laser described above. In this figure, 2 is a current that flows through the active layer 6 and contributes to light emission, while 2 and 3 are invalid currents that do not flow through the active layer 6t.

The current (2) flows through a path of pWInP cladding layer 7→P-type InP current blocking layer 2→n-type InP substrate 1, and this path includes a p-n junction of p-type InP-n-type InP.

On the other hand, the p-n junction included in the path of the current ■ is a p-type I
It is formed at the interface between the nP cladding layer 7 and the n-type InGaAsP active layer 6, and the forbidden band width of InGaAsP is smaller than that of InP. Current as far as I can see■
The density of is smaller than the density of current I. However, the pn junction area is much larger at the interface between the current blocking layer and the substrate than at the interface between the active layer and the C/D layers, and the μ current (2) as a current value (current density x junction area) becomes considerably large.

Next, regarding the current (2), if we look at the conductivity type of the semiconductor layer outside the stripe structure of the VSB laser with the above structure, we find that (()In
p-group region consisting of GaAsP contact layer 8 and InP cladding layer 7; (b) nff1 consisting of InP layers;
region, p region consisting of InPK flow blocking layer 2)
It is known that an nW region formed from an InP substrate 1, a cuff including an intermediate p-type or nm-thin InGaAsP layer 6a, and a pnpn junction formed between both electrodes. This structure itself consists of an nfflInP layer 5a and a p-type InP current blocking layer 2.
It has a high current blocking effect because a reverse bias junction is formed at the interface.

However, as the current ■ flows, this pn
The pnpn structure operates as a thyristor with the entire gate current, and the current corresponding to the anode current is turned on sequentially.The cross-sectional area of this pnpn structure is also much larger than the area of the active layer, and the reactive current increases, causing light emission. Efficiency decreases. This effect becomes more severe as the temperature rises.

(Condolences) OBJECT OF THE INVENTION An object of the present invention is to address the above-described problems and provide a semiconductor light emitting device in which reactive current is reduced and luminous efficiency is improved.

(e) Structure of the Invention The object of the present invention is to provide a semiconductor substrate of a first conductivity type or
in contact with the semiconductor layer, a second semiconductor confinement layer of the first conductivity type, and a third semiconductor confinement layer whose forbidden band width is smaller than that of the second semiconductor layer.
A double heterojunction structure in which a semiconductor active layer and a fourth semiconductor confinement layer of a second conductivity type are sequentially laminated is provided in a stripe shape, and the double heterojunction structure is sandwiched between the semiconductor substrate or the first semiconductor confinement layer. The fifth layer of the 24th electric type in contact with the semiconductor layer of
a semiconductor layer of a fourteenth semiconductor layer that is in contact with the fifth semiconductor layer, and a sixth semiconductor layer that is interposed between the sixth semiconductor layer and the double heterostructure and that is interposed between the sixth semiconductor layer and the double heterostructure. a seventh semiconductor layer of the 24th electric type in contact with the upper surface, an eighth semiconductor layer of the first conductivity type WL in contact with the seventh semiconductor layer, and a second semiconductor layer on the eighth semiconductor layer. Conductor's 9th cow conductor "turtle body I"
0 (fJ) achieved by a semiconductor light emitting device provided with 0 (fJ) Embodiments of the Invention The present invention will be specifically explained below using embodiments with reference to the drawings.

FIG. 2 is a sectional view showing an example of a semiconductor light emitting device having the structure of the present invention, in which 11 is an n-type InP substrate, 12A and 1
2B is each p-type In layer, 13 is each n-type In layer, 15 is n-InP cladding (confinement) J-515a is n-type In
Cuff, 16 B InGaAsP active layer, 17 is P type I
An nP cladding layer, 18 a p-type InGaAs cuff, 19 a p-side electrode, and 20 an n-side electrode.

Comparing this embodiment with the conventional example shown in FIG.
At the position of the p-type InP current blocking layer 2 of the conventional example, a p-type I
An n-type InP/d 13 is provided between the n-cuffs 12A and 12B in a side-ditch manner and separated from the double heterojunction structure in the groove. In addition, n-made In cuff 1
3. pear In of the part separating from the double heterozygous structure
Width of cuff 12B Normal I nGaAsP activity 1lli1
Make it narrower than the width of 6. n-type InP inserted as described above
The reactive current path is extremely limited by Ii13, and the current amplification factor of the npn) transistor structure composed of n'EI InP Jill15a + p-type InP layers 12B and 12A and nff1InP substrate 11 is reduced, and the reactive current is significantly reduced. FIGS. 3(a) to 3(c) are process-order sectional views showing an embodiment of the undiscovered invention.

Figure 3(a) For example, if the reference impurity concentration is 1 to 2X10''(cnI''3), an InP substrate Including n+ff1In
P layer 11A and example cuff zinc (Zn) 5X10" to LX
For example, the p-type In cuff 12A containing approximately 10" and the n-type In cuff 13 having an impurity concentration of 1 to 5Xxoil (.
For example, the total thickness of each layer is 2.0 [μm],
Epitaxial growth is performed to a thickness of about 0.5 [μm] and 1.5Cμm).

FIG. 3 (see OFF) For example, silicon dioxide (
A mask is provided using SiOx) or silicon nitride (S isN+), and etching is performed using, for example, hydrochloric acid (net) to form a stripe with a V-shaped cross section. In this embodiment, the opening width of this groove is, for example, 3 to 4.
[μm].

After removing the mask, cadmium ((
Dd) Diffusion is performed to introduce the substance near the exposed surface of the intermediate substrate at a concentration of about 1 to 2×10” (sub-8).

As a result, a p-type region 12B with a depth of approximately 0.5 to 1 [μm] is formed on the upper surface of the n-type InPIl@13 and the ■# surface, but since the n''InPllA has a high n-type impurity resistance, V111 plane μpWK is not converted. Note that Znk can also be used for the impurity to be diffused.

Each of the following intermediates 1-
It grows gradually. That is, the n-type InP cladding layer 15
In all examples, the impurity content is about 5X10IffI:cm-'', the InGaAsP active layer 16 is non-doped and has a thickness of, for example, about 0.2[μm], and the impurity is about 5X10''(cm-'). degree,
The p-type InGaAsP contact layer 18 has an impurity concentration of about 2×10'''(cln-''), for example. Furthermore, n-type I
During the growth of nP cladding 11115, n-type InPI11
5a* When growing the InGaAsP active layer 16, InG
An aAeP layer 16& extends above it.

Then, P9 [electrodes 19 and n
A side electrode 20 is provided, and the V of this embodiment is
The SB laser is completed.

(2) As described in the detailed explanation of the invention, in addition to the pn reverse bias junction in the intermediate layer 1-product/# direction, which has already been performed in the past, the pn reverse bias junction is also applied in the direction parallel to the ascending surface of the intermediate layer. By providing the bias junction in the vicinity of the stripe, the reactive current flowing out of the active layer is significantly reduced, thereby increasing the luminous efficiency of the intermediate light emitting device. This effect becomes particularly noticeable when the environmental temperature becomes high.

[Brief explanation of the drawing]

FIG. 1 shows a conventional example of a VSB laser.
FIG. 3 (aJ to (Q) are process order 11rtfi diagrams showing an embodiment of the invention. In the figure, 11 is an nff1InP substrate, IIA is an n+
凰InP cuff 12A and 12B tipffllnP layer,
13 is n MI I n P JH% 15 is nff1
InP clad l-115a is nya In cuff, 16 is I
nGaAsP active layer, 16a is InGaAsP layer, 17
UP type InP Kutsudono, 18 is p fin I n
A GaAsP layer, 19 a p@ electrode, and 2° a nollI electrode are all shown. Mine l mon￥-2 Gaken 3 Figure IL7

Claims (1)

[Claims] In contact with a first conductivity type semiconductor substrate or a first semiconductor layer,
A second semiconductor confinement layer of a first conductive layer, a third semiconductor active layer whose forbidden band width is smaller than that of the second semiconductor layer, and a fourth semiconductor confinement layer made of a second conductive layer are sequentially laminated. A fifth semiconductor layer of a second conductivity type that is in contact with the semiconductor substrate or the first semiconductor layer, sandwiching the double heterojunction structure, and a fifth semiconductor layer that is in contact with the semiconductor substrate or the first semiconductor layer;
a sixth semiconductor layer of a first conductivity type that is in contact with the semiconductor layer; and an eighth semiconductor layer that has a dielectric gap between the sixth semiconductor layer and the double heterostructure, A semiconductor light emitting device 0 characterized in that a ninth semiconductor layer of @2 conductivity type is provided on the layer.