JPS6014514U - analog waveform generator - Google Patents
analog waveform generatorInfo
- Publication number
- JPS6014514U JPS6014514U JP10398583U JP10398583U JPS6014514U JP S6014514 U JPS6014514 U JP S6014514U JP 10398583 U JP10398583 U JP 10398583U JP 10398583 U JP10398583 U JP 10398583U JP S6014514 U JPS6014514 U JP S6014514U
- Authority
- JP
- Japan
- Prior art keywords
- phase angle
- waveform generator
- angle range
- waveform
- analog waveform
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrophonic Musical Instruments (AREA)
- Recording Measured Values (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図はこの考案の一実施例を示す電気的ブロック図、
第2図aは発生すべき波形の一例を示す図、bは同波形
発生のために第1図のメモリに記゛憶すべきディジタル
値の記憶例を示す図、である。
1・・・クロック発生器、2・・・アドレスカウンタ、
3・・・メモリ(ROM)、Ro、 R,・・・アナロ
グ変換用のミキシング抵抗、C・・・積分用のコンデン
サ。
補正 昭5E111. 1
図面の簡単な説明を次のように補正する。
明細書10頁7行目の「a」を削除する。
明細書第10頁第7〜8行の「を示す図、bは」を「及
び」と補正する。
明細書荀頁9行目の「記憶例を」の次に「夫々」を加入
する。 。FIG. 1 is an electrical block diagram showing an embodiment of this invention.
FIG. 2A is a diagram showing an example of a waveform to be generated, and FIG. 2B is a diagram showing an example of storing digital values to be stored in the memory of FIG. 1 in order to generate the same waveform. 1... Clock generator, 2... Address counter,
3...Memory (ROM), Ro, R...Mixing resistor for analog conversion, C...Capacitor for integration. Correction Showa 5E111. 1. The brief description of the drawing shall be amended as follows. Delete "a" on page 10, line 7 of the specification. In the 7th to 8th lines of page 10 of the specification, ``The figure showing, b'' is corrected to ``and''. In the ninth line of page 9 of the specification, ``each'' is added next to ``memorized example''. .
Claims (1)
大振幅値に応じて選定された第1及び第2のディジタル
値を、該位相角範囲における波形振幅値に応じてパルス
幅変調した状態で該位相角範囲に対応するアドレス領域
内のアドレスに割当てて記憶したメモリと、このメ蕃り
から読み出されたディジタル値をアナログ変換スル手段
と、アナログ変換された信号を積分する回路とを具えた
アナログ波形発生装置。 2 所望の波形が複数の前記位相角範囲から成り、少な
(とも隣合う位相角範囲に関して前記第1及び第2のデ
ィジタル値の少なくとも一方の値が互いに異なっている
実用新案登録請求の範囲第1項記載のアナログ波形発生
装置。[Claims for Utility Model Registration] 1. First and second digital values selected according to the minimum and maximum amplitude values in a given phase angle range of a desired waveform, according to the waveform amplitude value in the phase angle range. a memory that stores the pulse width modulated state in an address within the address area corresponding to the phase angle range; a means for converting the digital value read from the memory into an analog converter; An analog waveform generator equipped with a circuit that integrates. 2. Utility model registration claim 1, in which the desired waveform consists of a plurality of the phase angle ranges, and at least one of the first and second digital values differs from each other with respect to adjacent phase angle ranges. The analog waveform generator described in Section 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10398583U JPS6014514U (en) | 1983-07-06 | 1983-07-06 | analog waveform generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10398583U JPS6014514U (en) | 1983-07-06 | 1983-07-06 | analog waveform generator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6014514U true JPS6014514U (en) | 1985-01-31 |
Family
ID=30244369
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10398583U Pending JPS6014514U (en) | 1983-07-06 | 1983-07-06 | analog waveform generator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6014514U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5750104A (en) * | 1980-07-10 | 1982-03-24 | Reliance Electric Co | Method and device for digitally generating control signal for operating converter |
-
1983
- 1983-07-06 JP JP10398583U patent/JPS6014514U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5750104A (en) * | 1980-07-10 | 1982-03-24 | Reliance Electric Co | Method and device for digitally generating control signal for operating converter |
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