JPH03105020U - - Google Patents
Info
- Publication number
- JPH03105020U JPH03105020U JP1435590U JP1435590U JPH03105020U JP H03105020 U JPH03105020 U JP H03105020U JP 1435590 U JP1435590 U JP 1435590U JP 1435590 U JP1435590 U JP 1435590U JP H03105020 U JPH03105020 U JP H03105020U
- Authority
- JP
- Japan
- Prior art keywords
- data
- converter
- output
- voltage
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本発明の一実施例の構成ブロツク図、
第２図は周波数補正データメモリに格納されてい
る周波数設定データに対応する出力値のグラフ、
第３図は補正前の出力レベルと補正後の出力レベ
ルを示す図、第４図は従来のＤＤＳ回路の図、第
５図は従来のＤＤＳ回路の出力レベル特性を示す
図である。
１……デイジタル加算器、２……正弦波データ
メモリ、３……ＤＡ変換器、４……基準電圧電源
、５……ＬＰＦ、６……周波数補正データメモリ
、７……第２ＤＡ変換器、８……加算器、９……
基礎電圧電源。
FIG. 1 is a block diagram of an embodiment of the present invention.
Figure 2 is a graph of output values corresponding to the frequency setting data stored in the frequency correction data memory.
FIG. 3 is a diagram showing the output level before correction and the output level after correction, FIG. 4 is a diagram of a conventional DDS circuit, and FIG. 5 is a diagram showing the output level characteristics of the conventional DDS circuit. 1... Digital adder, 2... Sine wave data memory, 3... DA converter, 4... Reference voltage power supply, 5... LPF, 6... Frequency correction data memory, 7... Second DA converter, 8... Adder, 9...
Basic voltage power supply.
Claims (1)
された出力データとをクロツク入力毎に加算する
デイジタル加算器１と、該デイジタル加算器１の
出力をアドレスとして、格納されているデータを
クロツク入力毎に読み出される正弦波データメモ
リ２と、その出力のデイジタル信号をアナログ信
号に変換するＤＡ変換器３と、該ＤＡ変換器３の
出力信号の高調波を除去するためのＬＰＥ５とで
構成されるＤＤＳ回路と、 入力された周波数データをアドレスとして前記
基本回路の有する出力周波数により変化する出力
レベル特性を補正するデータを格納している周波
数補正データメモリ６と、 該周波数データ補正メモリ６の出力デイジタル
データをアナログデータに変換して補正電圧を出
力する第２のＤＡ変換器７と、 前記ＤＡ変換器３に基準電圧を供給するための
基礎電圧を出力する基礎電圧電源９と、 前記ＤＡ変換器７の出力電圧と前記基礎電圧電
源９の電圧を加算して前記ＤＡ変換器３に基準電
圧を供給する加算器８とを具備することを特徴と
するＤＤＳを用いた正弦波発生回路。[Claims for Utility Model Registration] A digital adder 1 that adds input frequency setting data and feedback output data for each clock input, and data stored with the output of the digital adder 1 as an address. A sine wave data memory 2 is read out every clock input, a DA converter 3 converts the output digital signal into an analog signal, and an LPE 5 removes harmonics from the output signal of the DA converter 3. a DDS circuit configured, a frequency correction data memory 6 storing data for correcting output level characteristics that change depending on the output frequency of the basic circuit using input frequency data as an address; and the frequency data correction memory 6. a second DA converter 7 that converts the output digital data of the converter into analog data and outputs a correction voltage; a basic voltage power supply 9 that outputs a basic voltage for supplying a reference voltage to the DA converter 3; A sine wave generation circuit using a DDS, comprising an adder 8 that adds the output voltage of the DA converter 7 and the voltage of the basic voltage power supply 9 and supplies a reference voltage to the DA converter 3. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1435590U JPH03105020U (en) | 1990-02-16 | 1990-02-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1435590U JPH03105020U (en) | 1990-02-16 | 1990-02-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03105020U true JPH03105020U (en) | 1991-10-31 |
Family
ID=31517726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1435590U Pending JPH03105020U (en) | 1990-02-16 | 1990-02-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03105020U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013143716A (en) * | 2012-01-12 | 2013-07-22 | Seiko Npc Corp | Method for adjusting atomic clock reception ic |
-
1990
- 1990-02-16 JP JP1435590U patent/JPH03105020U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013143716A (en) * | 2012-01-12 | 2013-07-22 | Seiko Npc Corp | Method for adjusting atomic clock reception ic |
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