JPH01175439A - Optical receiver - Google Patents

Optical receiver

Info

Publication number
JPH01175439A
JPH01175439A JP62333292A JP33329287A JPH01175439A JP H01175439 A JPH01175439 A JP H01175439A JP 62333292 A JP62333292 A JP 62333292A JP 33329287 A JP33329287 A JP 33329287A JP H01175439 A JPH01175439 A JP H01175439A
Authority
JP
Japan
Prior art keywords
output
comparator
digital
value
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62333292A
Other languages
Japanese (ja)
Inventor
Yoshikazu Suehiro
末広 芳和
Kazuo Matsumura
松村 和郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62333292A priority Critical patent/JPH01175439A/en
Publication of JPH01175439A publication Critical patent/JPH01175439A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To stabilize the reference level for the binary coding of a comparator regardless of the length of the period of no light signal by digitizing the output signal of an amplifier and storing it in two storage circuits according to the output level of said comparator, and converting their intermediate value into an analog value and thus generating the reference level. CONSTITUTION:When the output signal of a photodetector 1 which is amplified by the amplifier 3 is converted by the comparator 4 into a binary signal, the output signal of the amplifier 3 is digitized by an analog-digital converting circuit 6 and written in a 1st storage circuit 7 when the output of the comparator is at 'H' level or in a 2nd storage circuit 8 when the output of the comparator is at 'L' level, an arithmetic circuit 10 calculates the center value between the digital output values stored in the 1st and 2nd storage circuits 7 and 8, and the output value of the arithmetic circuit 10 is converted into an analog value through a digital-analog converting circuit 11 for analog conversion, so that the analog value is applied as the reference level to the comparator 4. Consequently, the reference level is stable even when the period of no light signal becomes long.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は光通信に用いられる元データリンクの光受信装
置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to an optical receiving device for an original data link used in optical communications.

従来の技術 従来の光受信装置を第3図に示す。第3図において、受
光素子1で光信号2を検出し、その信号は増幅器3を介
して比較器4の逆相入力(→に印加さね、正相入力(+
)の電圧値と比較されて“H”レベ# (!: ”L’
 レベルの2値化信号に変換されている。
2. Description of the Related Art A conventional optical receiver is shown in FIG. In FIG. 3, a light receiving element 1 detects an optical signal 2, and the signal is applied to a negative phase input (→) and a positive phase input (+) of a comparator 4 via an amplifier 3.
) is compared with the voltage value of "H" level # (!: "L'
It is converted into a level binary signal.

比較器4の正相入力(+)には、次のようにして電圧が
印加さね、ている。基準電源5の出力と前記増幅器3の
出力の間には抵抗器6.7の直列回路が接続さね、てお
り、抵抗器6と7の中点電圧が電圧保持部8を介して比
較器4の正相入力(+)に印加さねている。コンデンサ
12は電圧保持部8の保持時間の時定数設定用である。
A voltage is applied to the positive phase input (+) of the comparator 4 in the following manner. A series circuit of resistors 6 and 7 is connected between the output of the reference power supply 5 and the output of the amplifier 3, and the midpoint voltage of the resistors 6 and 7 is connected to the comparator via the voltage holding section 8. No voltage is applied to the positive phase input (+) of No.4. The capacitor 12 is used to set a time constant for the holding time of the voltage holding section 8.

第4図(a)は比較器4の逆相入力(−1の信号波形S
lと正相入力(+)の信号波形S2を示し、第4図(b
)は比較器4の出力波形を示す。この第3図、第4図に
従ってその動作を詳しく説明する。
FIG. 4(a) shows the negative phase input of comparator 4 (-1 signal waveform S
Fig. 4(b) shows the signal waveform S2 of l and positive phase input (+).
) shows the output waveform of comparator 4. The operation will be explained in detail with reference to FIGS. 3 and 4.

受光素子1に人力された光信号2は増幅器3により増幅
さね、る。一方、基準電源5の出力電圧は元入力が細い
場合の増幅器3の出力電圧とほぼ同一に設定されており
、抵抗器6と7は同一の抵抗値に設定さねている。抵抗
器6と7の中点電位は、増幅器3の出力電圧と基準電源
5の出力電圧の間で変化し、その電圧値が“H”レベル
のときに電圧保持部8で保持さねで、電圧保持部8の出
力波形がコンデンサ12で決まる時定数で変化する。比
較器4では波形S1と82がレベル比較されて、第4図
(b) )n示第2値化信号に変換されている。
An optical signal 2 inputted to the light receiving element 1 is amplified by an amplifier 3. On the other hand, the output voltage of the reference power supply 5 is set to be approximately the same as the output voltage of the amplifier 3 when the original input is thin, and the resistors 6 and 7 are set to the same resistance value. The midpoint potential of the resistors 6 and 7 changes between the output voltage of the amplifier 3 and the output voltage of the reference power supply 5, and is held by the voltage holding section 8 when the voltage value is at the "H" level. The output waveform of the voltage holding section 8 changes with a time constant determined by the capacitor 12. In the comparator 4, the levels of the waveforms S1 and 82 are compared and converted into a second value signal shown in FIG. 4(b)).

発明が解決しようとする問題点 このような従来の構成では、光信号2を連続的に受信す
る場合と、光信号2を長時間にわたって受信しない状態
ののちに光信号2を受信する場合とでは、再生さねた出
力信号のパルス幅に差異が生じる。具体的には、第4図
の期間Aのように光信号2が連続して゛°H゛、゛L″
レベルを繰り返している場合には、電圧保持部8の出力
は増幅器3の出力の略中点レベルを示すため、比較器4
の出カバm 幅M 3のパルス幅(“H”レベルと“L
”レベルの50%値)と同一のパルス幅T1を示す。期
間Aの次に光信号2が無い期間Bが続き、期間Cになっ
て光信号2の入力があると、期間Bから期間Cでは、重
圧保持部8の出力は放電完了後に立上るため、比較器4
の出力パルス幅がT2に拡がり、同じパルス幅の光信号
2であってもT1≠T2でパルス幅変動が生じる。
Problems to be Solved by the Invention In such a conventional configuration, there are two cases: when receiving the optical signal 2 continuously and when receiving the optical signal 2 after not receiving the optical signal 2 for a long time. , a difference occurs in the pulse width of the reproduced output signal. Specifically, as in period A in FIG.
When the level is repeated, the output of the voltage holding section 8 indicates approximately the midpoint level of the output of the amplifier 3, so the comparator 4
Output cover m Width M 3 pulse width (“H” level and “L” level
Period A is followed by period B in which there is no optical signal 2, and when period C is reached and optical signal 2 is input, period B changes to period C. In this case, since the output of the heavy pressure holding section 8 rises after the completion of discharge, the output of the comparator 4
The output pulse width of is expanded to T2, and even if the optical signal 2 has the same pulse width, pulse width fluctuation occurs because T1≠T2.

本発明は光信号の無信号期間の直後の光信号の受信時に
おいても、2値化信号出力にパルス幅の変動が生じない
光受信装置を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide an optical receiver in which pulse width does not vary in the output of a binary signal even when receiving an optical signal immediately after a no-signal period of the optical signal.

問題点を解決するための手段 本発明の光受信装置は、光信号を受ける受光素子と、前
記受光素子の出力信号を増幅する増幅器と、前記増幅器
の出力をディジタル変換するアナログ・ディジタル変換
回路と、前記アナログ・ディジタル変換回路のディジタ
ル出力値をディジタル記憶する第1.第2の記憶回路と
、第1.第2の記憶回路が記憶している各ディジタル出
力値の間の中央値を算出する演算回路と、演算回路の出
力値をアナログ変換するディジタル・アナログ変換回路
と、前記ディジタル・アナログ変換回路のアナログ出力
値を基準レベルとして前記増幅器の出力信号を2値化す
る比較器とを設け、前記比較器の出力が“H”L/ベベ
ルときに第1の記憶回路にディジタル値を書き込み、比
較器の出力が“L″レベルときに第2の記憶回路にディ
ジタル値を書き込むように構成したことを特徴とする。
Means for Solving the Problems The optical receiving device of the present invention includes a light receiving element that receives an optical signal, an amplifier that amplifies the output signal of the light receiving element, and an analog-to-digital conversion circuit that converts the output of the amplifier into a digital signal. , a first . a second memory circuit; an arithmetic circuit that calculates the median value between the respective digital output values stored in the second storage circuit; a digital-to-analog conversion circuit that converts the output value of the arithmetic circuit into analog; and an analog conversion circuit for the digital-to-analog conversion circuit; A comparator that binarizes the output signal of the amplifier with the output value as a reference level is provided, and when the output of the comparator is "H"/L/bevel, a digital value is written in the first storage circuit, and the comparator outputs a digital value. The present invention is characterized in that a digital value is written into the second storage circuit when the output is at the "L" level.

作用 この構成によると、比較器での2値化のための基準レベ
ルを、増幅器の出力信号をディジタル変換して、その値
を前記比較器の出力レベルに応じて第1.第2の比較回
路にディジタル記憶させ、両ディジタル記憶値の中間値
を演算回路で算出し、こねをアナログ変換して作成して
おり、光信号の無信号期間の長さにかかわらず安定して
いる。
Effect: According to this configuration, the output signal of the amplifier is digitally converted to the reference level for binarization by the comparator, and the value is set to the first digit according to the output level of the comparator. It is created by digitally storing it in the second comparison circuit, calculating the intermediate value of both digitally stored values in an arithmetic circuit, and converting it into analog, so that it is stable regardless of the length of the optical signal no-signal period. There is.

実施例 以下、本発明の一実施例を第1図と第2図に基づいて説
明する。なお、従来例を示す第3図と同様の作用をなす
ものには同一の符号を付けて説明する。
EXAMPLE Hereinafter, an example of the present invention will be explained based on FIGS. 1 and 2. Components having the same functions as those in FIG. 3 showing the conventional example will be described with the same reference numerals.

第1図は本発明の光受信装置を示す。受光素子1に入力
された光信号2は、増幅器3により増幅される。増幅器
3で増幅すると、その出力信号には第2図(a)の波形
S1に示すように立上りと立下りに傾きが見られる。こ
の信号は比較器4で基準レベルVrefに基づいて2値
化信号に変換される。
FIG. 1 shows an optical receiver according to the present invention. An optical signal 2 input to the light receiving element 1 is amplified by an amplifier 3. When the signal is amplified by the amplifier 3, the output signal has a slope in its rising and falling edges, as shown in waveform S1 in FIG. 2(a). This signal is converted into a binary signal by the comparator 4 based on the reference level Vref.

基準レベルVrefは次のようにして作成されている。The reference level Vref is created as follows.

増幅器3の出力をA、/D変換回路6によりディジタル
変換する。基準電源5とA/D変換回路6との関係は後
で詳述する。比較器4の出力が”HIIレベルのときに
は、第1の記憶回路7の記憶制御信号S3が“H”レベ
ルになってA/D変換回路6のディジタル出力値が第1
の記憶回路7に記憶される。比較器4の出力が“L”レ
ベルのときには、第2の記憶回路8の記憶制御信号S4
にインバータ9を介して“H″レベル供給され、A/D
変換回路6のデイジタル出力値が第2の記憶回路8に記
憶される。
The output of the amplifier 3 is digitally converted by an A/D conversion circuit 6. The relationship between the reference power supply 5 and the A/D conversion circuit 6 will be explained in detail later. When the output of the comparator 4 is at the "HII" level, the storage control signal S3 of the first storage circuit 7 becomes "H" level, and the digital output value of the A/D conversion circuit 6 becomes the first
is stored in the memory circuit 7 of. When the output of the comparator 4 is at "L" level, the storage control signal S4 of the second storage circuit 8
“H” level is supplied to the A/D via the inverter 9.
The digital output value of the conversion circuit 6 is stored in the second storage circuit 8.

次に第1の記憶回路の記憶値■1と第2の記憶回路8の
記憶値■2が演算回路10に入力され、その中点2−V
l 値〔□〕 がディジタル演算される。演算回路10の出
力はL)/A変換回路11を介して比較器4の逆相人力
(→に基準レベルVrefとして印加されている。
Next, the memory value ■1 of the first memory circuit and the memory value ■2 of the second memory circuit 8 are input to the arithmetic circuit 10, and the midpoint 2-V
The l value [□] is digitally calculated. The output of the arithmetic circuit 10 is applied as a reference level Vref to the negative phase input (→) of the comparator 4 via the L)/A conversion circuit 11.

なお、基準電源5は増幅器3の出力の“L”レベルとほ
ぼ同じ電圧を出力しており、電源投入直後において第2
の記憶回路8の出力にディジタル出力値を与えるもので
、こねにより、電源投入後に増幅器3の出力がすぐに“
H′”レベルを示したとしても、比較器4に基準レベル
Vrefを与えることができ、光信号の2値化を直ちに
開始できる。
Note that the reference power supply 5 outputs almost the same voltage as the "L" level of the output of the amplifier 3, and immediately after the power is turned on, the second
The digital output value is given to the output of the memory circuit 8 of the amplifier 3. By kneading, the output of the amplifier 3 becomes "
Even if it indicates the H''' level, the reference level Vref can be applied to the comparator 4, and the binarization of the optical signal can be started immediately.

このように、第1.第2の記憶回路7.8のディジタル
記憶値に基づいて演算回路10で基準レベルVrefが
演算さねでいるため、第2図(a)に示すように基準レ
ベルVrefは、光信号2が長い時間にわたってと絶え
た直後であってもそのレベルは安定しており、第2図(
b)に示すように期間Cにおいても期間Aと同じパルス
幅TIで変換できる。
In this way, the first. Since the reference level Vref is calculated in the arithmetic circuit 10 based on the digital storage value of the second storage circuit 7.8, the reference level Vref is calculated as shown in FIG. 2(a). Even immediately after it ceases to exist over time, its level remains stable, as shown in Figure 2 (
As shown in b), period C can also be converted with the same pulse width TI as period A.

発明の効果 以上のように本発明によると、増幅器で増幅した受光素
子の出力信号を比較器で2値化信号に変換するに除し、
増幅器の出力信号をアナログ・ディジタル変換回路でデ
ィジタル変換し、このディジタル出力値を、比較器の出
力が“°H°゛レベルのときに第1の記憶回路にディジ
タル値を書き込み、比較器の出力がL”レベルのときに
第2の記憶回路にディジタル値を書き込み、演算回路で
第1゜第2の記憶回路が記憶している各ディジタル出力
値の間の中央値を演算回路で算出し、演算回路の出力値
をアナログ変換するディジタル・アナログ変換回路を介
してアナログ変換して、前記比較器に基準レベルとして
印加したため、受光素子に入射する光信号の無信号期間
が長時間にわたっても、比較器に印加さね、る基準レベ
ルが安定しており、パルス幅変動の生じない信号変換を
行うことができるものである。
Effects of the Invention As described above, according to the present invention, in addition to converting the output signal of the light receiving element amplified by the amplifier into a binary signal by the comparator,
The output signal of the amplifier is converted into a digital value by an analog-to-digital conversion circuit, and when the output of the comparator is at the "°H°" level, the digital value is written into the first storage circuit, and the output signal of the comparator is written as a digital value. writes a digital value to the second memory circuit when the is at L'' level, and the arithmetic circuit calculates the median value between the respective digital output values stored in the first and second memory circuits, Since the output value of the arithmetic circuit is converted to analog via a digital-to-analog conversion circuit and applied to the comparator as a reference level, even if there is a long period of no signal of the optical signal incident on the photodetector, the comparison The reference level applied to the device is stable, and signal conversion can be performed without pulse width fluctuations.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の光受信装置の一実施例の構成図、第2
図は同装置の比較器の入出力波形図、第3図は従来の光
受信装置の構成図、第4図は従来の比較器での信号の入
出力波形図である。 1・・・受光素子、2・・・光信号、3・・・増幅器、
4・・・比較器、6・・・A/D変換回路しアナログ・
ディジタル変換回路〕、7・・・第1の記憶回路、8・
・・第2の記憶回路、io・・・演算回路、11・・・
D/A変換回路しディジタル・アナログ変換回路〕、V
ref・・・基準レベル。
FIG. 1 is a configuration diagram of an embodiment of the optical receiving device of the present invention, and FIG.
FIG. 3 is a diagram showing the input and output waveforms of a comparator in the same device, FIG. 3 is a configuration diagram of a conventional optical receiver, and FIG. 4 is a diagram showing input and output waveforms of signals in the conventional comparator. 1... Light receiving element, 2... Optical signal, 3... Amplifier,
4... Comparator, 6... A/D conversion circuit and analog
digital conversion circuit], 7... first storage circuit, 8.
...Second memory circuit, io...Arithmetic circuit, 11...
D/A conversion circuit and digital/analog conversion circuit], V
ref...Reference level.

Claims (1)

【特許請求の範囲】[Claims] 1、光信号を受ける受光素子と、前記受光素子の出力信
号を増幅する増幅器と、前記増幅器の出力をディジタル
変換するアナログ・ディジタル変換回路と、前記アナロ
グ・ディジタル変換回路のディジタル出力値をディジタ
ル記憶する第1、第2の記憶回路と、第1、第2の記憶
回路が記憶している各ディジタル出力値の間の中央値を
算出する演算回路と、演算回路の出力値をアナログ変換
するディジタル・アナログ変換回路と、前記ディジタル
・アナログ変換回路のアナログ出力値を基準レベルとし
て前記増幅器の出力信号を2値化する比較器とを設け、
前記比較器の出力が“H”レベルのときに第1の記憶回
路にディジタル値を書き込み、比較器の出力が“L”レ
ベルのときに第2の記憶回路にディジタル値を書き込む
よう構成した光受信装置。
1. A light-receiving element that receives an optical signal, an amplifier that amplifies the output signal of the light-receiving element, an analog-to-digital conversion circuit that converts the output of the amplifier to digital, and digital storage of the digital output value of the analog-to-digital conversion circuit. an arithmetic circuit that calculates the median value between each digital output value stored in the first and second memory circuits; and a digital converter that converts the output value of the arithmetic circuit into analog.・Providing an analog conversion circuit and a comparator that binarizes the output signal of the amplifier using the analog output value of the digital-to-analog conversion circuit as a reference level,
An optical device configured to write a digital value into a first storage circuit when the output of the comparator is at the “H” level, and to write a digital value into the second storage circuit when the output of the comparator is at the “L” level. Receiving device.
JP62333292A 1987-12-29 1987-12-29 Optical receiver Pending JPH01175439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62333292A JPH01175439A (en) 1987-12-29 1987-12-29 Optical receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62333292A JPH01175439A (en) 1987-12-29 1987-12-29 Optical receiver

Publications (1)

Publication Number Publication Date
JPH01175439A true JPH01175439A (en) 1989-07-11

Family

ID=18264464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62333292A Pending JPH01175439A (en) 1987-12-29 1987-12-29 Optical receiver

Country Status (1)

Country Link
JP (1) JPH01175439A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8544950B2 (en) 2006-10-06 2013-10-01 Lufthansa Technik Ag Airplane seat

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58130675A (en) * 1982-01-28 1983-08-04 Matsushita Electric Ind Co Ltd Binary coding circuit of analog signal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58130675A (en) * 1982-01-28 1983-08-04 Matsushita Electric Ind Co Ltd Binary coding circuit of analog signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8544950B2 (en) 2006-10-06 2013-10-01 Lufthansa Technik Ag Airplane seat

Similar Documents

Publication Publication Date Title
JPS6323687B2 (en)
US4926178A (en) Delta modulator with integrator having positive feedback
JPS6335149B2 (en)
US4498072A (en) A/D Converter having a self-bias circuit
JPS6159913A (en) Ad converting circuit
KR880001114A (en) Offset automatic correction A / D conversion circuit
JPH01175439A (en) Optical receiver
EP0749084B1 (en) Direct digital synthesizer
ES472202A1 (en) Reversible analog to digital converter with high precision
EP0373736A3 (en) Analog to digital converter
JPH05167449A (en) Successive comparison a/d converter
JP3092340B2 (en) PDM converter
JP3230227B2 (en) A / D converter
JP3001623B2 (en) PWM type D / A converter
JPS58212220A (en) Method for compensating offset voltage of analog- digital converter
JP2578651B2 (en) DD / A converter for modulation type A / D converter
SU1309086A1 (en) Analog storage
JPH06177769A (en) High precision sigma delta a/d converter
JPS62202618A (en) Temperature compensation circuit
SU1520657A1 (en) Analog-digital converter
JPS5917476B2 (en) A/D converter
JPS60241307A (en) Multiplication type d-a converter
CN117278030A (en) Noise shaping variable quantizer
JPH0620190B2 (en) Optical signal receiving circuit
JPH04162828A (en) Pcm encoder