JPH06177769A - High precision sigma delta a/d converter - Google Patents

Abstract

PURPOSE:To reduce the power consumption and to reduce cost by making a reference voltage applied to a 1-bit D/A converter variable, thereby changing reference voltage in accordance with an input voltage. CONSTITUTION:An analog input X is connected to one input of a subtractor 4. An output of the subtractor 4 connects to one input of a subtractor 4. An output of the subtractor 6 is connected to a 1-bit D/A converter 9 via an integration device 7. Furthermore, an output of the D/A converter 9 is respectively connected to the other input of the subtractors 4, 6. An output voltage of a variable reference voltage generating circuit 10a being reference voltages -Vref, +Vref are multiplied by 2XFs/Vref and the result is fed to the D/A converter 9, then the reference voltage of the D/A converter becomes -2XFS and +2XFS. Since the input level range is doubled, an optimum input level range is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a .SIGMA..DELTA.A / D converter, and more particularly to a highly accurate .SIGMA..DELTA.A / D converter capable of accurately converting analog inputs in various input level ranges and having high input impedance. Regarding vessels.

[0002]

2. Description of the Related Art The conversion accuracy of a .SIGMA..DELTA. A / D converter changes depending on its input level range. For this reason, an amplifier or the like is provided at the input stage of the ΣΔ A / D converter, and the amplifier or the like is used to amplify the analog input to an input level range where the conversion accuracy is the best and input the ΣΔ A / D converter. There is. FIG. 8 is a configuration block diagram showing an example of such a conventional high precision ΣΔ A / D converter of FIG. 7. In FIG. 7, 1 is a multiplexer for switching a plurality of analog inputs “X ₁ ” to “X _N ”, 2 is a variable gain amplifier, and 3 is a ΣΔ A / D converter.

[0003] When the output from the analog input _{"X 1" ~ "X N} " , for example, various sensors, the output level of each sensor becomes a different value. Therefore, the variable gain amplifier 2 to the analog input _{"X 1" ~ "X N} " selected by the multiplexer 1 is amplified by changing the gain so that the input level range in which most conversion accuracy is improved. As a result, the ΣΔ A / D converter 3 can most accurately convert the output of the variable gain amplifier 2 into the digital output “Y”.

FIG. 8 is a block diagram showing the details of the case where the ΣΔ A / D converter 3 is a second-order ΣΔ A / D converter. In FIG. 8, 2 is the same reference numeral as in FIG.
And 6 are subtractors, 5 and 7 are integrators, and 8 is 1-bit A /
D converter, 9 is a 1-bit D / A converter, and 10 is a reference voltage generating circuit. Also, after this, the multiplexer 1
Is omitted and only the analog input "X" is considered.

The analog input "X" is connected to one input of the subtractor 4 via the variable gain amplifier 2. The output of the subtractor 4 is connected to one input of the subtractor 6 via the integrator 5, and the output of the subtractor 6 is connected to the 1-bit A / D via the integrator 7.
It is connected to the converter 8. The output of the 1-bit A / D converter 8 is output as a digital output "Y" and is also connected to the 1-bit D / A converter 9. 1-bit D / A
The output of the converter 9 is connected to the other inputs of the subtractors 4 and 6, respectively. Further, a reference voltage is connected to the 1-bit D / A converter 9 from the reference voltage generation circuit 10.

[0006] In general, an input level range of the analog input _{"X""-XFS" ~} "+ X FS", when "V _ref" is a reference voltage, the input level range to ΣΔA / D converter 3 the "-0.5 · V _ref" can most accurately a / D conversion in the case of the ~ "+0.5 · V _ref". Therefore, if the gain of the variable gain amplifier 2 is set to “0.5 · V _ref / X _FS ”, that is, if the input level range is 1/2 of the reference voltage value range, ΣΔ
This is the optimum input level range for the A / D converter 3.

[0007]

However, FIG. 7 and FIG.
In the conventional example shown in, for example, when the accuracy of the ΣΔ A / D converter 3 is 16 bits, the linearity of the variable gain amplifier 2 at the input stage must be 16 bits or more.
Since it is difficult to realize with S, it is usually composed of a bipolar device, resulting in high power consumption and high cost. Further, even when the high-accuracy ΣΔ A / D converter 3 is composed of CMOS, most of the circuit is a switched capacitor circuit, so that there is a problem that the input impedance is not high. Therefore, an object of the present invention is to realize a high-accuracy ΣΔA / D converter that has low power consumption, low cost, and high input impedance.

[0008]

In order to achieve such an object, according to the first aspect of the present invention, in a ΣΔ A / D converter, a subtractor having an analog input connected to one input,
The integrator to which the output of this subtractor is connected, the output of this integrator and a 1-bit A / D converter that outputs a digital output, and the output of this 1-bit A / D converter are connected. , A 1-bit D / A converter whose output is connected to the other input of the subtractor, and a variable reference voltage generation circuit for supplying a reference voltage to the 1-bit D / A converter. To do. In the second aspect of the present invention, ΣΔ
In the A / D converter, a voltage holding circuit to which an analog input is connected, a subtractor to which the output of the voltage holding circuit is connected to one input, and a first to which the output of the subtractor is connected
Variable gain amplifier, a second variable gain amplifier whose output is connected to the other input of the subtractor, an integrator to which the output of the first variable gain amplifier is connected, and an output of this integrator. A 1-bit A / D converter that is connected and outputs a digital output, and an output of the 1-bit A / D converter are connected, and an output is connected to the second variable gain amplifier And a converter.

[0009]

High accuracy is achieved by changing the reference voltage supplied to the 1-bit D / A converter and changing the reference voltage according to the input voltage. In addition, a voltage holding circuit is provided in the input stage to hold the voltage for a certain period of time, and charge this voltage to the variable capacitance or capacitance of the input stage in advance so that the charging current becomes almost "0" and high input impedance is achieved. Is possible.

[0010]

The present invention will be described in detail below with reference to the drawings.
FIG. 1 is a configuration block diagram showing a first embodiment of a high precision ΣΔ A / D converter according to the present invention. Here, 4 to 9 have the same reference numerals as those in FIG. In FIG. 1, reference numeral 10a is a variable reference voltage generating circuit whose reference voltage output is variable. The first embodiment shown in FIG. 1 is a second-order .SIGMA..DELTA.A / D converter, and its connection relationship is the same as that of FIG. 8 except that the variable gain amplifier 2 is not provided.

Further, FIG. 2 shows a high precision ΣΔA / according to the present invention.
It is a block diagram which shows the 2nd Example of a D converter.
Here, 8, 9 and 10a are denoted by the same reference numerals as in FIG. In FIG. 2, 11 is a subtractor and 12 is an integrator.
In FIG. 2, the ΣΔ A / D converter 3 is realized by a first-order ΣΔ A / D converter.

In FIG. 2, the analog input "X" is connected to one input of the subtractor 11, and the output of the subtractor 11 is connected to the 1-bit A / D converter 8 via the integrator 12.
The output of the 1-bit A / D converter 8 is a digital output "Y".
And is connected to the 1-bit D / A converter 9. The output of the 1-bit D / A converter 9 is connected to the other input of the subtractor 11. Further, the output voltage of the reference voltage generator 10a is connected to the 1-bit D / A converter 9.

The operation of the embodiment shown in FIGS. 1 and 2 will now be described. 1 and 2, the variable reference voltage generation circuit 1
0a output voltage as reference voltage "-V _ref " and "+ V
_{The ref} voltage is multiplied by “2 · X _FS / V _ref ” and supplied to the 1-bit D / A converter 9, so that the reference voltage of the 1-bit D / A converter 9 is “−2 · X _FS ” and “ + 2 · X _FS ”. Here, the range of the reference voltage value is twice the input level range“ −X _FS ”to“ + X _FS ”, so the optimum input level range is set as described above. .

Incidentally, FIG. 3 shows a high precision ΣΔA / according to the present invention.
It is a block diagram which shows the 3rd Example of a D converter,
In particular, it realizes a high input impedance. Figure 3
13 is a voltage holding circuit, 14 and 17 are subtractors,
Reference numerals 15 and 22 are variable gain amplifiers, 16 and 19 are integrators, 18 is an amplifier, 20 is an adder which is a 1-bit A / D converter, and 21 is a 1-bit D / A converter. The third embodiment shown in FIG. 3 is a second-order ΣΔ A / D converter.

The analog input "X" is connected to one input of the subtractor 14 via the voltage holding circuit 13, and the subtractor 14
Is connected to one input of a subtractor 17 via a variable gain amplifier 15 and an integrator 16. The output of the subtractor 17 is connected to one input of the adder 20 via the amplifier 18 and the integrator 19. The output of the adder 20 is output as a digital output "Y" and is also connected to the 1-bit D / A converter 21. The output of the 1-bit D / A converter 21 is the other input of the subtractor 17 and the variable gain amplifier 22.
, And the output of the variable gain amplifier 22 is connected to the other input of the subtractor 14. Furthermore, the adder 20
A voltage "E", which is quantization noise, is applied to the other input of the.

FIG. 4 is a circuit diagram showing details of the third embodiment shown in FIG. 3 when it is formed of CMOS. In FIG. 4, 23, 24, 26, 29, 30, 31, 31,
3, 38 and 40 are switch circuits, 25a and 25b are variable capacitors, 28a, 28b, 32a, 32b, 35a and 3
5b, 39a, 39b, 39c and 39d have a capacity of 2
7, 34 and 41 are differential input / output amplifiers, 36 is a comparator,
37 is a flip-flop circuit, 42 is a switch control circuit, and 43 is a reference voltage generating circuit.

Reference numerals 23 and 24 denote a subtractor 14, a 1-bit D / A converter 21 and a variable gain amplifier 22, and 25a.
˜29 are variable gain amplifier 15 and integrator 16, 30 and 31 are subtractor 17 and 1-bit D / A converter 21,
32a to 35b denote an amplifier 18 and an integrator 19, 36 and 37 denote an adder 20 which is a 1-bit A / D converter, and 3
Reference numerals 8 to 41 constitute the voltage holding circuit 13, respectively.

In the third embodiment shown in FIGS. 3 and 4, the variable gain amplifiers 15 and 22 are provided in the loop to substantially change the reference voltage of the 1-bit D / A converter 21. Therefore, a highly accurate ΣΔ A / D converter can be realized according to the input voltage.

Further, the fact that the third embodiment shown in FIG. 4 has a high input impedance will be described with reference to FIGS. 5 and 6. Here, FIG. 5 is a timing chart showing the output timing of the output of the switch control circuit 42 and the like. In FIG. 5, the control signals (a) to (d), (g) and (h) turn on the switches "p1" to "p4", "pp" and "pn" shown in FIG. 4, respectively. , Or "p1"
~ The terminals on the side where "p4", "pp" and "pn" are described are turned "ON".

The control signal (e) is a control signal which rises at the rising of the control signal (b) and falls at the falling of the control signal (c), and (f) is the output signal of the flip-flop circuit 37, that is, the digital signal. The output is "Y". Here, the control signal (g) is a logical product of the control signal (e) and the control signal (f), and the control signal (h) is the control signal (e).
And the inverted signal of the control signal (f).

FIG. 6 shows switch circuits 23, 24, 26, 2
FIG. 4 according to the switching state of 9, 30, 31, 38, 40
FIG. 6 is a circuit diagram showing a connection relationship of circuits on the left side of the middle AA ′, which are respectively shown in FIGS. 6A to 6D when the control signals (a) to (d) of FIG. 5 are at a high level. Like Here, the switch “pch” in FIG.
It is assumed that it is connected to the middle "a" to "d".

Here, “V _in ” and “V _ip ” are input voltages, “V _rp1 ”, “V _rn1 ”, “V _{rp 2} ”, and “V”.
_RN2 "is the reference voltage output of the reference voltage generating circuit 43," V _rp1 "and" V _rn1 "output of the variable gain amplifier 22," V _rp2 "and" V _RN2 "is 1-bit D / A converter 21 The control signal (a) to the control signal (d) in Fig. 5 are sequentially switched to the high level every time "t".

In FIG. 6 (A), the variable capacitors 25a and 2 are provided.
Input voltage "V" after 5 hours "0" in 5b_in(0) "and"
V_ip(0) ”is charged, and the reference voltage in FIG.
Pressure "V _rp1 "And" V_rn1 "And subtracted. Also, capacity
39a and 39b have an input voltage "V" after time "t"
_in(T) "and" V_ip(T) ”is charged.
Charges charged in the capacitors 39a and 39b in (C)
Is charged to the capacities 39c and 39d. Furthermore, FIG.
Charges charged in the capacitors 39c and 39d in (D)
Is charged in the variable capacitors 25a and 25b.

Referring again to FIG. 6A, the variable capacitor 25a and the variable capacitor 25a
And input voltage “V” after time “4t” at 25b_in(4t) ”
And "V_ip(4t) ”is charged, but it is variable at this point
Input voltage "V" after time "t" is applied to the capacitors 25a and 25b.
_in(T) "and" V_ip(T) ”is charged,
If the input voltage is direct current, "V_in(4t) "and" V
_ip(4t) "is" V_in(T) "and" V_ip(T) ”
Since they are almost the same, the variable capacitors 25a and
No charging current flows to 5b. That is, the variable capacitance 25a and
And a circuit composed of 25b etc.
Becomes

On the other hand, again in FIG. 6B, the capacitor 39a
And 39b, the input voltage “V _in (5
t) ”and“ V _ip (5t) ”are charged, but the capacitances 39c and 39d to the capacitances 39a and 3d in FIG. 6 (A) immediately before are charged.
Input voltage “V _in (t)” and “V after time“ t ”in 9b
_{Since ip} (t) ”is charged, the charging current from the input voltage to the capacitors 39a and 39b does not flow for the same reason as described above, and the circuit including the capacitors 39a and 39b also has a high input impedance.

As a result, by providing the voltage holding circuit 13 in the input stage, holding the voltage for a certain period of time, and precharging this voltage to the variable capacitors 25a and 25b or the capacitors 39a and 39b of the input stage, Charge current is almost "
It becomes 0 "and has a high input impedance. Also, CMO
Since it can be composed of an S switched capacitor, the power consumption is small and the cost is low.

The third embodiment shown in FIGS. 3 and 4 shows a second-order ΣΔ A / D converter.
It is not limited to the A / D converter, but may be, for example, a first-order ΣΔA / D
By providing the voltage holding circuit 13 at the input stage of the converter, high input impedance can be achieved.

[0028]

As is apparent from the above description,
The present invention has the following effects. 1-bit D / A
The reference voltage supplied to the converter is variable, and the reference voltage is changed according to the input voltage, resulting in low power consumption and low cost, and by providing a voltage holding circuit in the input stage, high input impedance High precision Σ
A ΔA / D converter can be realized.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing a first embodiment of a high precision ΣΔ A / D converter according to the present invention.

FIG. 2 is a configuration block diagram showing a second embodiment of the high precision ΣΔ A / D converter according to the present invention.

FIG. 3 is a configuration block diagram showing a third embodiment of the high precision ΣΔ A / D converter according to the present invention.

FIG. 4 is a circuit diagram showing details of a third embodiment shown in FIG.

FIG. 5 is a timing diagram showing output timings of outputs and the like of a switch control circuit.

FIG. 6 is a circuit diagram showing a circuit connection relationship depending on a switching state of a switch circuit.

FIG. 7 is a configuration block diagram showing an example of a conventional high precision ΣΔ A / D converter.

FIG. 8 is a configuration block diagram showing details of a second-order ΣΔ A / D converter.

[Explanation of symbols]

1 Multiplexer 2,15,22 Variable gain amplifier 3 ΣΔ A / D converter 4,6,11,14,17 Subtractor 5,7,12,16,19 Integrator 8 1-bit A / D converter 9,21 1 Bit D / A converter 10, 10a, 43 Reference voltage generating circuit 13 Voltage holding circuit 18 Amplifier 20 Adder 23, 24, 26, 29, 30, 31, 31, 33, 38, 4
0 switch circuit 25a, 25b variable capacitance 28a, 28b, 32a, 32b, 35a, 35b, 3
9a, 39b, 39c, 39d Capacitance 27, 34, 41 Differential input / output amplifier 36 Comparator 37 Flip-flop circuit 42 Switch control circuit

Claims (2)

[Claims] 1. In a ΣΔ A / D converter, a subtractor whose analog input is connected to one input, an integrator to which the output of this subtractor is connected, and an output of this integrator are connected and a digital A 1-bit A / D converter that outputs an output; a 1-bit D / A converter to which the output of the 1-bit A / D converter is connected and whose output is connected to the other input of the subtractor; High precision ΣΔ characterized by comprising a variable reference voltage generating circuit for supplying a reference voltage to a 1-bit D / A converter
A / D converter. 2. In a ΣΔ A / D converter, a voltage holding circuit to which an analog input is connected, a subtractor to which the output of this voltage holding circuit is connected to one input, and an output of this subtractor are connected. A first variable gain amplifier, a second variable gain amplifier whose output is connected to the other input of the subtractor, an integrator to which the output of the first variable gain amplifier is connected, A 1-bit A / D converter connected to the output and outputting a digital output, and a 1-bit D / D converter connected to the output of the 1-bit A / D converter and connected to the second variable gain amplifier A high-accuracy ΣΔA / D converter characterized by including an A / A converter.