JPH0469783U - - Google Patents
Info
- Publication number
- JPH0469783U JPH0469783U JP11320690U JP11320690U JPH0469783U JP H0469783 U JPH0469783 U JP H0469783U JP 11320690 U JP11320690 U JP 11320690U JP 11320690 U JP11320690 U JP 11320690U JP H0469783 U JPH0469783 U JP H0469783U
- Authority
- JP
- Japan
- Prior art keywords
- value
- address
- counter
- count value
- end value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図は、本考案の実施例に係るアドレス制御
回路の回路図である。第２図は、第１図の回路の
各部論理値のタイミングチヤート図である。第３
図は、従来例に係るアドレス制御回路の回路図で
ある。第４図及び第５図は、本考案の実施例を応
用したパターンジエネレータに使用するパターン
メモリの記憶内容を示すアドレスマツプ図である
。
FIG. 1 is a circuit diagram of an address control circuit according to an embodiment of the present invention. FIG. 2 is a timing chart of logical values of each part of the circuit of FIG. 1. Third
The figure is a circuit diagram of an address control circuit according to a conventional example. 4 and 5 are address map diagrams showing the stored contents of a pattern memory used in a pattern generator to which an embodiment of the present invention is applied.
Claims (1)
アドレスカウンタと、該カウンタのカウント値が
予め設定される終了値と比較するアドレスコンパ
レータとを具備し、前記初期値と前記終了値との
間のカウント値を繰り返し出力するアドレス制御
回路。 (2) 設定される初期値からカウントを開始する
アドレスカウンタと、該カウンタのカウント値が
予め設定される終了値と比較するアドレスコンパ
レータとを具備し、発生させようとする波形パタ
ーンに対応するデータを記憶させたパターンメモ
リに対し、前記初期値と前記終了値との間のカウ
ント値を繰り返し出力するパターンジエネレータ
用アドレス制御回路。[Claims for Utility Model Registration] (1) An address counter that starts counting from a set initial value, and an address comparator that compares the count value of the counter with a preset end value, and an address control circuit that repeatedly outputs a count value between the end value and the end value. (2) Equipped with an address counter that starts counting from a set initial value and an address comparator that compares the count value of the counter with a preset end value, the data corresponds to the waveform pattern to be generated. An address control circuit for a pattern generator that repeatedly outputs a count value between the initial value and the end value to a pattern memory storing the .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11320690U JPH0469783U (en) | 1990-10-29 | 1990-10-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11320690U JPH0469783U (en) | 1990-10-29 | 1990-10-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0469783U true JPH0469783U (en) | 1992-06-19 |
Family
ID=31860763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11320690U Pending JPH0469783U (en) | 1990-10-29 | 1990-10-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0469783U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07146342A (en) * | 1993-11-22 | 1995-06-06 | Nec Corp | Address control memory circuit |
-
1990
- 1990-10-29 JP JP11320690U patent/JPH0469783U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07146342A (en) * | 1993-11-22 | 1995-06-06 | Nec Corp | Address control memory circuit |
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