JPS60136319A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS60136319A
JPS60136319A JP59195910A JP19591084A JPS60136319A JP S60136319 A JPS60136319 A JP S60136319A JP 59195910 A JP59195910 A JP 59195910A JP 19591084 A JP19591084 A JP 19591084A JP S60136319 A JPS60136319 A JP S60136319A
Authority
JP
Japan
Prior art keywords
layer
silicon
region
oxide
semiconductor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59195910A
Other languages
English (en)
Japanese (ja)
Other versions
JPH032338B2 (enExample
Inventor
ヘンリー・ジヨン・ゲーペル、ジユニア
チヤールス・アンドリユー・シエーフアー
フランシス・ロジヤー・ホワイト
ジヨン・マイケル・ワーソーン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS60136319A publication Critical patent/JPS60136319A/ja
Publication of JPH032338B2 publication Critical patent/JPH032338B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P14/6502—
    • H10P14/6308—
    • H10P14/6309—
    • H10P14/6322—
    • H10P14/69215—
    • H10P95/90—
    • H10P14/6927—
    • H10P14/69433—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/911—Differential oxidation and etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
JP59195910A 1983-12-23 1984-09-20 半導体装置の製造方法 Granted JPS60136319A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/564,880 US4527325A (en) 1983-12-23 1983-12-23 Process for fabricating semiconductor devices utilizing a protective film during high temperature annealing
US564880 1983-12-23

Publications (2)

Publication Number Publication Date
JPS60136319A true JPS60136319A (ja) 1985-07-19
JPH032338B2 JPH032338B2 (enExample) 1991-01-14

Family

ID=24256275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59195910A Granted JPS60136319A (ja) 1983-12-23 1984-09-20 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US4527325A (enExample)
EP (1) EP0158715B1 (enExample)
JP (1) JPS60136319A (enExample)
DE (1) DE3481148D1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3583472D1 (de) * 1984-08-28 1991-08-22 Toshiba Kawasaki Kk Verfahren zum herstellen einer halbleiteranordnung mit gateelektrode.
JP2644776B2 (ja) * 1987-11-02 1997-08-25 株式会社日立製作所 半導体装置及びその製造方法
US5252501A (en) * 1991-12-30 1993-10-12 Texas Instruments Incorporated Self-aligned single-mask CMOS/BiCMOS twin-well formation with flat surface topography
US5770492A (en) * 1995-06-07 1998-06-23 Lsi Logic Corporation Self-aligned twin well process
US5763302A (en) * 1995-06-07 1998-06-09 Lsi Logic Corporation Self-aligned twin well process
US5583062A (en) * 1995-06-07 1996-12-10 Lsi Logic Corporation Self-aligned twin well process having a SiO2 -polysilicon-SiO2 barrier mask
US5670393A (en) * 1995-07-12 1997-09-23 Lsi Logic Corporation Method of making combined metal oxide semiconductor and junction field effect transistor device
US5872052A (en) 1996-02-12 1999-02-16 Micron Technology, Inc. Planarization using plasma oxidized amorphous silicon
US6297170B1 (en) 1998-06-23 2001-10-02 Vlsi Technology, Inc. Sacrificial multilayer anti-reflective coating for mos gate formation
US11791271B2 (en) * 2020-09-30 2023-10-17 Tokyo Electron Limited Monolithic formation of a set of interconnects below active devices

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3921283A (en) * 1971-06-08 1975-11-25 Philips Corp Semiconductor device and method of manufacturing the device
US3999213A (en) * 1972-04-14 1976-12-21 U.S. Philips Corporation Semiconductor device and method of manufacturing the device
US3911168A (en) * 1973-06-01 1975-10-07 Fairchild Camera Instr Co Method for forming a continuous layer of silicon dioxide over a substrate
US3920481A (en) * 1974-06-03 1975-11-18 Fairchild Camera Instr Co Process for fabricating insulated gate field effect transistor structure
GB1559583A (en) * 1975-07-18 1980-01-23 Tokyo Shibaura Electric Co Complementary mosfet device and method of manufacturing the same
US4214917A (en) * 1978-02-10 1980-07-29 Emm Semi Process of forming a semiconductor memory cell with continuous polysilicon run circuit elements
JPS5693344A (en) * 1979-12-26 1981-07-28 Fujitsu Ltd Manufacture of semiconductor device
US4240845A (en) * 1980-02-04 1980-12-23 International Business Machines Corporation Method of fabricating random access memory device
US4398338A (en) * 1980-12-24 1983-08-16 Fairchild Camera & Instrument Corp. Fabrication of high speed, nonvolatile, electrically erasable memory cell and system utilizing selective masking, deposition and etching techniques
US4412375A (en) * 1982-06-10 1983-11-01 Intel Corporation Method for fabricating CMOS devices with guardband
GB2140202A (en) * 1983-05-16 1984-11-21 Philips Electronic Associated Methods of manufacturing semiconductor devices

Also Published As

Publication number Publication date
JPH032338B2 (enExample) 1991-01-14
EP0158715A2 (en) 1985-10-23
US4527325A (en) 1985-07-09
EP0158715A3 (en) 1986-07-16
EP0158715B1 (en) 1990-01-24
DE3481148D1 (de) 1990-03-01

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