JPS60134518A - デイジタル遅延回路 - Google Patents

デイジタル遅延回路

Info

Publication number
JPS60134518A
JPS60134518A JP58242560A JP24256083A JPS60134518A JP S60134518 A JPS60134518 A JP S60134518A JP 58242560 A JP58242560 A JP 58242560A JP 24256083 A JP24256083 A JP 24256083A JP S60134518 A JPS60134518 A JP S60134518A
Authority
JP
Japan
Prior art keywords
signal
circuit
field effect
level
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58242560A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0222568B2 (enrdf_load_stackoverflow
Inventor
Jiro Shimada
島田　二郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58242560A priority Critical patent/JPS60134518A/ja
Publication of JPS60134518A publication Critical patent/JPS60134518A/ja
Publication of JPH0222568B2 publication Critical patent/JPH0222568B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
JP58242560A 1983-12-22 1983-12-22 デイジタル遅延回路 Granted JPS60134518A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58242560A JPS60134518A (ja) 1983-12-22 1983-12-22 デイジタル遅延回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58242560A JPS60134518A (ja) 1983-12-22 1983-12-22 デイジタル遅延回路

Publications (2)

Publication Number Publication Date
JPS60134518A true JPS60134518A (ja) 1985-07-17
JPH0222568B2 JPH0222568B2 (enrdf_load_stackoverflow) 1990-05-21

Family

ID=17090903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58242560A Granted JPS60134518A (ja) 1983-12-22 1983-12-22 デイジタル遅延回路

Country Status (1)

Country Link
JP (1) JPS60134518A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62282823A (ja) * 1986-05-28 1987-12-08 Fanuc Ltd ワイヤ放電加工機の３点支持ガイド
JP2006333105A (ja) * 2005-05-26 2006-12-07 Toshiba Microelectronics Corp データラッチ回路およびそれを用いた液晶表示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62282823A (ja) * 1986-05-28 1987-12-08 Fanuc Ltd ワイヤ放電加工機の３点支持ガイド
JP2006333105A (ja) * 2005-05-26 2006-12-07 Toshiba Microelectronics Corp データラッチ回路およびそれを用いた液晶表示装置

Also Published As

Publication number Publication date
JPH0222568B2 (enrdf_load_stackoverflow) 1990-05-21

Similar Documents

Publication Publication Date Title
US4843254A (en) Master-slave flip-flop circuit with three phase clocking
US4691122A (en) CMOS D-type flip-flop circuits
US20070146033A1 (en) Circuit arrangement and method for operating a circuit arrangement
CA1157111A (en) Dynamic ratioless circuitry for random logic applications
US3862440A (en) Pulse transforming circuit arrangements using a clock pulse responsive delayed inverter means
JPH0158896B2 (enrdf_load_stackoverflow)
JPH0375976A (ja) 半導体集積回路装置
US4894559A (en) Buffer circuit operable with reduced power consumption
JP2591066B2 (ja) アナログスイッチ回路
US4420695A (en) Synchronous priority circuit
US20180262191A1 (en) Switch control circuit
US3708688A (en) Circuit for eliminating spurious outputs due to interelectrode capacitance in driver igfet circuits
JPS60134518A (ja) デイジタル遅延回路
JPH1173775A (ja) 半導体記憶装置の出力回路
US3588527A (en) Shift register using complementary induced channel field effect semiconductor devices
US4451908A (en) Address Buffer
US3925685A (en) Time sharing information circuit
CA1265850A (en) Complementary input circuit with nonlinear front end
JPS63304494A (ja) 半導体集積回路
US3813563A (en) Flip-flop circuit
JP2541244B2 (ja) クロック発生回路
JPS6012352Y2 (ja) プッシュプル型ゲ−ト回路
US3854059A (en) Flip-flop circuit
JP4075082B2 (ja) 位相差検出器及び半導体装置
JPS622485B2 (enrdf_load_stackoverflow)