JPS60134518A - Digital delay circuit - Google Patents

Abstract

PURPOSE:To decrease power consumption, to attain ease of miniaturization and to improve the reliability by using a few transistors (TRs) so as to allow the TRs to respond to the one-way level change of an input signal only. CONSTITUTION:When an output terminal Q and a circuit point E are in preset state, the terminal Q gives a negative potential VSS of the power supply even if a clock control signal C is inputted continuously to TRs T15, T16 so long as no level inversion is caused to an input signal D. When the level of the signal D changes from low to high state and the TR14 is brought into the conductive state, and when the T15 is conductive at the leading of the signal C, the potential of the circuit point E changes suddenly from a positive potential VDD to the potential VSS, a TR13 is conductive, and the T16 is conductive at the trailing of the signal C, then the potential of the terminal Q changes from the potential VSS to the potential VDD and the level is stored in a capacitor. Thus, the signal D is synchronized with the signal C, delayed by one clock time and outputted from the terminal Q.

Description

[Detailed description of the invention] 〔Technical field〕 The invention particularly relates to synchronous digital delay circuits.

[Background of the invention]

Synchronous digital delay circuit ld, which is widely used today,
Even if it uses a D-type 7-ribbon flop, the master
Slave type JK7 lip/7r:! Regardless of whether it is due to the knobs, all of the circuits are designed to handle input signals that change level 20,000 times. That is, it is configured to respond to changes in the human input signal from low to high and from high to low, respectively. However, depending on the signal processing function, a configuration is often used that responds only to a signal change in one direction from low to high or from high to low in the input signal to be delayed. For example, it has an input switch terminal, which is normally in a low state and changes to a high level when the switch is turned on.

This is a case where the internal circuit operates in response to this change and automatically stops. If a circuit with a conventional configuration is used as it is for this purpose, it will include circuit elements that are completely unnecessary in terms of function, which is extremely wasteful.

[Prior art]

FIG. 1 is a connection circuit diagram of a known dynamic type digital delay circuit that utilizes gate capacitance retention of field effect transistors, and is known as having the simplest circuit configuration. This circuit consists of two transfer gate transistors ′↓l+ T2 controlled by an input signal.
and input side transfer gate transistor l11 controlled by clock control No. 18 C and C, respectively.
3. A total of eight transistors are used: a transfer gate transistor T7'1'8 and a gate 8m holding transistor T5 and T6 which act to provide a one clock time delay to the input signal. Here, the circled transistors represent P-channel type field effect transistors, and the unmarked transistors represent N-channel type field effect transistors.
V8S and Q are the positive potential, negative potential and delay output terminals of the power supply, respectively. The operation of this circuit is well known and will therefore be omitted.

Since this delay circuit is constructed symmetrically with respect to the human input signal and the two clock control signals C1C, and performs dynamic operation, the number of circuit elements is relatively small, and only eight transistors are required. However, even if this circuit has a small number of circuit elements, if it is used as a circuit that responds only to a level change of one of the signals to be delayed, at least two transistors T3 m corresponding to one clock control signal C or C are used. TB or Ill, 1it7 will be completely functionally playable. Furthermore, in the case of a circuit using a D-type slip/70 tube or a mask/slave type JK71J tube/70 tube, which requires a larger number of circuit elements, the number of unnecessary circuit elements for one function increases even more.
This not only creates waste in the circuit configuration, but also unnecessarily increases the size of the semiconductor chip, wastes power pointlessly, and even adversely affects reliability.

[Purpose of the invention]

In view of the above circumstances, it is an object of the invention to provide a digital delay circuit suitable for responding only to changes in the level of an input signal.

[Structure of the invention]

The inventive digital delay circuit has a first . A fourth transistor connected in series between the second and third transistors and the first and second power supply terminals. The fifth and sixth transistors have a human input signal, the second and fifth transistors receive a clock signal, the third transistor receives the first preset No. 16, and the fourth transistor receives a human input signal. A second preset signal having a complementary relationship with the first preset signal is supplied to the sixth transistor with the signals obtained at the connection points of the second and third transistors, respectively, and the signals obtained at the connection points of the fourth and fifth transistors are supplied to the sixth transistor. The main feature is that the output signal is generated from the connection point of the transistor.

According to the present invention, the digital delay circuit can be constructed from only six transistors, all of which are involved in the delay function, so there is no waste in circuit elements.

The semiconductor chip is miniaturized, power consumption can be reduced, manufacturing is simplified, and reliability can be improved.

〔Example〕

The invention will now be described in detail with reference to one drawing.

2(a) and 2(b) are a connection circuit diagram and a symbol diagram showing an embodiment of the invention, respectively, and FIG. 3 is a timing chart diagram for explaining the operation of the embodiment of the invention. be. The non-embodiment circuit responds to a change in level of an input signal from low to high, and parts common to those in FIG. 1 are given the same reference numerals. The non-example circuit includes an N-channel field effect transistor Tll that is turned on by the first preset signal p, transfers the negative potential V58 of the power supply to the output terminal Q, and holds it with the load capacitance, and the first preset signal p. The P-channel type field effect transistor Txz is made conductive by the preset signal P having a complementary relationship with the positive potential VDD of the power source and transferred to the circuit point E connected to the drain, and is made non-conductive by the potential of this circuit point E.

A P-channel field effect transistor 1 is configured to prohibit the positive potential vDD of the power supply connected to the source from being transferred to the output terminal QK, and maintain this state with the gate capacitance. When the input signal level changes from low to high, the three circuit elements of the preset circuit consisting of
DD is connected to one circuit element of the input signal circuit consisting of an N-channel field effect transistor T14 extending to the drain side, and is exclusively connected to the rising edge of clock control No. 1g C, and extended to the negative potential of the power supply ■ss'5 circuit point E. The N-channel field effect transistor 'I'ss conducts the transistor T13, which has been preset to a non-conducting state, and cancels the state in which transfer of the positive potential VDD of the power supply to the output terminal Q side is inhibited. A P-channel field effect transistor that conducts when signal C falls at 9 and transfers the positive potential of the power supply from the transistor Tss extending to the output terminal Q side ■DD to the output terminal Q and holds it within the load capacitance. T1
and two circuit elements of a clock control signal circuit consisting of 6.

The transistor T1t, which is preset to transfer the negative potential vss of the output terminal QK source, receives the preset signal P.
becomes non-conductive when the level is reversed, but this negative potential Vs8 is the period from when the level of the input signal 1) changes from low to high until the next clock control signal C falls, that is, the third During the time span 11 shown in the figure surrounded by a dashed line, the load capacitance connected to the output terminal Q is set so as to maintain its capacity, and the positive potential vDD' of the circuit point EK is set! The transistor T1g, which is preset to hold il, is also connected to the preset signal P whose level is inverted, the level of the human input signal changes from low to high, and the time until the next clock control signal C rises, i.e. Settings are made so that this positive potential can be maintained in the gate capacitance during a time width t2 shown surrounded by a dashed line in FIG.

As mentioned above, if the output terminal Q and the circuit point E are in the preset state, it is assumed that the clock control signal C is continuously input to the transistors '11s and T16 as long as there is no level reversal due to the input signal. Also, output terminal Q
is not affected at all and continues to output the negative potential Vss of the power supply. Here, the level of the input signal is changed from low to high, and the transistor l1114 becomes conductive.
Then, when the clock control signal C rises to 9, the transistor'
When I'ts becomes conductive, the potential at the first circuit point E completely changes from the positive potential vDD, which has been maintained, to the negative potential VSS. Therefore, the transistor T13 which was in the non-quadruple state
becomes conductive at this negative potential ■ss, and then at the fall of the control signal C, the transistor 'I'ta becomes conductive, so that the output terminal Q changes from the negative potential Vs8 to the positive potential VD.
The potentials of the 0 circuit point E and the output terminal Q that change to D are the transistors Ill, 5, which are controlled by the clock control code C.
Even while T16 is rendered non-conductive, the respective capacitances are maintained by the gate capacitance and the load capacitance, so the output level of the output terminal Q is held at the positive potential VDD. Third
The time widths t3 and t4 shown surrounded by dashed lines in the figure are:
The holding time of each of the circuit point E and the output terminal Q is shown. Thus, the input signal is outputted from the output terminal Q in synchronization with the clock control signal C and delayed by the clock time. Therefore, the non-embodiment circuit is shown in N2 diagram (b
)V) can be represented by a symbolization circuit F as follows.

FIGS. 4(a) and 4(b) are a connection circuit diagram and a symbol diagram showing another embodiment of the present invention, respectively, and FIG. 5 is a timing chart for explaining the operation of the non-transparent embodiment.

The non-embodiment circuit responds to a change in level of a human input signal from high to low, and the same reference numerals are used for parts common to those in FIG. The non-example circuit consists of a P-channel field effect transistor T21 that conducts with the preset signal π and transfers the positive potential to the "DD" output terminal Q of the power source to hold the load, and a P-channel field effect transistor T21 that conducts with the preset signal Potential ■ss 'e N-channel field effect transistor T transferred to circuit point E' connected to drain
22 and the negative potential of the power supply connected to the source vs3. is prohibited from being transferred to the output terminal Q, and the three circuit elements of the preset circuit consisting of the N-channel field effect transistor T23, which maintains this state with the gate capacitance, and the human input signal change from high to low level. When changing, it conducts and turns the positive power supply ■DD
One circuit element of the human power signal circuit consisting of a P-channel field effect transistor Tu with the voltage applied to the drain side and the positive potential VDD of the power supply connected to the circuit point E' The transistor Tz3e4, which is preset to a non-conducting state, is made to conduct.

The P-channel field effect transistor T26 cancels the state in which the transfer of the negative potential VSS of the power supply to the output terminal side is inhibited, and the rising edge of the clock signal C is made conductive at 9 with an interval of one clock time, and is extended to the output terminal Q side. Two circuit elements of a clock control signal circuit consisting of an N-channel field effect transistor T26 transfer the negative potential VsS of the power supply from the transistor T23 to the output terminal QK and hold it in the load capacitance connected to the output terminal Q. include.

The non-embodiment circuit differs from the embodiment circuit described above in that, prior to the level reversal of the human input signal, the output terminal Q is connected to the positive potential VD of the power supply.
It is preset to output D. However, there is no essential difference in circuit operation. That is, the transistor 'I'zi, which is preset to transfer the positive potential "DD" of the power supply to the output terminal Q, becomes non-conductive when the level of the preset signal P is reversed, but this positive potential ■DD is then transferred to the The time from when the level of the clock signal changes from high to low until the next clock control signal C rises, that is, the fifth
During the time width tI' shown in the figure surrounded by a dashed line, the load capacitance connected to the output terminal Q is provided so that the capacity can be maintained, and the negative potential ■s5 of the power supply is applied to the circuit point E'. The transistor T23, which is preset to hold the preset signal P, maintains the level until the level of the preset signal P is inverted, the level of the human input signal changes from NOI to LOW, and the next clock control signal C falls, that is, the fifth This negative potential is provided so that the gate capacitance can be maintained during the time width t2' indicated by the dashed line in the figure.

If the output terminal Q and the circuit point E' are in this preset state, the clock control 1 is applied to the transistors T211 and T26 unless the input signal inverts the level.
Even if No. 5C is input continuously, the output terminal Q is not affected at all and continues to output the positive potential ■DD of the power supply. Here, the level of the input signal changes from high to low, transistor T24 enters the 4-way state, and then transistor T2S becomes conductive at the fall of the clock control signal C, and the circuit point E' v) potential remains as it is now. negative potential V
The potential changes from SS to positive potential VDD. Therefore, the transistor T23, which was in a non-conductive state, is tied to this positive potential VDD, and then, when the clock control signal C rises to 9, the transistor T26 becomes conductive, and the output terminal Q changes from the positive potential VDD to the negative potential VSS. The potential at the zero circuit point E' and the output terminal Q is maintained by the gate capacitance and load capacitance, respectively, even while the transistors T25 and T26 controlled by the clock-controlled consumption C are rendered non-conductive. , the output level of the output terminal Q is held at the negative potential ■ss. Time widths t3' and t4' shown surrounded by dashed lines in FIG. 5 indicate the capacitance retention time of the circuit point E' and the output terminal Q, respectively. The input signal is then synchronized with the clock control signal C.

The signal is delayed by one clock time and output from the output terminal Q. Therefore, the non-embodiment circuit can be represented by a symbol circuit F' as shown in FIG. 4(b).

In both of the above two embodiments, the preset signal p is used to control the negative potential Vss side of electrolytic erosion, and the preset signal pf is used to control the positive potential VDD side, but the reverse preset circuit configuration is also easily possible. It is.

6 and 7 are connection circuit diagrams showing other embodiments of Fugenmei, in which a preset signal P is used to control the negative potential Vss side of the power supply, and a preset signal P' is used to control the positive potential VDD of the power supply. lz are used in correspondence with each other. The transistors in these embodiment circuits are labeled with symbols corresponding to their functions in the two embodiment circuits described in detail above. Here, FIG. 6 shows a delay circuit that responds to a level change from low to high in the input signal, and FIG. 7 shows a delay circuit that responds to a level change from high to low.

At this time, it is necessary to make the preset signal level higher than that of the input signal, but I think there is no need to explain the circuit operation again, so I will omit it.

FIGS. 8 and 9 show the digital delay circuit (f) of the present invention.
-m cascaded non-inventive application example diagram and timing chart diagram respectively.

In this circuit diagram, an inventive digital delay circuit F or F' is connected to an input signal D1. The clock control signal C1.degree. is cascaded to the preset signal PL produced by the preset signal PL and the foot circuit N4, resulting in a 1 clock time delay output 91.22172 time delay output Q2.・
. . . Delayed outputs Qm k of m clock times can be individually output.

As explained above, the inventive digital delay circuit responds only to level changes in one direction of the human input signal, consists of only six transistors, and is configured as a semiconductor device with low power consumption and miniaturization. In addition, since only one clock control signal is required, when high-speed operation is required, there are fewer power transistors that increase transconductance, which is extremely advantageous in circuit design and manufacturing. The contribution it makes to the above request is also extremely large.

[Brief explanation of the drawing]

FIG. 1 is a connection circuit diagram of a known dynamic type digital delay circuit using the gate latch function of a field effect transistor, and FIGS. 2(a) and (b) are. FIG. 3 is a timing chart diagram for explaining the operation of a non-embodiment, and FIGS. V) A connection circuit diagram and a symbol diagram showing the embodiment, FIG. 5 is a timing chart diagram for explaining the operation of this embodiment, and FIGS. Connection circuit diagram showing all examples, Figure 8 and Figure 9 Q.
FIG. 2 is an example diagram and a timing chart of an uninvented circuit in which m uninvented digital delay circuits are connected in cascade. P, P, PL, PI, ... = Preset signal,
C, C, CI... Clock control signal, D, DI
・Mountain...Input signal, Q, Qs, Q2,...
...Qm...Output terminal, E, E' River...Circuit point kvDD...Positive potential of power supply" ss...
・Negative NZ position of the power supply, N...tongue-to-mouth circuit, F, F'...uninvented symbolization circuit - T1, T3, T5, T7, T
ll・'f' I 4・T15゜722m "23 *
T26 w T32 m T34 m ”r35I
'r41 m'I'ia * T46...N-channel field effect transistor T2 * T4
* T6・T8・1゛L2・'rta・'I'ts・T
24m'124 # T25・”S1* Tss j
T36 e T42・1゛44・T45゛...P channel type field effect transistor htl*t2*t3 m
t4 * tIZ "2'e t3's 14/...
... Capacity retention time width. 7 flashes (a no (b) Fig. 2 Vv.

Claims (1)

[Claims] w<
1. w2 and the third field effect transistor are connected in series between the power supply terminal 7'2: the fourth field effect transistor. 5th and 6th
It has a field effect transistor. a human input signal is provided to the first field effect transistor, a clock signal is provided to the second and fifth (1) field effect transistors, and a first preset signal is provided to the third field effect transistor; A second preset signal having a complementary relationship with the first bullet signal is supplied to the fourth field effect transistor, and the second and third field effect transistors are connected to the sixth field effect transistor. A digital delay circuit, characterized in that a signal obtained at a point is supplied to a point, and an output signal is taken out from a connection point of the fourth and fifth field effect transistors.