JPS60130154A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the disconnection of the upper Si layer by a method wherein the titled device having at least two layers of polycrystalline Si superposed on a substrate via insulation oxide film is provided with an Si layer pattern provided on a selected Si layer inside the pattern outer edge of the arbitrary Si layer. CONSTITUTION:An SiO2 film 12 is produced on the surface of the Si substrate 11 by heat treatment, and a polycrystalline Si layer 13 of a required shape is formed. Conductivity is given by P ion implantation, and an SiO2 film 14 is produced over the entire surface including the layer 13 by another heat treatment. Next, a polycrystalline Si layer 15 is deposited over the entire surface and patterned, thus being turned into an Si layer 15' not going beyond the edge of the layer 13. The entire surface including it is covered with an SiO2 film 16, and apertures to exposed part of the layers 15' and 13 are bored in the film 16. Thereafter, an extending Al wiring 18 is adhered on the film 16 while being made to abut against the layers 15' and 13 exposed in the apertures 17. Thus, the disconnection of the layer 15' is avoided without making the layer 15' swelling out of the edge of the layer 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device and is applied to a semiconductor device having a polycrystalline silicon layer of 1% or more.

[Technical background of the invention]

In semiconductor devices, polycrystalline silicon layers are often used as r' electrodes. Sometimes, in places where a capacitor is required in a circuit, polycrystalline silicon 1-2 of 2 to 1 or more is sometimes provided to utilize the capacity of an oxide film having better characteristics than junction valleys. FIG. 1 is a cross-sectional view showing a semiconductor device having such two polycrystalline silicon layers, in which an oxide film 2 is formed on a silicon substrate 1, and a first polycrystalline silicon layer is formed on top of the oxide film 2. It is formed by three predetermined mehaturns. A second oxide film 4 is formed on this first polycrystalline silicon layer 3 and other oxide films 2, and a second polycrystalline silicon layer is formed on this second oxide film 4. 5 is formed. This second polycrystalline silicon 1fIj5 forms a capacitor using a second oxide film 4, which is a dielectric, sandwiched between it and the first polycrystalline silicon layer 3.
Since it also serves as an electrode lead line, it protrudes from above the first polycrystalline silicon layer 3 and moves onto the second oxide film 4 in a stepwise manner.

[Problems with background technology]

However, in such a conventional configuration, 5' in FIG.
As shown in a, the thickness of the second polycrystalline silicon No. 5 becomes thinner in the stepped portion, and there is a problem in that the wire is easily broken in this portion.

The film layer of such a stepped portion 5a tends to become thinner as the end face portion 3a of the first polycrystalline silicon layer 3 rises more steeply. Therefore, after the first polycrystalline silicon layer 3 is formed, a heat treatment is performed. Furthermore, it is possible to perform processing 2 such as forming another thin polycrystalline silicon layer and etching it to make the rise of the end face portion 3a gentler, but if such a method is adopted, the positional accuracy and the accuracy of the formed capacitance will be reduced. The problem is that it is inferior.

[Purpose of the invention]

The present invention has been made in view of the above problems.

An object of the present invention is to provide a semiconductor device in which the upper r- of two or more polycrystalline silicon layers superimposed via insulating oxide ayt is not disconnected.

[Summary of the Invention] In order to achieve the above object, the present invention provides a semiconductor device having at least two polycrystalline silicon layers superimposed on a substrate with an insulating oxide film 2 interposed therebetween. , above +n polycrystalline silicon layer patterns are formed inward from the outer edge of the polycrystalline silicon layer pattern of an arbitrary layer, and the upper 1- polycrystalline silicon layer pattern is formed inward from the outer edge of the polycrystalline silicon layer pattern of the lower layer. Since it does not protrude from the pattern, there is no step-like portion, and there is no disconnection in the upper polycrystalline silicon layer.

[Embodiments of the invention]

Below is Figure 2? An embodiment of the present invention will be described in detail with reference to the following.

FIG. 2 (W is a cross-sectional view showing the completed state of the capacitor portion of the semiconductor device according to the present invention, in which a first polycrystalline silicon film 1 is formed on a first oxide film 12 formed on a silicon substrate 11). -13 are formed in a predetermined pattern, a second oxide film 14 is formed on these, and a second polycrystalline silicon layer 15' is formed on this second oxide film 14.
is formed in a predetermined pattern, but the end face of this second polycrystalline silicon layer is always located inwardly from the end face of the first polycrystalline silicon layer formed below. There is. An insulating oxide film 16 is formed on all of these, and an aluminum wiring I8 is further provided on top of the insulating oxide film 16. It is connected to the first and second polycrystalline silicon layers 3 and 15' thereunder. Note that the polycrystalline silicon layers 13 and 15' are made conductive by doping them with impurities.

FIG. 2(a) to FIG. 2(2) are cross-sectional views 7''r of the states in each step of manufacturing the semiconductor device 1R according to the present invention.

First, silicon semiconductor substrate 11Y is thermally oxidized in an atmosphere of approximately 1000°C to form a silicon oxide film 12 of 10%
It is formed with a length of 14 of 0OA (Fig. 2 (&)). Next, a multi-layered silicon layer of about 400 OA was applied using the 1licVD method on top of this.
If a patterned polycrystalline silicon layer 13 is formed and photoetched to leave only a predetermined pattern 2 and remove the others, a patterned polycrystalline silicon layer 13 remains (FIG. 2(b)). This polycrystalline silicon layer 13 is made conductive by implanting ions such as phosphorus. Next, thermal oxidation is performed again in an atmosphere of about 1000° C. to form a second oxide film 14 with a thickness of 100 OA (FIG. 2(C)). Thereafter, a second σ polycrystalline silicon layer 'a?' is formed again using the CVD method. 400OA
2 (d)), this second layer is formed to a thickness of
The polycrystalline silicon layer 15 is etched using a photoetching technique so that the end portion is located within the outer line of the pattern of the underlying polycrystalline silicon layer 13, thereby forming a second polycrystalline silicon layer 15 which has been turned. This second polycrystalline silicon layer 15', which becomes layer 15', does not extend beyond the edge of the first polycrystalline silicon layer 130. Next, a silicon insulating film 16 is formed over the entire surface (see FIG. 2(f)).

Openings 17 reaching the polycrystalline silicon layers 13 and 15' are provided at the electrode lead-out positions (Fig. 2 (g)), aluminum is deposited on the entire surface, and a pattern is formed by performing a battering process to complete the process. Naru (Asahi 2 Zu Wholesale).

Although the above embodiments have been described assuming a canopy section, the transistor section can be formed using normal MO8 manufacturing techniques. Furthermore, the present invention can be applied even when the polycrystalline silicon layers are used as a pair of wires for the purpose of forming a capacitor and not for forming a capacitor.

Furthermore, although the embodiment shows a case in which two polycrystalline silicon layers overlap/twist, the present invention can also be applied to a case in which three or more polycrystalline silicon layers 1A overlap each other via an insulating pattern.

Furthermore, the present invention is applicable regardless of the conductivity type (n-type, p-type) of the semiconductor device and whether the substrate is a semiconductor substrate or an insulating substrate such as sapphire.

〔Effect of the invention〕

According to the present invention as described above, any 11! The pattern of the polycrystalline silicon layer is formed inward from the outer edge of the polycrystalline silicon L-pattern below, so that the upper polycrystalline silicon layer is not formed in a step-like manner. Therefore, disconnection can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a part of a conventional semiconductor device having two polycrystalline silicon layers, and FIG. 2 is a cross-sectional view showing the manufacturing process and formation state of the semiconductor device according to the present invention. 1.11... Semiconductor substrate, 2.12... First oxide film. 3.13...first polycrystalline silicon layer, 4. U...
Second oxide film, 5, 15, 15'... second polycrystalline silicon layer. 5a...Stepped portion, 16...Insulation t-, 17...
・Opening, I8... Aluminum wiring applicant's agent Kiyotori Inomata Figure 1 Figure 12

Claims (1)

Claims: A semiconductor device comprising at least two polycrystalline silicon layers overlaid on a substrate with an insulating oxide film interposed therebetween. The polycrystalline silicon I! A semiconductor device characterized in that an upper layer of polycrystalline silicon 1-pattern is formed inward from the outer edge of a polycrystalline silicon 1-pattern of any layer.