JPS6012761A - Photoelectric conversion device - Google Patents

Abstract

PURPOSE:To obtain the titled device sufficiently responding to high resolution by a method wherein the potential of a control electrode region of floating state providing in a semiconductor transistor is controlled via capacitor, where the potential is then controlled by means of a clamping diode during the action of carrier accumulation, read-out, and refreshing. CONSTITUTION:An n<-> type layer 5 is epitaxially grown on an n<+> type Si sunstrate 1 and formed into island form by means of an SiO2 or Si3N4 film 4 for element isolation, the base region 6 of a p type bi-polar transistor is diffusion- formed in the surface layer part of the island-formed layer 5, and an n<+> emitter region 7 is provided therein. Next, after the entire surface of covered with an SiO3 film 3, an aperture is bored, an Al wiring 8 to lead out signals is connected to the region 7, a floated electrode 9 whereon pulses are impressed via film 3 is provided on the region 6. Besides, an Al collector electrode 12 is adhered to the back surface of a substrate 1 via n<+> type layer 11, and then the surface of the device is irradiated with a light 20 while the potential of the electrode 9 is controlled by the clamping diode via capacitor generating in the element.

Description

[Detailed description of the invention] The present invention relates to a photoelectric conversion device.

In recent years, research on photoelectric conversion devices, especially solid-state imaging devices, has been
With the progress of semiconductor technology, this has been actively carried out, and in some cases it has begun to be put into practical use.

These solid-state imaging devices can be roughly divided into CCD type and M
It is classified into two types of OS. The CCD type imaging device is MO
A potential well is formed under the S capacitor electrode, and charges generated by incident light are accumulated in this well. During readout, these potential wells are sequentially moved by a pulse applied to the electrode to remove the accumulated charges. It uses the principle of transferring the data to the output amplifier section and reading it out. Furthermore, some CCD type imaging devices use a pn junction diode structure for the light receiving section and a CCD structure for the transfer section. On the other hand, the lVtO3 type imaging device is
The charge generated by the incidence of light is accumulated in each of the photodiodes made of pn junctions that make up the light receiving section, and during readout, the MOS connected to each photodiode is
It uses the principle that the accumulated charge is read out to the output amplifier section by sequentially turning on the switching transistors. “The CCD type imaging device has a relatively simple structure and
In terms of the noise that can be generated, only the value in the capacity of the charge detector consisting of a floating diffusion in the final stage contributes to random noise, so it is a relatively low-noise imaging device and is capable of low-light photography. However, CCD
Since the MO8 type amplifier is on-chip as the output amplifier due to the process of making a type imaging device, the interface between the silicon and the SiO2 film generates both images and noticeable I/F I sound. do. Therefore, although it is said to have low noise, there are limits to its performance. Furthermore, if the number of cells is increased to achieve higher density in order to achieve higher resolution, the general charge that can be stored in one potential well will decrease, making it impossible to maintain a dynamic range. -This becomes a big problem as the resolution increases. In addition, since CCD-type imaging devices transfer charge while sequentially moving potential wells, even if there is a defect in one of the cells, charge transfer may stop there, or It also has the disadvantage that it becomes extremely poor and the manufacturing yield cannot be improved.

On the other hand, MOS type imaging devices are structurally a little more complex than CCD type imaging devices, especially frame transfer type devices, but they can be configured to increase the storage capacity.
It has the advantage of having a wide dynamic range.

Further, even if one of the cells has a defect, the defect does not affect other cells because of the X-Y addressing method, which is advantageous in terms of manufacturing yield. However, in this MOS type imaging device, since a wiring capacitor ψ is connected to each photodiode during signal readout, an extremely large signal voltage drop occurs, resulting in a droop in the output voltage. This causes a large amount of random noise, and fixed pattern noise is mixed in due to variations in parasitic noise in each photodiode and horizontal scanning MOS switching transistor.
Compared to conventional imaging devices, these devices have drawbacks such as difficulty in low-light photography.

Furthermore, in the future, as the resolution of imaging devices increases, the size of each cell will be reduced and the amount of accumulated charge will decrease. On the other hand, the wiring density, which is determined by the chip size, does not decrease much even if the line width is made thinner, so the MOS type imaging device becomes increasingly disadvantageous in terms of S/N.

Although CCD type and MOS type image pickup devices have advantages and disadvantages as described in 1-1 above, they are gradually approaching a level of practical use. However, it can be said that there are major problems with the quality of the wood in order to further increase the resolution that will be required in the future.

In honor of those solid-state imaging devices, Japanese Patent Application Laid-Open No. 58-15087
8 ゛Semiconductor imaging device゛, open/close 58-157073
“Semiconductor imaging device”, JP 58-185473 “A new method has been proposed for semiconductor imaging device. CC
D type.

While MOS-type imaging devices accumulate charges generated by incident light in the main 'It pole (e.g. source of a MOS transistor), the method proposed here accumulates charges generated by incident light. , control electrode (e.g. bipolar
base of the transistor.

The new idea of controlling the flowing current using the charges accumulated in the SIT (static induction transistor) or the gate of a MOS transistor and generated by light is also promising. That is, CCD type, MOS
Whereas the conventional type reads out the accumulated charge itself to the outside, the method proposed here uses the amplification function of each cell to amplify the charge and then reads out the accumulated charge. Also, looking at it from another perspective, it is read out as a low impedance output by impedance conversion. Therefore, the method proposed here has high output, wide dynamic range, and low noise, and since the carriers (electrons m) excited by the optical signal accumulate in the control electrode, non-destructive readout is possible. It has several advantages such as: Sara.

It can be said that this method has the potential for higher resolution in the future.

However, this method is basically an X-Y address method, and the element structure described in the L publication is an amplification element such as a bipolar transistor or a 5IT) transistor in each cell of a conventional MO3 type imaging device. The basic structure is a composite one. Therefore, although it has a relatively complex structure and has the potential for high resolution, there is a limit to high resolution as it is.

An object of the present invention is to provide a new photoelectric conversion device that has an amplification function in each cell but has an extremely compact structure and can sufficiently cope with future increases in resolution.

This purpose is to make the control electrode region of a semiconductor transistor, which consists of two main electrode regions of the same conductivity type and a control electrode region of the opposite conductivity type to the main electrode region, into a floating state! Breathe,
By controlling the potential of the control electrode region in the floating state through a capacitor, an accumulation operation is performed in which carriers generated by light are accumulated in the control electrode region in the floating state. In a photoelectric conversion device having a structure that performs a read operation to read out the generated accumulated voltage and a refresh operation to eliminate carriers accumulated in the control electrode region, a clamp diode controls the potential of the control electrode region in a floating state. This is achieved by a photoelectric conversion device having the following feature:

Hereinafter, the first embodiment will be described in detail with reference to the drawings.

FIG. 1 is a diagram illustrating the basic structure and operation of a photosensor cell that constitutes a photoelectric conversion device according to an embodiment of the present invention.

FIG. 1(a) shows the 1L side view of the optical sensor cell at 0'S1
Figure (b) shows the cross section I of the AA' section in the plan view of Figure 1 (a).
A, and FIG. 1(C) shows its equivalent circuit. In addition, in each part, Fig. 1 (a), (b),
(c) No.1: The same numbers are given to those that are sent.

In Figure 1, a plan view of the alignment arrangement method is shown.
Of course, in order to increase the directional resolution, it is also possible to arrange using a pixel shifting method (interpolation arrangement method).

This optical sensor cell is as shown in ff11 figures (a) and (b).

Phosphorus (P), antimony (sb), arsenic (A*)
A passivation layer 11 usually made of a PSG film or the like is formed on a silicon substrate 1 which is doped with impurities such as n-type or n+ type; and an insulating oxide film 3 made of a silicon oxide film (Si02). An element isolation region 4 made of an insulating film made of SiO or SjlNa, or a polysilicon film, etc. for electrically insulating between it and the photosensor cell;
-region 5; The p region 6, which is the base of a bipolar transistor doped with an impurity such as poron (B) using an impurity diffusion technique or an ion implantation technique; n+ region 7, which becomes the emitter of the bipolar transistor:
I), ^l-9i, AIJ: Arrangement i8° formed of a conductive material such as u-9i Electric Ij9: its wiring for applying a pulse to the p region 6 in a floating state through the insulating film 3 10: (N+ region l with high impurity concentration formed by impurity diffusion technology etc. in order to make ohmic contact with the back surface of the plate l; aluminum to give the potential of the substrate, that is, the collector potential of the bipolar transistor) It consists of a 1tt pole and 12° made of a conductive material such as.

Note that 19 in FIG. 1(a) is a contact portion for connecting the n+ region 7 and the wiring 8. Further, the alternating portions of the wirings 8 and 10 are so-called two-layer wirings, and are insulated from each other by insulating regions formed of an insulating material such as SiO. That is, it has a two-layer metal wiring structure.

fI%1 Capacitor Co of the equivalent circuit in Figure (C)! 13 is the electrode 9. It is composed of an MO3 structure with an insulating film 3 and a p-region 6, and a bipolar transistor 14 has an n-type emitter.
1 area7. p region 6 as a base, n- region 5 with low impurity greed. It is composed of each part of the n or n+ region as a collector. As is clear from these drawings, p region 6 is made into a floating region.

The second equivalent circuit in FIG. 1(C) consists of a bipolar transistor 14, a base-emitter junction capacitor Cbe15, a base-emitter pn junction diode Dbe16. This is expressed using a base-collector junction JiCbc17 and a base-collector pn junction diode DbclB.

The basic operation of the optical sensor cell will be explained below with reference to FIG.

The basic operation of this photosensor cell consists of a charge accumulation operation by light incidence, a read operation, and a refresh operation. In the charge storage operation, for example, the collectors are grounded through the wire 8, and the collector is biased to a positive potential through the wire 12. Also, the base is pre-condenser Co! It is assumed that the emitter 7 is sealed to a negative potential by applying a positive pulse voltage to the emitter 13 through the wiring 10, thereby making it in a reverse bias state. The operation of applying a pulse to Cox 13 to lower the base 6 to a negative potential will be explained in detail later when the refresh operation is explained.

In this state, when light 20 enters from the front side of the photosensor cell as shown in FIG. 1, electron-hole pairs are generated within the semiconductor.

Among these electrons, the electrons flow to the n region 1 because the n region l is biased to a positive potential, but the holes accumulate in the p region 6 more and more. Due to the accumulation, the potential of p region 6 gradually changes toward a positive potential.

In FIGS. 1(a) and 1(b), the lower surface of the light-receiving surface of each sensor cell is mostly occupied by the p-region, and is partially occupied by the n+ region. As a matter of course, the concentration of electron-hole pairs excited by light increases the closer to the surface, and therefore many electron-hole pairs are excited in the p-region 6 as well. Electrons photoexcited in the p region immediately flow out of the p region 6 without recombining,
If the structure is such that it is absorbed in the n region, the p region 6
Holes excited in the pTr region 6 are accumulated as they are and
changes towards positive potential. When the impurity concentration in the P region 6 is made uniform, electrons excited by light diffuse to the pn-junction between the P region 6 and the n-region 5, and then join the n-region. It is absorbed by the n collector region l due to the drift caused by the strong electric field. Of course, electrons may travel within the P region 6 by diffusion alone, but if the structure is configured so that the P-based impurity concentration decreases from the surface to the inside, this impurity concentration can be reduced. The difference generates an electric field Ed, in the base from the inside toward the surface. Here, W is the depth from the light incident surface of the p region 6, k is the Boltzmann constant, T is the absolute temperature, q is the unit charge, PJAs is the surface impurity concentration of the p base region 6, and N Ai is the This is the impurity concentration at the interface of the p9n castle 6 with the n- high resistance region 5.

Here, if N As / N At > 3, then p
The movement of 'F; and f- in @ area 6 is carried out by drift rather than diffusion. That is, in order to effectively operate the carriers excited by light in the P region 6 as a signal, the impurity concentration of the P region 6 must decrease from the light incident surface toward the inside. If the p region 6 is formed by diffusion, the impurity concentration decreases toward the inside compared to the surface on the light incident side.

A part of the light-receiving surface of the sensor cell is occupied by the n+ region 7. The depth of the n" region 7 is usually designed to be about 0.2 to 0.3 mm or less, so the amount of light absorbed by the n" region 7 is not that large to begin with. No problem.

However, for light on the short wavelength side, especially blue light, the presence of the n4 region 7- causes a decrease in sensitivity.The impurity concentration of the an" region 7 is usually around I x 10"cm-' or more. Designed. The diffusion distance of holes in the n1 region 7 doped with impurities at such a high concentration is 0.15
It is approximately 0.2 JLII. Therefore, n +<
In order to effectively flow the holes optically excited in the TI region 7 into the p region 6, it is desirable that the n+ region 7 also have a structure in which the impurity concentration decreases from the light incident surface toward the inside. If the impurity concentration distribution in the n+ region 7 is as described above, a strong drift electric field will be generated from the light incident surface toward the inside, and the holes optically excited in the n+ region 7 will immediately flow into the p region 6 due to the drift. n+ region7. If the impurity concentration of the p-region 6 is configured such that it decreases from the light-incidence side surface toward the inside, the n4'' region 7 and the p-region 6 existing on the light-incidence side surface of the sensor cell will be optically excited. All of the carriers function effectively as optical signals.^ If this n+ region 7 is formed by impurity diffusion from a silicon oxide film or a polysilicon film heavily doped with S or P, the desired effect as described above can be achieved. It is very easy to obtain an n+ region with an impurity gradient.

Eventually, due to the accumulation of holes, the ζ rebase potential changes to the emitter potential, in this case to the ground potential,
It will be clipped there.

If the condition is set more strictly, the base-emitter region will be biased deeply in the forward direction, and the holes accumulated in the base will be clipped at a voltage at which they begin to flow to the emitter. In other words, the saturation potential of the photosensor cell in this case is close to the bias potential when the p region 6 is initially biased to a negative potential JI! ! When n+ region 7 is not grounded and accumulates charges generated by optical input in a floating state, p region 6 has approximately the same potential as n region l. Charges can be multiplied up to #.

The following is a qualitative summary of the charge storage operation, but a more specific and quantitative explanation will be given below.

The spectral sensitivity distribution of the sensor cell is given by the following equation.

λ S (input) = □・exp(-αX) 1.24 Light attenuation coefficient [IL■-1], x is I') on the semiconductor surface; Does not contribute to sensitivity”
Dead 1ayer” thickness [gm
l, y are the thickness of the shrimp layer [pLm], and T is the transmittance.

The ratio of the light 4L that effectively enters the conductor to the incident light r4 is set to be less than 1, taking into account reflection and the like. The photocurrent Ip is then calculated using the following formula using the spectral sensitivity IJ\S (on) and the irradiance Ee (on) of the sensor cell.

! p= f'' S (in)・Ee (in) - d in [le A/c
m'] Erotic irradiance E'e (in), [gW 'l cll
-211nfil-' ] is given by the following equation.

[ILW * am-2@nm-' ] However, Ema is the illuminance of the sensor's light-receiving surface [shi■], P (on) is the spectral distribution of the light incident on the sensor's light-receiving surface, and ■ (8) is This is the relative luminous sensitivity of the human eye.

Using these formulas, an optical sensor cell with a layer 4 #LIl of shrimp thickness is irradiated with A light & 1f (2854°K), and the sensor light receiving surface illuminance is l [Luxl, approximately 28
A photocurrent of 0 n^/cm 2 flows, and the number of incident photons or the number of generated electron-active hole pairs is about 1.8 XIO 2/cm 2 a see.

Also, at this time, the potential Vp generated by the accumulation of holes excited by light in the base is given by Vp = Q/C, #Q is the amount of charge of the accumulated holes, and C is C
This is the junction capacitance that is the sum of bel,5 and Cbel7.

Now, the impurity concentration of n+ region 7 is 102fic-3,
The impurity concentration of p region 6 is 5 x 1,0"Cm-'
, the impurity of n- region 5 is 10 cta'', the area of n+ region 7 is 16 pm2, the area of p region 6 is 1114 g
When the thickness of the m', n- region 5 is 3 gm+, the junction capacitance is about 0.014 pF, and the number of holes accumulated in the p region 6 is determined by the accumulation time 1/1 lQsec.
, from the effective light-receiving area, that is, the area of the p region 6, the electrode 8
If the area obtained by subtracting the areas of Therefore, the potential Vp generated by light incidence is about 190 mV.

Note 1-1 here: When the resolution is increased and the cell sensor/fs is downsized, the light that will be incident on the photo sensor cell! - decreases, and the accumulated charge Q decreases as well, but as the cell becomes smaller, the junction capacitance also decreases in proportion to the cell size, so the potential Vp generated by light incidence decreases. This means that you can lean almost constantly. This is because the optical sensor cell according to the present invention has an extremely simple structure as shown in FIG. 1, and has a ril ability that allows an extremely large effective light-receiving surface.

This is one of the reasons why the photoelectric conversion device of the present invention is advantageous compared to interline type COD.
In a D-type imaging device, in order to secure the amount of charge to be transferred, the area of the transfer section becomes relatively large, which reduces the effective light-receiving surface, resulting in a decrease in sensitivity, that is, the voltage generated by incident light. become. In addition, in an imaging device using an interline type CCD, the saturation voltage is limited by the size of the transfer section and gradually decreases, whereas in the optical sensor cell of the present invention, as mentioned earlier, The saturation voltage is determined by the bias voltage when the p-region 6 is initially biased to a negative potential, and a large saturation voltage can be ensured.

The operation of reading out the voltage generated by the charges accumulated in p region 6 as described above to the outside will be described next.

In the read operation state, the emifter and wiring 8 are in a floating state,
The collector is held at a positive potential Vcc.

The equivalent circuit is shown in Figure 2. Before irradiating light, the potential when the base 6 is biased to a negative potential is -V@.
If the accumulated voltage generated by light irradiation is Vp, the base potential is -v, +Vp. In this state, when a positive voltage V for reading is applied to the electrode 9 through the wiring lO, the 'potential vI+ of this IE changes to the oxide film capacity JiC
The capacitance is divided by ox13, the base-eminter junction capacitance 1cbe15, and the base-collector junction capacitance Cbc7, and a voltage is added to the base. Therefore, the base potential becomes 0X -V+Vp1□·v,l CO1+ Cbe+ Cbe. Here, −v, + −shi and 111 −* v = .

When conditions such as Cox+ Cbe+ Cbc were established, a base potential was generated by light irradiation. ¥: Becomes the product voltage Vp itself. In this way, the base potential is I with respect to the emitter potential.
When biased in the E direction, electrons are injected from the emitter to the base, and since the collector potential is positive, they are accelerated by the drift electric field and reach the collector. The current flowing at this time is a linear equation! j - can be obtained.

x (exp - Miko T (vp -■e) -11
Here, Aj is the junction area between the base and emitter, q is the unit charge It (1,8x 1g-+q coulombs), and Dn is the electron diffusion constant in the base, n. is the electron concentration as minority carriers at the emitter end of the p base, WI is the base width, NA2 is the acceptor concentration at the Emink end of the base, NAC is the acceptor sensitivity at the collector end of the base, k is the Portzmann constant, and T
is the absolute temperature and Ve is the emitter potential.

It is clear from the above equation that this current flows until the emitter potential Ve becomes equal to the base potential, that is, the accumulated voltage Vp generated by light irradiation here. At this time, the temporal change in the emitter potential Ve is calculated by 111 using the following equation.

However, here, the wiring length Cs is the capacitance 21 of the wiring 8 connected to the emitter and the terminal.

FIG. 3 shows an example of a temporal change in the eminter potential calculated using Set 1.

According to FIG. 3, it takes about 1 second for the emitter potential to become equal to the base potential. This is because when the emitter potential Ve approaches Vp, less current flows. Therefore, in the L stage that solves this problem, when applying the positive voltage ρ to the electrode 9, we set the following condition, but by inserting a condition to replace this condition, the base potential is changed by v[1Ias, One possible method is to apply an extra forward bias.

The current flowing at this time is given by the following formula! j - can be obtained.

X (exp −(Vp + VIltas −V e
) -11T In Fig. 4(a), when V e+ as = 0.8 V, after a certain period of time, the Vl! applied to IUJ4i9! The relationship between the read voltage, that is, the emitter potential, and the accumulated voltage Vp is shown when the voltage is returned to zero volts and the flowing current is stopped. However, in Figure 4(a),
As for the read voltage, a constant potential depending on the read time due to the bias voltage component is always added, but the value A4 obtained by subtracting the gain is plotted. When the voltage vlI applied to the electrode 9 is returned to zero volts, a voltage opposite to that when applied is added to the base potential, so the base voltage is 11: the state before voltage VII is applied. , that is, = V8, and the emitter is reverse biased, so the current flow stops. Figure 4 (a
), if the readout time is about +00ns or more (that is, the time during which ■R is applied to the electrode 9), the linearity of the storage voltage Vp and the readout voltage is ensured over a range of about 4 digits, and high-speed readout is possible. This shows that = r ability. In FIG. 4(a), the line 456 is the result when 1 minute is taken for reading, and the line is the result when sufficient time is taken for reading, and in the calculation example in L, The capacitance Cs of wiring 8 is set to 4pF, which is Cbe+Cbc.
Although it is approximately 300 times larger than the junction capacitance of 0.014 pF, the accumulated voltage V generated in the p region 6
Figure 4 shows that p is not subject to any M attenuation and can be read out at extremely high speed due to the effect of bias pressure.
a) shows. This is because the amplification function of the photosensor cell according to the configuration described in -1-, that is, the charge amplification R function is working effectively.

On the other hand, in the conventional MO5 type imaging device, the accumulated voltage V
p is the wiring capacitance Qj Cs in such a read process
Due to the influence of Cj.Vp/(Cj +Cs) (zero, Cj is the pn junction capacitance of the optical part of the MO3O3 type image pickup device), which has the drawback of lowering the readout voltage I1 by about two orders of magnitude. For this reason, in the MO5 type imaging device, the fixed pattern n mark due to variations in the parasitic capacity of the main rung MO3) transistor for reading out to the outside, or the rung J, Gl [sound] caused by the large wiring capacitance, that is, the output customer base. There was a large I/% and l,% 13+8 with poor S/N ratio, but Fig. 1 (a) and (b)
, (C), the accumulated voltage generated in the p region 6 is read out to the outside, and since this voltage ε) is considerably larger than the fixed pattern a*1.
Random noise caused by f, r'' force capacity becomes relatively small, making it possible to obtain a signal with an extremely good S/N ratio.
It is Noh.

Previously, when the bias voltage V s+ as was set at 0.8 V, a linearity of about 4 orders of magnitude could be obtained with a high-speed readout time of about 100 nsec. The results of calculating the relationship between Iasumi pressure and Visas are shown in more detail in FIG. 4(b).

In Fig. 4(b), the horizontal axis is /(Iasumi 11: Vua
s, and the vertical axis represents the readout time.

The parameters are: when the stored voltage is 1 V, the read voltage is 80%, 90%, and 95% of 1 mV.

It shows the time dependence until it reaches 98%. Fourth
As shown in Figure (a), when the accumulated voltage l and V are 80%, 90%, 95%, and 98%, respectively, the accumulated voltage is even better. It is clear that he is referring to Haku.

According to this wS4 diagram (b), the bias voltage Visas
When the voltage is 0.8V, the readout time becomes 80% of the accumulated voltage in 0.12μs, 90% in 0.27S, and 95% in 0.541Ls, 9
It can be seen that it takes 1.4 μs to reach 8%. Also,
It is shown that if the bias voltage V it as is made larger than 0.6 V, even faster readout is possible. In this way, once the readout time and required linearity are determined from the overall design of the imaging device, the required bias voltage v@tas can be determined using the graph in FIG. 4(b). can.

Another advantage of the optical sensor cell having the above configuration is that the holes accumulated in the p region 6 can be read out non-destructively since the 1r+ coupling probability of electrons and holes in the p region 6 is extremely small. That is, when the voltage V applied to the electrode 9 during reading is returned to zero volts, the potential of the p region 6 becomes the reverse bias state before applying the voltage V, and the accumulated voltage Vp generated by light irradiation becomes It will remain as it is unless exposed to new light. This means that when the optical sensor cell according to the above configuration is configured as a photoelectric conversion device, system operation
This means that new functionality can be provided.

The time during which the accumulated voltage Vp can be held in this p region 6 is extremely long, and the holding time is rather long.

It is limited by the thermally generated dark current in the junction depletion layer. In other words, this thermally generated dark current saturates the optical sensor cell. However, in the optical sensor cell according to the above configuration, the depletion layer spreads out to the region t±, which is I/, and the region n−, which is the low impurity concentration region.
region 5, and this n-region 5 is 10"am-' ~
Since the impurity concentration is extremely low at about 10"am-", its crystallinity is excellent, and compared to MOS type and CCD type imaging devices, thermally generated electron-hole pairs and I/C are less. ).

For this reason, the dark current is small compared to other conventional devices, that is, the optical sensor cell according to the above configuration has an essentially low dark current noise structure.

Next, the operation of refreshing the charges accumulated in p region 6 will be explained.

In the optical sensor cell according to the L configuration, as already mentioned, the charge accumulated in the p region 6 does not disappear in the readout operation. Therefore, in order to manually input new optical information, +
A refresh operation is required to eliminate the charge accumulated in iij. At the same time, it is necessary to charge the potential of the p region 6 which is in a floating state to a predetermined negative voltage.

In the optical sensor cell having the above configuration, the refresh operation is also performed by applying a positive voltage to the electrode 9 through the wiring 10, similarly to the reading operation. At this time, the emitter is grounded through the wiring 8. The collector is grounded or set to an IF potential through the electrode 12. FIG. 5 shows an equivalent circuit for a refresh operation, with the collector side being grounded.

When a positive voltage V4 is applied to the electrode 9 in this state, the base 22 has an oxide film capacitor 1icox13 and a base
By dividing the capacitances of the emitter junction 8cbe15 and the base-flefter junction capacitance Cbc17, a voltage of 0 is instantaneously applied as in the previous read operation. This voltage causes the base-to-emitter junction diode Dbe16 and the base-to-collector junction diode to
)" DbclB is forward biased and becomes conductive, current begins to flow, and the base potential gradually decreases.

At this time, the change in the potential V of the base in a floating state is approximately expressed by the following equation.

However, X(e(-V) -1) T qDIlnp* +2 = Ae I It is an electric current. A- is the base area, Ae
is the emitter area, op is the hole diffusion constant in the collector, D-Pne is the hole concentration at thermal equilibrium in the collector, t, p are the mean free path of holes in the collector, I2. is the electron concentration at thermal-1i equilibrium IE in the base. In i, the current due to hole injection from the base side to the emitter can be ignored because the impurity concentration of the emitter is sufficiently higher than that of the base.

The equation shown in 1- is an approximation of a one-step junction, which deviates from the step-junction in actual devices, and the base is thin and has a complex concentration distribution, so it is not a strict one. However, the refresh operation can be explained with a fair approximation.

Of the current 11 flowing between the base and collector in the above formula,
q・DP・P II@/LP indicates a current due to holes, that is, a component where holes flow from the base to the collector side. In order to facilitate the flow of current due to these holes, in the optical sensor cell having the above configuration, the impurity concentration of the collector is designed to be a little lower than that of a normal bipolar transistor.

An example of the time dependence of the base height calculated using this formula is shown in FIG. The horizontal axis represents the elapse of time from the moment when the refresh 1 was applied to the electrode 9, that is, the refresh time, and the vertical axis represents the base potential, and the initial potential of the base is used as a parameter. The initial potential of the base is the potential exhibited by the base in the floating state m at the moment refresh voltage VIIH is applied, and VT
IH.

CO! , Cbe, Cbc and the charge stored in the base.

Looking at this FIG. 6, the potential of the base always falls along the -· straight line on the semi-logarithmic graph after a certain period of time, regardless of the initial potential.

Figure 6(b) shows experimental values of base potential change with respect to refresh time.Compared to the calculation example shown in Figure 6(a), the test device used in this experiment has considerably larger dimensions. 1. Although the absolute value does not match the calculation example, the base voltage (h
It is true that the change is linear on a semi-logarithmic graph. This experimental example shows values when both the collector and emitter are grounded.

Now, the maximum value of the accumulated voltage Vp due to light irradiation is 0.4 [V]
, the voltage applied to the base by the refresh voltage V gH is 0.4 [V], the maximum value of the initial base potential is 0.8 [V] as shown in Fig. 6, and the maximum value of the initial base potential is 0.8 [V]. After [sec], the base potential starts to drop in a straight line, and becomes 10-'[5ecl
After that, the potential change coincides with that when no light was applied, that is, when the initial base potential was 0.4 [V].

There are two ways in which the p region 6 can be charged to a negative potential by applying the iE voltage for a certain period of time through the MOS capacitor Cot and removing the positive voltage. One is an operation in which holes with positive charges flow from the p region 6 to the n region l, which is mainly in a grounded state, thereby accumulating negative charges.

In order to prevent holes from flowing unilaterally from p-region 6 to n-region l and to prevent electrons from n-region l from flowing too much into p-region 6, the impurity density of p-region 6 must be set to the impurity density of n-region l. It should be higher. On the other hand, n + area 7 and n
Electrons from the region 1 flow into the p region 6 and recombine with holes, so that negative charges Ma can be added to the p region 6. In this case, the impurity density of n region l is higher than that of p region 6. The operation in which negative charges are accumulated due to the outflow of holes from the p region 6 is more
This is much faster than the operation in which negative charges are accumulated by electrons flowing into the p-region 6 and recombining with holes, but according to previous experiments, even the refresh operation in which electrons flow into the p-region 6 does not result in photoelectric conversion. For the operation of the device.

It has been confirmed that the time response is sufficiently fast.

When a large number of optical sensor cells according to the above configuration are arranged in the x and Y directions to construct a light 1 [conversion device, the accumulated voltage Vp in each sensor cell is determined to be θ~0.4 [in the above example] according to the image.
V], but the refresh voltage VR
Although a constant voltage of about 0.3 [V] remains at the base of all sensor cells 'O-'' [sec] after H is applied, the change in the accumulated voltage Vp caused by the image may completely disappear. That is, in the photoelectric conversion device using optical sensor cells according to the above configuration, there is a complete refresh mode in which the base potential of all sensor cells is brought to zero volts by a refresh operation (in this case, as shown in FIG. 6(a)).
In the example, there are lo [5 ecl required) and -5 transient refresh modes in which a certain constant voltage remains at the base potential but the fluctuation component due to the accumulated voltage Vp disappears (in this case, the 6th IM ( In example a), 1
0 [refresh pulse of μ5ecJ to 10EsecJ), in the following example 1-, the refresh voltage V 111
The voltage V applied to the base by + is set to 0.4 [V], but if this voltage ■^ is set to 0.13 [V], then ■-
According to FIG. 6, the transient refresh mode is
[Occurs in n5ecl and can be refreshed very quickly. The choice between operating in complete refresh mode or transient refresh mode is photoelectric conversion! :! Determined by the intended use of the device.

If the voltage remaining at the base in this transient refresh mode is vK, after applying the refresh voltage V□, V
In the momentary transient state of returning the pH to zero volts.

Since a negative voltage is added to the base, the base potential 5 after the refresh operation by the refresh pulse becomes OX V, -□·V□ CO+Cbe+Cbe, and the base becomes reverse biased with respect to the emitter.

Earlier, it was explained that during the accumulation operation of accumulating carriers excited by light, the base is in a reverse bias state in the accumulation state, but this refresh operation puts the charge and the base in a reverse bias state. The two actions of bringing it to the surface are performed at the same time.

FIG. 6(C) shows the base potential yK--Colt, v*u CO! after the refresh operation with respect to the refresh voltage vIII+. The value of Cow is set from 5 pF to 100 pF as a parameter indicating the experimental value of the change in +Cbe+Cbc. The circles are experimental values, and the solid lines are calculated values calculated from Cow VK-□・VRH Cox+Cbe+Cbe. At this time VK
= 0.52V Te, and Cbc+ Cbe=
It is 4pF. However, the probe capacitor φ13 pF of the observation oscilloscope is connected in parallel to Cbc+Cbe.

In this way, the calculation A1 and the experimental values are in complete agreement, and the refresh operation has been experimentally confirmed.

In the refresh operation described in I- below, an example has been described in which the collector is grounded as shown in FIG. 5, but it is also possible to perform the refresh operation with the collector at surface potential. At this time, even if a refresh pulse is applied to the base-collector junction diode Dbc18,
If the ilE potential applied to the collector is greater than the voltage level applied to the base by this refresh pulse, it remains non-conductive, so current can flow only through the base-emitter junction diode Dbe16.

Therefore, the base potential decreases more slowly, but basically the operation is completely the same as that described above.

In other words, the relationship between the base potential and the refresh time in FIG. 6(a) is such that the diagonal straight line when the base potential decreases in FIG. 6(a) shifts to the right, that is, in the direction that requires more time. Become.

Therefore, if you use the same refresh voltage VRH as when the collector is grounded, it will take time to refresh, but if you slightly increase the refresh voltage 7 songs, you can achieve the same high-speed refresh operation as when the collector is grounded. f ability.

The following is an explanation of the basic operation of the photosensor cell according to the above configuration, which includes a charge accumulation operation, a readout operation, and a refresh operation by light incidence.

As explained in 1-1 below, the basic structure of the sensor cell according to the configuration in Section 16 is disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 56-150878.
, JP-A-50-157073, JP-A-56-IE1
Compared to 5473, it has an extremely simple structure and can fully support future higher resolutions, and its excellent features include low noise RF, high output, wide dynamic range, and non-destructive power from the amplifier. The advantages of reading etc. are preserved as they are.

Next, an embodiment of a photoelectric conversion device of the present invention, which is constructed by two-dimensionally arranging optical sensor cells according to the configuration described below, will be described with reference to the drawings.

FIG. 7 shows a circuit MFj diagram of a photoelectric conversion device in which optical sensor cell structures are arranged in a 3×3 dimension.

The basic optical sensor cell 30 surrounded by the dotted line already explained
(At this time, the collector of the Ibora transistor is shown to be connected to the substrate and the substrate electrode.) Water for applying read pulses and refresh pulses
+1 line 31° 31', 31'', vertical shift register 32 for generating readout pulses, to l between superimposed shift register 32 and horizontal lines 31.31', 31'', F MO3) lano register 33.33 '.

33”, /Heffer MO3) transistor 33°3
Terminal 3 for applying pulses to gates 3' and 33''
4. Buffer γMO for applying refresh pulses
5) Transistor 35. 35', 35'', terminal 36 for applying a pulse to its gate, terminal 37 for applying a refresh pulse. Basic photosensor cell 30
Vertical lines 38, 38' for reading out the accumulated voltage from
, 38'', Water 41 Shift register 39 which generates pulses to select each take line. Game) 1t1MO3) Run sister 40°40 to open and close each vertical line.
', 40'', storage 1n'n1JEtc7 yp part 2 output line 41 for reading, MOS transistor 42 for refreshing the charge accumulated in the output line after reading, MOS) range meta 42 Heli frequency pulse is applied. Terminal 43 for amplifying the output signal, transistor 44 such as MOS, FET, J-FET, etc. for amplifying the output signal.Load resistor 45, terminal f-46 for connecting the transistor and power supply, output terminal 47 of the transistor. , forward line 40.40' in a read operation,
MO for refreshing the charge accumulated in 40”
S) Runcissta48. j8′, 48″, and MOS
This photoelectric conversion device is constituted by a terminal 49 for applying a pulse to the gates of transistors 48, 48', 48''.

The operation of this photoelectric conversion device will be explained using pulse timing diagrams shown in FIGS. 7 and 8.

In the diagram t58, one section 61 corresponds to a refresh operation, one section 62 corresponds to an 11M operation, and one section 63 corresponds to a read operation.

At time t1, the substrate potential, that is, the collector potential 64 of the photosensor cell portion is still kept at a positive potential, but FIG. 8 shows that it is kept at the ground potential. Regardless of whether it is a ground potential or a positive potential, as already explained, the time required for refreshing differs, and there is no change in the basic operation.
5 is in the high state, Mo3) transistor 48°4
8', 48'' are kept conductive, and each photosensor cell is
It is grounded through the vertical lines 38, 38', 38''.
3) A voltage is applied that makes the transistor conductive, and the refresh buffer MO3) transistor 35 is applied to refresh the entire screen at once.
．． 35' and 35'' are in a conductive state. When a pulse as shown in waveform 67 is applied to the terminal 37 in this state,
A voltage is applied to the base of each photosensor cell through the horizontal lines 31, 31' and 31'', and as explained above, a refresh operation is initiated, and the T that has been accumulated in 1ii since then is
rt, r4 are refreshed according to full refresh mode or transient refresh refresh mode. The pulse width of the waveform 67 determines whether the complete refresh mode or the transient refresh mode is entered.

T! At that time, the base of the transistor of each photosensor cell is reverse biased with respect to the emitter, as previously described, and the next storage interval 62 is entered. In this refresh section Ill 61, as shown in FIG. 1, all other applied pulses are kept in the loe+ state.

In the accumulation operation period 62, the substrate voltage, that is, the collector potential waveform 64 of the transistor is set to rE potential.

This allows electrons of the electron-hole pairs generated by optical separation to quickly flow toward the collector side. However, keeping this collector potential at a positive potential is not an essential condition because the S base is reverse biased with respect to the emitter, that is, images are taken with a negative potential (even if it is kept at ground potential or a slightly negative potential) There is no change in the basic 5lAvJ production.

In the storage operation state, Mo3) transistors 4B, 4
The voltage at the gate terminal 49 of 8', 48'' is kept high, as in the refresh interval, and each MO3) transistor is kept conductive. Therefore, the emitter of each photosensor cell is connected to the vertical line 38.38. When holes are accumulated in the base due to the irradiation of strong light that is grounded through ', 38'', the base potential becomes forward biased with respect to the emitter potential (ground potential). All around, the hole is a vertical line of 38.38″,
38'', where the base potential change stops and is clipped.

Therefore, even if the emitters of vertically adjacent photosensor cells are commonly connected by the vertical lines 38.38', 3B'', the vertical lines 38.38', 3B''
If 8'' is grounded, no blooming phenomenon will occur.

To avoid this pluming phenomenon, even if the MOS transistors 48, 48', 48'' are in a non-conductive state and the vertical lines 38, 38', 38'' are in a floating state, the substrate potential, that is, the collector potential 64, can be slightly reduced. It is also possible to achieve this by setting the potential to be negative, and when the base potential changes to a positive potential due to accumulation of holes, the potential flows to the collector side before the emitter.

Following the accumulation section 62, a readout section 63 begins at time t. At this time t3, Mo3) transistor 48
．． 48', 48'' gate end f・49 potential 65 is lo
w, water repellent f line 31.31', 31" bar/
77-Mo S) 57 Jister 33, 33', 33
The potential 68 of the gate terminal 34 is set high, and each Mo3) transistor is made conductive. However, the timing at which the potential 68 of the gate terminal 34 is set high is as follows.
It is not an essential condition that it is time t3, but any earlier time is sufficient.

At time t4, among the outputs of the vertical shift register 32, those connected to the horizontal line 31 have a waveform 69 (
At this time, the 1M03) transistor 33 is in a conductive state, so each of the three photosensor cells connected to this horizontal line 31 is read out. This readout operation is as already explained earlier, and is generated by the signal charges accumulated in the base region of each photosensor cell.
The voltage is the same as the vertical line 38.38'.

38". Vertical shift register 3 at this time
As shown in FIG. 4, the pulse width of the pulse voltage from 2 is set to a pulse width that maintains linearity between the read voltage and the accumulated voltage. Further, as explained earlier, the pulse voltage is adjusted so that a forward bias is applied to the emitter by v@tas.

Then, at time t, the water qt shift register 39
Among the outputs of , only the output to the gate of the MOS transistor 40 connected to the vertical line 38 is as shown in the waveform 70 (
becomes high, the MOS transistor 40 becomes conductive, and the output signal enters the output transistor 44 through the output line 41.

The current is amplified and output from the output terminal 47. After the signal is read out in this way, signal charge due to the wiring remains in the output line 41, so in II Mt, a pulse is generated at the gate terminal 43 of the MOS transistor 42 as shown in the pulse waveform 71. is applied to turn on the IMOS transistor 42 and ground the output line 41.
This residual signal charge is refreshed. Thereafter, in the same manner, the switching MO3L transistors 40', 40'' are sequentially made conductive, and the vertical lines 3B', 3
Read out the signal output of 8", lined up horizontally like this -
After reading the signals from each optical sensor cell for the line, @
Correct in 38.38'.

38'', similar to the output line 41, there remains signal charge due to its wiring capacity, so each vertical line 3
8. MOS) transistor 4 connected to 38', 38"
8.48', 48. ” is made high and conductive at its gate terminal 49 as shown by the waveform 65, and this residual signal ``charge is refreshed.Next, at 1 time t, among the outputs of the 1T! direct shift register 32, the horizontal The output connected to line 31' becomes high as shown in waveform 69', and water 4L line 3
The accumulated voltage of each photosensor cell connected to W1' is read out to each vertical line 38, 38', 38''.Hereafter, a signal is read out from the output terminal 47 by the same operation as before W1'. be done.

In the following explanation, the storage section 62 and the readout section 63 are
We have explained the operating conditions applied to application field 1, for example, still video, which is actively being researched and developed in New Zealand. Even in the field of application where the operations in 63 are performed at the same time, application 1 can be made by changing the pulse timing shown in FIG. However, the refresh at this time is not a one-time refresh of the entire screen, but requires a line-by-line refresh function.For example, after the signals of each photosensor cell connected to the horizontal line 31 are read out, each vertical MOS transistors 48 and 48' to remove the charge remaining on the line.

48'' is made conductive, and at this time a refresh pulse is applied to the horizontal line 31. That is, in the waveform 69, at time 1., pulses with different pulse voltages and pulse widths are generated as at time t4. This can be achieved by using a vertical shift register with the same configuration as the one on the left. It is also possible to achieve this by providing a second vertical shift register on the right side and operating it with a timing shift from that of the vertical register provided on the left side.

In this case, in the accumulation state as described above, the degree of freedom in controlling blooming by controlling the potentials of the emitter and collector of each photosensor cell is reduced. However, as explained in the basic operation,
In the read state, the configuration is such that high-speed reading is possible only when a bias voltage called Vitas is applied to the base, so as can be seen from the graph in Figure 3, vIl
When taS is not applied, due to the saturation of each photosensor cell, the signal type load flowing into the vertical lines 28, 28', 28'' is extremely small, and the blooming phenomenon occurs.

No problem at all.

Moreover, the photoelectric conversion device according to this embodiment can obtain extremely excellent characteristics with respect to the smear phenomenon. Smear phenomenon is an operational and structural problem that occurs in CCD type imaging devices, especially frame transfer type, in which charge is transferred to the area irradiated with light. This problem occurs because carriers generated deep in the semiconductor due to the light are accumulated in the charge transfer section.

Furthermore, in the MO3 type imaging device, this problem arises because carriers generated deep in the semiconductor due to long wavelength light are accumulated on the drain side of the switching MO3) transistor grounded to each photosensor cell.

In contrast, in the photoelectric conversion device according to the non-example, there is no smear phenomenon that occurs at all, and there is no phenomenon in which carriers generated deep in the semiconductor are accumulated due to long wavelength light. However, there is a concern that electrons are accumulated among the electrons and holes generated relatively near the surface of the emitter of the optical sensor cell. Since it is grounded, electrons are not accumulated and smear phenomenon does not occur. Also, during line refresh operation, which is applied in normal TV cameras, the accumulated voltage is read out on the vertical line during the horizontal blanking period. Since the vertical line is grounded and refreshed beforehand, the electrons accumulated in the emitter during one horizontal scanning period flow out at the same time, so that almost no smear phenomenon occurs. In such a photoelectric conversion device, the smear phenomenon occurs only to a negligible extent due to its structure and operation, which is one of the major advantages of the photoelectric conversion device according to this embodiment.

In addition, as previously described, in the storage operation state, the emitter and collector potentials are manipulated to suppress the blooming phenomenon.

It is also possible to control the γ characteristics using this.

In other words, during the accumulation operation, the potential of the emitter or collector is temporarily set to a certain negative potential, and of the carriers accumulated in the base, holes that are accumulated in a greater number than the number of carriers that give this negative potential are transferred to the emitter. Alternatively, the data may be flowed to the collector side. As a result, the relationship between the accumulated voltage and the incident light value shows the characteristic of γ=1 of silicon crystal when the amount of incident light is small, and shows the characteristic that γ becomes smaller than 1 when the amount of incident light is large. In other words, it is possible to provide the characteristic of γ=0.45, which is normally required for television cameras, using a polygonal line approximation. If the operation 1- is performed once in the middle of the storage operation, it becomes a one-fold line approximation, and if the negative potential applied to the emitter or collector is changed twice as appropriate, it is also possible to have a two-fold line type γ characteristic. In the embodiments described above, the silicon substrate is used as a common collector, but a buried n+ region may be provided like a normal bipolar transistor, and the collector may be divided for each line.

Note that, in addition to the pulse timing shown in FIG. 8, clock pulses for driving the vertical shift register 32 and the water IL shift register 39 are required for actual operation.

FIG. 9 shows an equivalent circuit related to the output signal.

Capacitor Cma 80 is vertical line 38.38'.

The wiring capacitance is 38", and the capacitance "cHat" indicates the wiring capacitance of the output line 41, respectively. The equivalent circuit on the right side of Figure 019 is in the read state, and the switching MOS transistors 40, 40', 40''
is a continuity letter! It is an island, and its resistance value in a conductive state is shown by resistor RM82. Also, the amplification transistor 4
4 is shown as an equivalent circuit using a resistor r183 and a current source 84. MOS) transistor 42 for refreshing charge accumulation caused by wiring capacitance of the output line 41
is in a non-conducting state in the read state and has high impedance, so it is omitted in the equivalent circuit on the right side.

Each parameter of the equivalent circuit is determined by the size of the photoelectric conversion device actually constructed. For example, the capacitance C 80 is about 4 pF, and the capacitance C 81 is about 4 pF.
(MOS) transistor continuity! FIG. 10 shows an example of calculating the output signal waveform observed at the output terminal 47, assuming that the resistor RM82 of E is about 3Ω, and the radio wave amplification factor β of the bipolar transistor 44 is about 100.

In Fig. 1O, the horizontal axis represents the time from the moment when the swing-lung MOS transistors 40, 40', 40'' become conductive.
gsl, the vertical axis is a vertical line 38° 38', 38'' wiring capacitance Cma 80, output terminal 4 when a signal charge is read out from each photosensor cell and a voltage of 1 volt is applied.
The output voltage [V] appearing at 7 is shown, respectively.

The output signal waveform 85 shows that the load resistance R645 is IOKΩ, 86
is load resistance Rε45 is 5Ω, 87 is load resistance R□45
The peak value in both cases is about 0.5 V due to the capacitance division between Cn 80 and Cn 81. Naturally, the load resistance Rε45
The larger the value, the smaller the attenuation field, resulting in a desirable output waveform.

) γ rise time is approximately 20 when the parameter values are
It is fast as n5ec. Sui Nlang MO5) By reducing the resistance RM in the conducting state of the lano resistors 40, 40' and 40'', and the wiring capacitance tCv
, CH can be made smaller, even faster reading is possible.

- In the photoelectric conversion device using the photosensor cells according to the configuration described above, the voltage appearing at the output is large due to the amplification function of each photosensor cell, so the final stage amplification amplifier is also MOS
It can be a fairly simple device compared to a type imaging device. Although the example described above uses a single-stage bipolar transistor type, it is of course possible to use other systems, such as a two-stage configuration. When bipolar transistors are used as in this example, the problem of I/F noise that is easily noticeable in the image 1 and generated from the MOS transistor of the final stage amplifier in a CCD imaging device can be solved.
This does not occur in the photoelectric conversion device of this example, and the S/M
Uf ability is to obtain a good image quality.

As mentioned in Section H, in the charging conversion device using the optical sensor cell of the above configuration, the amplification amplifier in the final stage can be extremely simple, so it is preferable to provide only one amplification amplifier in the final stage. Instead of the type shown in the embodiment shown, it is also possible to install a plurality of amplification amplifiers and configure one screen to be divided into a plurality of parts and read out.

Figure tjSl1 shows an example of the divided readout method. 11th
The embodiment shown in the figure is an example in which the horizontal direction is divided into three parts and three final stage amplifiers are installed. The basic operation is almost the same as that described using the embodiment of Section 7r;4 and the timing diagram of FIG. 8, but in the embodiment of this fJSl1 diagram, three equivalent water 1L shift registers 1
01, 102 are provided, and when a starting pulse is input to the terminal 103 for applying these starting pulses, 1 column + 1 . (n
+1) column [1° (2n+1) column (n is an integer, and in this embodiment, the number of horizontal picture elements is 31), the outputs of each sensor cell are read out simultaneously. At the next point in time, the second column, (n+2) column, (2n+
2) The column will be read.

According to this embodiment, when the time to read out the horizontal line of -tree is fixed, the horizontal scanning frequency is lower than that of the system with one final stage amplifier! /3
, the horizontal shift register is easy to use,
In addition, for applications in which the output signal from a photoelectric conversion device is converted into analog-to-digital and signal processing is performed, a high-speed analog-to-digital converter is unnecessary, which is a great advantage of the one-division readout method.

In the embodiment shown in FIG. 11, three equivalent horizontal shift registers are provided, but it is possible to provide the same function with only one horizontal register. An example in this case is shown in FIG.

The embodiment shown in FIG. 12 depicts only the middle part of the water f switching MOS transistor and the final stage amplifier of the embodiment shown in FIG. 11, and the other parts are as follows.
Since it is the same as the embodiment shown in FIG. 11, it is omitted.

In this embodiment, the output from one watert shift register 104 is connected to the gates of the first, (n+1), and (2n+1) column [l switching MO3] run registers, and those lines are simultaneously connected. At the 0th order point in time, the 2nd column F-1, (n+2)th column, (2n+2
) column is read out.

According to this embodiment, although the number of wirings to the gates of each switching MOS transistor increases, only one horizontal shift register is required for operation.

In the examples shown in FIGS. 11 and 12, three output amplifiers are provided, but it goes without saying that this number may be increased depending on the purpose.

In both the embodiments shown in FIGS. 11 and 12, the starting pulses and clock pulses for the water f shift register and vertical shift register are omitted, but these are similar to other refresh pulses.

It is supplied from a clock pulse generator provided in the same chip or from a clock pulse generator provided in another chip.

In this split readout method, when horizontal lines or all screens are refreshed at once, the storage time is slightly different between the n-th and (n+1)-th column photosensor cells, which causes the te current component and signal component to Although it is possible that a slight discontinuity may occur and appear on the top of one image, the amount of this is small and there is no problem in practical use.
Furthermore, even if this exceeds the allowable limit, correcting it using an external circuit will generate a serrated wave, subtracting this from the dark current component, and subtracting this from the signal component. Hf is easily achieved using conventional correction techniques using multiplication and division.

When capturing color images using such a charging conversion device, it is possible to create a stripe filter, mosaic filter, etc. on-chip on top of the photoelectric conversion device, or to attach a separately made color filter to the photoelectric conversion device. It is possible to obtain color signals.

As an example, use R, G, and H stripe competition filters.
When used, it is possible to obtain the R signal, G signal, and B signal from separate final-stage amplifiers in a photoelectric conversion device using the optical sensor cell according to the configuration described in L. An example of this is shown in FIG. 13, which, like FIG. 12, only shows the area around the horizontal register. The rest is the same as Fig. 7 and Fig. 1'1, except that the first column is an R color filter, the second column [l is a G color filter,
It is assumed that color filters are provided in the third column 11, such as a B color filter and an H color filter in the fourth column. As shown in Figure 13, 1 column 0.4 column 1], 7
Each car i in column tJ ([line is output line l
connected to lO, which takes out the R signal, and the second column,
Each vertical line of column 5 tJ, column 8 11--1 is connected to an output line 111, which takes out the G signal, and similarly for column 3.

Each vertical line of the 6th column and 9th column - 11111 is connected to the output line 112 and takes out the B signal, the output line 11
0. Ill and 112 are connected to an on-chip refresh MO5) transistor and a final stage amplifier, for example, an emitter follower type bipolar transistor, and each color signal is output separately.

FIG. 14 shows a diagram for explaining the basic structure and operation of another example of a photosensor cell constituting a photoelectric conversion device according to another example of the present invention, and its equivalent circuit and overall circuit configuration diagram. is shown in FIG. 15(a).

The photosensor cell shown in FIG. 14 is an photosensor cell that can simultaneously perform a read operation and a line refresh using the same horizontal scan pulse. 1st
4, the difference from the configuration already shown in FIG. 1 is that the MOS connected to the horizontal line wiring 10 in FIG.
What used to be the only capacitor electrode 9 was a MOS capacitor on the side of the optical sensor cell adjacent to the human? 1
4i120 is connected, and when viewed from one photosensor cell, it is a double capacitor type, and in the figure, the emitter 7 of the vertically adjacent photosensor cell
, are two-layer wiring (1) 8, and wiring ■1
21 (In Figure 14, the vertical line looks like one tree, but
2 lines are placed through the insulating layer)
f, that is, the emitter 7 is connected to the contact hole 19
The difference is that the emitter is connected to the wiring (1) 8 through the contact hole 1, and the emitter is connected to the wiring (1) 121 through the contact hole l.

This becomes clearer when looking at the equivalent circuit shown in FIG. 15(a). That is, the MOS capacitor 150 connected to the base of the photosensor cell 152 is connected to the horizontal line 31, and the MOS capacitor 151 is connected to the horizontal line 3. Further, in the diagram of the optical sensor cell 152, the MOS capacitors 15 1 of the adjacent optical sensor cells 15 1 are connected to a common horizontal line 3 2 .

The emitter of the photosensor cell 152 is placed on the vertical line 38, the emitter of the photosensor cell 15 is placed on the vertical line 138,
The emitters of the optical sensor cells 15 are each connected to an alternating current W as a line 38.

In the equivalent circuit of FIG. 15(a), other than the basic photosensor cell section described above, the only difference from the imaging device of FIG.
Switching MO5) Switching MOS transistor 148 for refreshing the vertical line 138 in addition to the transistor 48 and selecting the front line 38 Switching MO3) Selecting the vertical line 138 in addition to the transistor 40 for refreshing the vertical line 38 A switching MO3) transistor 140 has been added, and one output amplifier system has been added. The configuration of this output system is such that switching MO3) transistors 48 and 148 are connected to refresh each line, and a switching MOS transistor for scanning the water 11L is used as shown in FIG.
A configuration with only one output amplifier as shown in b) is also possible. Fig. 15(a) in Fig. 151m(b)
Only the vertical line selection and output amplifier system parts are shown.

According to the optical sensor cell shown in FIG. 14 and the embodiment shown in FIG. 15(a), the following operations are possible. That is, when the readout operation of each optical sensor cell connected to the horizontal line 31 is finished and the water f blanking period in the TV operation is in progress, the output pulse from the vertical shift register 32 is output to the water 1L line 3. Then, the optical sensor cell 152 from which reading has been completed is refreshed through the MOS capacitor 151. At this time, the switching MOS transistor 48 is rendered conductive, and the vertical line 38 is grounded.

Also, a MOS capacitor 15 connected to the horizontal line 3
Through the vertical line 1, the output of the optical sensor cell 15
38. At this time, the switching MOS transistor 148 is naturally rendered non-conductive,
This means that the vertical line 138 is in a floating state.

In this way, with one vertical scan pulse, it is possible to simultaneously refresh the photosensor cells that have already finished reading and read out the photosensor cells of the next line using the same pulse. At this time, as already explained, the voltage for refreshing and the voltage for reading differ because a bias voltage is applied during reading due to the necessity of high-speed reading, but this is as shown in FIG. This is achieved by changing the area of the MOS capacitor electrode (J4i9 and MOS capacitor electrode 12017) so that even if the same voltage is applied to each electrode, a different voltage is applied to the base of each photosensor cell.
&I'm pissed.

In other words, the area of the refresh MOS capacitor is
The area is smaller than that of the readout MOS capacitor. As in this example, when refreshing the sensor cells one by one rather than all at once, the collector is constructed of an n-type or nJ, Li plate, as shown in Figure 1(b). However, it may be desirable to separately provide a collector for each 1L water line. When the collector is a substrate, the collectors of all the photosensor cells are a common area, so that a constant bias voltage is applied to the collectors in the storage and light reception/readout states. Of course, as already explained, floating base refresh can be performed between the emitters even with a bias voltage applied to the collector. However, in this case, there is a drawback that at the same time that the pace region is refreshed, a wasteful current flows between the emitter and collector of the cell to which the refresh pulse has been applied, increasing power consumption.

In order to overcome these drawbacks, instead of making the collectors of all the sensor cells a common area, the collectors of the sensor cells lined up in each of the 11 water lines are J (wide), but the collectors of each horizontal line are separated into structure, i.e.
To explain this in relation to the structure shown in FIG. 1, the substrate is made of p-type plastic, and there are n embedded regions in the p-type substrate, which are separated in the same manner for each horizontal line of the collector; Create a digit structure. Separation of adjacent water 11u/in n embedded regions is p9Ir
In order to reduce the collector capacitor buried along the horizontal line, it is possible to have a structure in which the castle is interposed in the UL.
Insulator isolation is better. In FIG. 1, since the collector is constituted by the substrate, all isolation regions surrounding the sensor cell are provided almost to the depth. on the other hand,
In order to warmly separate the collectors for each horizontal line, the separation area in the horizontal line direction is made deeper than the vertical line area by a necessary value.

If the collector is separated for each water f line, if the voltage of the collector of that horizontal line is grounded when reading is finished and the refresh operation starts, the emitter-collector current as described above will not flow, and the consumption will be reduced. Does not result in an increase in power. When refreshing is completed and a charge storage operation based on an optical signal begins, a predetermined bias voltage is applied to the collector region again.

Further, according to the equivalent circuit shown in FIG. 15(a), outputs are output to the output terminals 47 and 147 in q directions for each horizontal line. As already explained, this is the 15th
It is also possible to take out the output from one amplifier by using a configuration as shown in FIG. 2(b).

1. As explained above, according to this embodiment, line refreshing becomes OI function with a relatively simple structure, and it can be applied to ordinary application fields such as television cameras.

Other embodiments of the non-emission 1 include a structure in which the optical sensor cell is provided with a plurality of emitters, or a structure in which one emitter is provided with a plurality of contacts.

- A type that takes out multiple outputs from one optical sensor cell is considered.

This is because each optical sensor cell of the photoelectric conversion device according to the present invention has an amplifier section, so even if multiple wiring ants are connected to each optical sensor cell in order to extract multiple outputs from ~1 optical sensor cell, the optical This is due to the fact that the accumulated voltage Vp generated inside the sensor cell can be read out to each output without being attenuated at all.

In this way, by having a configuration in which multiple outputs can be taken out from each optical sensor cell, many advantages can be added to the photoelectric conversion device formed by arranging a large number of each optical sensor cell in terms of signal processing, noise countermeasures, etc. is possible.

Next, an example of a manufacturing method of the optical tunnel conversion device according to the present invention will be explained. FIG. 16 shows the 11-choice epitaxial formation ff1 (
N, Endo et at, “Novel devi
ce isolation technology
th 5elected epitaxial gro
wth"Tech, Dig, of 1982 I
An example of the manufacturing method using EDM, PP, 241-244) is shown below. On the W side of the n-type S1 substrate 1 with an impurity concentration of about 3 IW, an n4 for contact is formed. Area 1
1 is provided by ^S or P diffusion. In order to prevent auto-doping in the n+ regions, an oxide film and a nitride film are usually provided in Table 101, although not shown.

711 (For the plate l, use one in which the impurity concentration and oxygen concentration are controlled uniformly. In other words, use a crystal wafer with a long and uniform carrier line time of 1 minute per wafer. For example, MCZ A crystal produced by the method is suitable.The substrate 10 has an oxidation level of approximately Igm on the ICI.
19 is formed by sea urchin oxidation. That is, )1
．． Oxidize in an OX atmosphere or (H2+O7) atmosphere. To obtain a good oxide film without causing stacking faults, etc.,
High pressure oxidation at a temperature of about 800°C is suitable.

Second, for example, 31 with a thickness of about 2 to 4 pLs.
0, membrane is subjected to CV D -11' jlI product. (N2
+SiH4+02) scum system, and deposit 5i021 to a desired thickness at a temperature of about 300 to 500°C. Ot
/SiH4 molar ratio is set to about 4 to 40, depending on the temperature. During the photolithography process, only the oxide film in the area between the cells is left, and the oxide film in other areas is as follows: (CF4 + I2) -C2Fg, CH
Remove by reactive ion etching using a gas such as 2F2 (step 1-(a) in Figure 16). For example, if one pixel is provided in 10×10 m2,
The 9102 film is left in the form of a meningle of ILm pinch. 5iO
The width of z Di is selected to be, for example, about 2 μm. After removing the damaged layer and contamination layer on the surface caused by reactive ion etching by Ar/Cl 2 gas-based plasma etching or wet etching, it is deposited in an ultra-high vacuum or in a load-lock format to ensure a sufficient atmosphere. Amorphous silicon 301 is deposited using cleaned sputtering or reduced IE light CVD in which the 5IH4 residue is irradiated with a CO2 laser beam (step (b) in FIG. 16). Anisotropic etching using CBrF, CG12F2, CI2, etc., or active ion etching.

Remove the amorphous silicon other than that deposited on the 5IOz layer (+11) (step (C) in Figure 16).Similar to the song, after sufficiently removing the damage and contamination layer, thoroughly clean the silicon substrate surface. Washed and (I2 SiH,,C
(Text, 10FICKL) Selective growth of the silicon layer is carried out for 1r using a dregs system. Decompression of several tens of Torr! , Growth takes place in town, board 3! The temperature is set at 900 to 1000°C, and the molar ratio of till:i is set to a value that is somewhat higher than that of the nail. 17 of 110 sentences
If 1 is too small, 4J,! Growth does not occur.

A silicon crystal layer grows on the silicon substrate, but S
Since the silicon of the iO2 layer 1= is etched by [1], no silicon is deposited on the 5102 layer 1 (FIG. 16(d)). The thickness of the n single layer 5 is, for example, 3~
5 It is a practical matter.

The impurity concentration is &I or preferably 1012~1g +sc
Set it to about m-3. Of course, it is possible to deviate from this range, but it may be completely depleted at the diffusion potential of the pn-junction (with the operating voltage applied to the collector).
It is desirable to select an impurity concentration and thickness such that at least the n-region is completely depleted.

Usually available IJCI gas contains human moisture, so an oxide film is constantly formed on the surface of the silicon substrate, making it impossible to expect high-quality epitaxial IBM. HCl reacts with the material in the cylinder when it is in the cylinder, and contains a large amount of heavy metals, mainly iron, so it is used in optical sensor cells that tend to become contaminated with heavy metals. The shrimp layer has [11] The smaller the current component, the more desirable it is.
Heavy metal pollution must be suppressed to the absolute minimum. Si
H.

Of course, an ultra-high purity material is used for C1, but for HCi, a material with particularly low water content, preferably at least 0.5 pp or less water content, is used. Of course, the lower the water content, the better.

In order to obtain an even higher quality epitaxial growth layer, the substrate is first treated at a high temperature of about 1150 to 1250°C to remove oxygen from near the surface, and then heat treated for a long time at about 800°C, which generates many micro-defects inside the substrate. It is also extremely effective to use a substrate that has a denuded zone and is capable of indolithic gettering.
Since epitaxial growth is performed using L, Si
In order to reduce the uptake of oxygen from n, the lower the growth humidity, the better. In the commonly used high-frequency heating method, there is a lot of contamination from the carbon susceptor, and it is difficult to lower the temperature further. The wafer direct heating method using lamp heating without using a carbon susceptor provides the cleanest growth atmosphere and allows high-quality shrimp layers to grow at low temperatures.

For the wafer support in the reaction chamber, ultra-high purity fused sapphire, which has a lower folding pressure, is suitable. The wafer 1a contact heating method using lamp heating, which allows easy preheating of the raw material gas and makes it easy to equalize the temperature within the eight surfaces of the urchin even when a large flow of gas is flowing, produces almost no thermal stress, and produces high-quality epitaxial layers. Good for getting layers. Ultraviolet irradiation of the wafer surface during growth further improves the quality of the shrimp layer.

Amorphous silicon is deposited on the sidewalls of the Sin layer, which will become the isolation region 4 (see r (C) in Figure 16).
In, the crystal near the interface with the separation region 4 becomes very good. After forming the high resistance n-layer 5 by selective epitaxial growth (FIG. 16 (d)), a P region 6 with a surface concentration of about 1 to 20×10”C11 is formed by diffusion from doped oxide or It is formed to a predetermined depth by diffusion using a low-dose ion-implanted layer as a source.

The depth of p region 6 is, for example, about 0.6 to 1 path.

The thickness and impurity concentration of P region 6 are determined based on the following considerations. In order to increase the sensitivity, it is desirable to reduce Cbe by lowering the impurity concentration of the p region 6. Cbe is given as follows.

However, Vbi is the emitter-e-base diffusion potential, which can be expressed as follows. Here, ε is the dielectric constant of silicon crystal, N
is the impurity concentration of the emitter, N is the impurity density of the portion of the base adjacent to the emitter, and Di is the intrinsic carrier concentration. The smaller N is, the smaller Cb@ is, and the sensitivity is LJf. However, if N is made too small, the base region will be completely depleted in the operating state, resulting in a punch-through state, so it cannot be made too low. It is set to such an extent that the base region is not completely depleted and a punch-through state occurs.

After that, the silicon substrate surface tTH(l(t +o, )
A thermal oxide film 3 with a thickness of several 1 OA to several 100 Å is formed by dregs-based steam oxidation at a temperature of about aOO to 900''C.
Nitride film (STS N4) 302 is 50%
It is formed with a thickness of about 0 to 1500A. Formation temperature is 70
The temperature is about 0 to 900°C. Nil and gas, as well as NCI gas, are usually made by hand and contain a large amount of water. If Nil or gas with a high moisture content is used as a raw material, the result will be a nitride film with a high oxygen concentration, resulting in poor reproducibility.
The subsequent selective etching with the Sin and film results in an inability to obtain a selectivity.

NH and gas should also have a water content of at least 0.5 pp■ or less. It goes without saying that it is more desirable to have less moisture content.
Deposit Q300 by CVD. For example, the gas system uses (My + 5IHa + 02 + PHi) at a temperature of about 300 to 450 °C and a temperature of 2000 to 30 °C.
A PSG film with a thickness of about 00A is deposited by CVD (
In step (e) of FIG. 16, photolithography including two mask alignment steps is performed to form the n+ region 7 J- and the refresh and readout pulse application electrodes.
A S-doped polysilicon film 304 is deposited. In this case, a P-doped polysilicon film may be used. For example, the emitter [
Yu is p S G llu.

All of the Si3N4 film 1sho, a is removed, and the 5i02 film of F is left in the area where refresh and read pulse application electrodes are provided, and the PSG film and Sil
N, etching only the film. After that, ^S-doped polysilicon was added to (N2 +5ill 4 +AsH1
) or (H, + SiH4+ AsH,) Cas-
Deposited by cCVD method. Deposition temperature is 550°C~7
The temperature is about 00°C and the film thickness is 1000-2000A. Of course, non-doped polysilicon may be deposited by CVD and then S or P may be diffused. Emitter and refresh and read pulse application weight 4% I
The other portions of the polysilicon film except for Z are removed by etching after one step of mask alignment photolithography. Furthermore, when PSGFfA is etched, the polysilicon deposited on PSGFlli is removed in a self-aligned manner due to lift-off (step (f) in Figure 16).
)), kneeling of polysilicon film is C2C1t F
Etching is performed using a gas system such as (CB r F5 + c 12 ), and 5ilN4a is CH.

Etch with gas such as F7.

Next, after PSGl 151305 is deposited by the gas-based CVD method as described above, a contact hole is formed on the polysilicon ridge for the refresh pulse and read pulse electrodes by a mask alignment process and an etching process. In this state, AI, ^1-3i, A-C
Deposit metal such as u-9i by vacuum evaporation or sputtering, or (C:Hff) i A sentence or A1
1 is deposited by the plasma CVD method using C11 as the raw material gas, or by the light irradiation CVD method in which the raw material gases listed above, such as 1-C pounds and 1-01 pounds, are cut by direct light irradiation. (CL) x A gL and ^2C1
, is used as the raw material gas. ■ When performing a CVD method such as Nisashi, a large excess of hydrogen is allowed to flow. In order to deposit An into a narrow and steep contact hole, there is no need for moisture or oxygen to be mixed in. 300-400 in a clean atmosphere
The CVD method, which increases the substrate temperature to the film thickness in °C, is superior. After patterning the metal wiring 10 shown in FIG. 1, one interlayer insulation layer 18i 306 is deposited by CVD. 306
is the above-mentioned PSG film or CVDVD method 02 film,
Or, if yellow is required due to water resistance etc., (
Sil! , +NII, ) Si:+N41sJ formed by a dregs-based plasma CVD method. 5i3N
In order to suppress the hydrogen-containing acid in 41FJ, (5
A plasma CVD method in a gas system (il14 + N2) is used.

The Si3N4 film formed by the photo-CVD method is excellent in increasing the electrical breakdown voltage of the Si3N4 film formed by the plasma CVD method and reducing the leakage current. There are two types of photo-CVD methods.

(SiH4+Nlh +8g) A method of irradiating ultraviolet rays from the outside to 2537 of a mercury lamp in a gas system, and (S
iH4+NH) 1 gas system is irradiated with 1848A ultraviolet light from a mercury lamp. In both cases, the substrate temperature is 15
The temperature is about 0 to 350°C.

Mask alignment process and etching [Depending on the process, a contact hole penetrating the insulating film 305. 1
- Deposit gold 14 such as Cu-3i. In this case, since the aspect ratio of the contact hole is large, the deposition force by the CVD method is excellent113. After completing the turning of the metal wiring 8 shown in FIG.
It is deposited by the VD method (FIG. 16(g)).

In this case as well, the film produced by the photo-CVD method is superior.

12 is A1 on the back side. This is a metal electrode made by ^1-5i etc.

There are many different methods for manufacturing the photoelectric conversion device of the present invention, and FIG. 16 shows only one example.

The important point of the photoelectric conversion device of the present invention is that I! between p region 6 and n- region 5 and between p region 6 and n+ region 7! The problem lies in how to keep the leakage current of No. 1 to a minimum.

In addition to improving the quality of the n-region 5 and reducing dark current, the interface between the isolation region 4 and the n-region 5 made of an oxide film, etc. (this is a 1m problem. In FIG. 16, To this end, a method has been described in which amorphous Si is first deposited on the side wall of the separation region 4 and then shrimp growth is performed. In this case, amorphous Si is made into a single crystal by solid phase growth from the Si substrate during growth. Shrimp growth takes place at a relatively high temperature of about 850° to 1000°C. Therefore, microcrystals often begin to grow in the amorphous Si before the amorphous Si is made into a single crystal by solid-phase growth from the Si substrate, which causes poor crystallinity. Once the power is low.

Since the speed at which solid phase growth occurs is relatively much higher than the speed at which microcrystals begin to grow in amorphous Si, the temperature at 550°C to 7-00°C before selective epitaxial growth is
If amorphous Si is made into a single crystal using a low-temperature process, the characteristics of the interface will be improved. At this time, oxidation l15! between the substrate Si and the amorphous S1! If such a layer exists, the start of solid-phase growth will be delayed, so an ultra-high cleanliness process that does not include such a layer at the boundary between the two is required.

In addition to the above-mentioned furnace growth, for solid phase growth of amorphous Si, a rapid annealing technique is also effective, which involves keeping the substrate at a certain temperature and using flash lamp heating or an infrared lamp, for example, for about a few seconds to 910 seconds. When using these techniques, the Si deposited on the sidewalls of the layer may be polycrystalline, but it is deposited in a very clean process, with oxygen and oxygen at the grain boundaries of the polycrystalline material.
It is necessary to use polycrystalline Si that does not contain carbon or the like.

After the Si on the SiO2 side is single crystallized, the Si
This will result in selective growth.

When leakage current at the interface between the SiO2 isolation region 4 and the high resistance n-region 5 becomes a problem, the S of the high resistance n-region 5
This problem of leakage current can be avoided by increasing the n-type impurity concentration in the portion lJ≧adjacent to the isolation region 4. For example, min @ Sin, n- touching region 4
The n-type impurity placement is increased only in the region 5 with a thickness of about 0.3 to 1 #Lm, for example, about 1 -10 x 10" c -3. This structure is relatively easy. After forming a thermal oxide film of about 1L haze on the substrate, the film is first deposited by CVD on the substrate to the required thickness, containing P of a predetermined acid. 5iOz
Set it to IIA. Furthermore, CVD of Sin in 42
Separation regions 4 are created by depositing by a method. In the subsequent high-temperature process, phosphorus diffuses from the phosphorus-containing Sin film present in a sandwich form in the separation region 4 into the high resistance n-region 5, and the impurity concentration at the interface is the highest (+(7).
Creates a good impurity distribution.

In other words, the structure is as shown in FIG. 17. The isolation region 4 has a three-layer structure, in which 308 is a thermal oxide film of Sin, and 309 is a CVD SiO film containing phosphorus.
0 separation region 4, where 301 is a CVD Si02 film.
Adjacent to and between the n-region 5, an n-region 307,
It is formed by diffusion of SiO containing phosphorus from the film 309.

307 is formed all around the cell. With this structure, the base-collector distance 1l-Cbc becomes large, but the base-collector leakage current is drastically reduced.

In FIG. 16, an example was explained in which the isolation insulating region 4 is formed in advance and one selective epitaxial growth is performed. U group separation technology (^, Ha
yasakaet at, “U-groove 1s
olation technique forhigh
5peed bipolar VLSI'S'',
Tech, Dig, ofIEDM, P, B2.
+982. This can also be done using (see).

The photoelectric conversion device according to the present invention forms a bipolar transistor in which the base region, most of which is adjacent to the surface of the semiconductor, is in a floating state in a region surrounded by an isolation region made of an insulator. This device converts optical information into optical units by controlling the plane position of the floating base region with an electrode provided on a part of the +111 base region via a thin insulating layer. An emitter region made of a high impurity concentration region is provided in a part of the base region, and this emitter is connected to a MOS transistor operated by a water 1L scan pulse. The aforementioned electrode provided on a portion of the floating base region via a thin insulating layer is connected to the water gel line. The collector provided inside the wafer may be composed of a substrate, or depending on the purpose, it may be composed of a high-a-grade impurity physico-containing region separated for each tree 1t line on a high-resistance substrate of the opposite conductivity type. In some cases. The pulse voltage applied when reading out a signal is substantially larger than the pulse voltage when refreshing the floating base region with the electrode provided through the insulating layer. In fact, a pulse train with two types of voltages may be used, and as explained in the Dub 1 Recapacitor Construction, the capacitance Cow of the readout MOS capacitor electrode can be made larger than the capacitance Cox of the refresh river MOS capacitor electrode. You can leave it as is. By applying a refresh pulse, photoexcited carriers are accumulated in the floating base region which is in a reverse bias state, and a signal (based on the optical signal) is recorded, and when reading out the signal, the base region is
The feature is that a reading pulse voltage is applied so that the space between the emitters is deeply noisy in the forward direction, so that signals can be read out at high speed. As long as such a 1N characteristic is provided, the photoelectric conversion device of the present invention may be realized with a structure of I/1, and it is needless to say that it is not limited to the structure described in the above embodiments.

For example, the same applies to a structure in which the conductivity type is completely reversed to that described in the embodiment described in iii. However, at this time, it is necessary to completely reverse the polarity of the applied voltage. In a structure where the conductivity types are completely reversed, the region would be n-type. In other words, the impurities that make up the base are ^S and P.
become. ^When the surface of a region containing S and P is oxidized, As
and P pile up on the Si side of the S+/S+02 interface. That is, a strong drift field is generated inside the base from the surface toward the inside, and the optically excited holes immediately move from the base to the collector side, and electrons are efficiently accumulated in the base.

・When the ＼-s is p-type, the impurity usually used is poron. When the p-region surface containing poron is oxidized by /'8, poron is incorporated into the oxide film, so Si/Si
The poron concentration in the Si near the 02 interface is slightly lower than the poron concentration inside. This depth is IBt oxide! Depending on the thickness, there are usually several hundred people. A reverse drift electric field for electrons is generated near this interface, and if the electrons that are photoexcited in this region tend to be collected on the surface, the region that generates this reverse drift electric field will become an insensitive region. However, in the photoelectric conversion device of the present invention, an n+ region exists in a part along the surface;
Electrons gathered at the Si/Sing interface in the 9n region flow into this n1 region before being coupled to +l). Therefore, even if boron is reduced near the Si/Sio interface, a reverse drift electric field will occur. Even if such a region exists, it will hardly become a dead region.In fact, if such a region exists at the Si/5i02 interface, the accumulated holes will be separated from the Si/5i02 interface and exist inside. In order to do this, the effect of holes disappearing at the interface is eliminated, and the hole # end effect at the base of the pat becomes good, which is extremely desirable.

As described above, the photoelectric substation device of the present invention has a feature in which carriers excited by light are multiplied in the base region, which is the flj control electrode in a floating state. That is, Ba5e 5tore ImageSe
It is a device that should be called NSOR and is abbreviated as BASIS.

The photoelectric conversion device of the present invention uses one transistor to achieve li!
It is extremely easy to increase the density because it can be composed of elements, and at the same time, its structure causes less blooming and smearing, and it has high sensitivity. Its dynamic range is wide, and its internal amplification function generates a large signal voltage regardless of the wiring capacitance, so it has the characteristics of low noise and easy peripheral circuitry. As a solid-state imaging device, its industrial value is extremely high.

In addition to the above-mentioned solid-state imaging device, the photoelectric conversion device related to Unreleased III can also be used, for example, image input devices such as manual image processing, facsimiles, workstations, digital copying machines, word processors, OCR, and bar code reading. It can also be applied to photoelectric conversion object detection devices for autofocus devices, cameras, video cameras, 8mm cameras, etc.

FIG. 8(b) shows a transient refresh operation, an accumulation operation,
The graph shows the potential levels at each part of the emitter, base, and collector during the continuous operation and the transient refresh operation.

The voltage level of each part is the potential seen externally.

There are some areas that do not match the internal potential level.

To simplify the explanation, the emitter-base diffusion potential is excluded. Therefore, when the emitter and base are represented at the same level in the FF18 diagram [b], there actually exists a diffusion potential applied between the emitter and the base.

In m81 (b), the state Φ, palpitation) is a reflation.

The state [phase] indicates the storage operation, the state S@, @ indicates the read operation, and the state ψ indicates the operating state when the emitter is grounded.The potential level increases from 0 port. It is assumed that the base potential of the song in state 2, where the side indicates negative potential and the bottom indicates positive potential, is zero volts, and the collector potential is biased from state Φ to state Φ (all the way to iF, itt).

The series of operations described below will be explained with reference to the timing diagram of FIG. 8(a).

As shown in the waveform 67 in FIG. 8(a), at time t1,
Terminal 37 uses LTE Denkawa, ie Lift Sea. When the voltage vllllH is applied, the 81st, 4th (b) state (
]) There is already a theory 1j on the base like 1C 200
Like 1.

A partial pressure is applied. This potential gradually decreases toward zero potential between time t1 and t2, and at time t, 1! of FIG. 8(b)! The potential becomes the potential 201 shown by the vertical line. As explained earlier, this potential is the potential vk that remains at the base in the 'djr transient refresh mode. lI! At FMt, waveform 6? As shown, at the moment when the refresh +t v 4 returns to zero voltage, 1E voltage of −, V Cox + Cbe + Cbe is generated in the base by division in the same way as +iij, so the pace is the remaining voltage VK The potential is the sum of the voltage and the newly generated voltage. That is, the state fil:
This is the pace potential 202 shown in the LR month.

is given by

When light enters such an emitter in a reverse bias state, holes generated by this light are accumulated in the pace area, so that Therefore, the base potential 202 is the base potential 20
3,203'.

203'', the potential gradually changes toward positive potential.

Ru. Let the voltage generated by this light be Vp.

Next, as shown in the hourglass shape 69, a voltage is applied to the horizontal line from the vertical shift register, that is, a read voltage V.

When is applied, a voltage η is applied to the base, so the base potential 204 when no light is irradiated is as follows. As explained earlier, the potential 204 at this time is
It is set so that the emitter is biased in the forward direction by about 0.5 to 0.ev. Also.

The base potentials 2051, 205', and 205'' are respectively You can get it, you can get it.

The base potential is thus relative to the emitter.

When forward biased, electron G is injected from the emitter side, and the emitter potential gradually moves toward a positive potential. The emitter potential 206 with respect to the base potential 204 when no light is irradiated is approximately 50 to 1 OOm when the forward bias is set to 0.5 to 0.6 V and the read pulse width is about 1 to 2 ps. V, and if this voltage is vI, the emitter potential 2
07.207'.

207'', as in the previous example, linearity is sufficiently ensured if the pulse width is less than 0.1 JLs, so each V
p 10V@+, Vp '+-vll, vp ''+V
B,! :Become.

After a certain readout time, when the readout voltage V reaches zero degree potential as shown in waveform 69, the voltage that becomes the base is added, so the base potential becomes the readout pulse as shown in fr\(%). The state before is applied.

In other words, it becomes a reverse bias state, and the emitter stops increasing its potential. That is, the base potential 20B at this time
The base potentials 209, 209', and 209'' are respectively, q- is obtained by Cbe. This is the state 43) before reading starts.
It's a complete turn of events.

This situation is 7! ? In tIj), Emi 1. The optical information No. 411 on the data side is read out to the outside. After this reading is completed, each switching MO3) run transistor 48.
48', 4B" became 4 letters, Emi.

The emitter is grounded and the emitter is at zero potential (like a mountain). This completes a cycle of refresh operation, storage operation, and readout operation, and then returns to state (2).
At this time, before starting the refresh operation for the first time, the base potential started from zero potential, but after reaching -g, the pace 1 [position is ot V, -□ meeting VRH CO! +Cbe+Cbc and Vp, Vp', Vp'' are added to it, respectively. Therefore, in this state, even if refresh i[(voltage VIIH is applied, the base potential is v(.

Vy +Vp , V(+Vp ′, V(+Vp ″). In this case, sufficient forward bias is not applied to the base, and the amount of forward bias is large in areas that are strongly hit by light, so optical information is lost. It is fjS6 that although the information in the weak light area disappears, the information in the weak light area remains.
This is clear from the example of the refresh operation shown in the figure.

Such a phenomenon is unique to the transient refresh mode, and in the complete refresh mode, such a problem does not occur because a long refresh interval is taken until the base potential always reaches zero potential.

A method that uses a transient refresh mode capable of high-speed refresh and that does not cause such inconvenience will be described below.

This disadvantage is caused by the same voltage value being applied to the base region when the refresh pulse is applied and when the read pulse is applied, caused by the positive and negative capacitance division at the leading and trailing ends of the pulse. Since this is a phenomenon, this problem can be solved by somehow clamping the value to a constant value when a negative voltage is applied to the base region.

FIG. 18 shows an embodiment for achieving this. 1st
FIG. 8(a) shows a cross-sectional view of a sensor cell, and FIG. 18(b) shows an equivalent circuit of FIG. 18(a).

In FIG. 18(a), in the basic sensor cell of FIG. 1 already explained, S10 is used to separate the sensor cell.
．． A p4'' region 251 and an n+ region 252 forming a p+ n+ junction diode are additionally added, and this n1 region 252 is connected to the base region 6 of the sensor cell by an aluminum wiring 253, and a p+ region 250 is added.
+) region has a structure in which it is connected to an external power source by an aluminum wiring 254. The other parts are exactly the same as the basic sensor cell shown in FIG. In the equivalent circuit of FIG. 18(b), a p+-n+ junction diode 255 consisting of a p+ region 251 and an n+ region 252 has its anode side (p'' region side) connected to a wiring 254 for connecting to an external power supply. The cathode side (n+ region side) is connected to the base side of the basic photosensor cell.The other parts are the same as the equivalent circuit of the basic photosensor cell shown in FIG.

According to this configuration, in the state (c) of FIG. 8(b),
At the end of the refresh pulse, the negative potential of the base region 20
2 becomes "Cox+Cbe+Cbc"" is the voltage -Vc supplied from the wiring 254.
It will be done. That is, the clamp voltage -Vc
When the potential becomes lower, current flows through the four diodes 255, and the voltage is finally clamped to the clamp voltage -Vc.

The clamp level -Vc at this time is set to the optimum level -Vc in consideration of the refresh speed in the transient refresh mode operation, the IF direction bias in the read operation, the dynamic range of the optical signal, etc.

The clamp voltage -Vc is set appropriately, but in the n+ region 25
A desired voltage -Vc can be obtained by controlling the impurity density of 2 and p''251.

It is shown below. An optical sensor cell with a pn junction tie-out for clamping can reliably solve the problems that occur in 1fiW refresh mode operation, making it possible to provide an image sensor capable of high-speed refresh using IRF. It is.

In the embodiment shown in FIG. 18, a wiring 8 from the MOS capacitor' electrode emitter 7, a wiring 2 for connecting the base 6 and the n+ region 252 of the pn junction diode.
53. Wiring 254 etc. for supplying voltage to the p+ region 251 of the pn junction diode for convenience of explanation] 2. All times -
This is an old-fashioned model with very few windows through which light enters, but in reality, each light enters other parts of the same optical sensor cell depending on the shape of the window and the wiring. It is possible to arrange them in consideration of convenience and the like.

[Brief explanation of drawings]

FIG. m1 to FIG. 6 are diagrams for explaining the main structure and basic operation of an optical sensor cell according to an embodiment of the present invention. Figure 1 (a) is a 1L side view, (b) is a sectional view, (C
) is an equivalent circuit diagram, Fig. 2 is an equivalent circuit diagram during readout operation, tJS3 is a graph showing the relationship between readout time, readout 1V, and voltage, and Fig. 4(a) is a graph showing the relationship between storage voltage and readout time. Figure 4 (b) is a graph showing the relationship between bias voltage and read time, Figure 5 is an equivalent circuit diagram during refresh operation, and Figures 6 (a) to (C) are graphs showing the relationship between bias voltage and read time. It is a graph showing the relationship with the base potential. 714 to 10 are explanatory diagrams of a photoelectric conversion device using the optical sensor cell shown in FIG. 1, FIG. 7 is a circuit diagram, FIG. 8(a) is a pulse timing diagram, and FIG. b) is a graph showing t position/lt during each operation. Figure 9j
FIG. 10, an equivalent circuit diagram related to the output signal, is a graph showing the output voltage from the moment of conduction in relation to time. 11.12 and 13 are circuit diagrams showing other photoelectric conversion devices. FIG. 14 is a plan view for explaining a modification of the optical sensor cell according to the embodiment of unoccurred IJI. 1st
FIG. 5 is a circuit diagram of a photoelectric conversion device using the optical sensor cell shown in FIG. 14. FIGS. 16 and 17 are cross-sectional views showing an example of a method for manufacturing a photoelectric conversion device of the present invention. FIG. 18 shows a photosensor cell according to an embodiment of the present invention,
(a) is a cross-sectional view, and (b) is its equivalent circuit - for children. l...Silicon substrate, 2...PSG film, 3...Insulating oxidation! 1, 4...element isolation region, 5...n- region (collector<(I region), 6...p region (base region), 7.7'...n+ region emitter region) , 8...
・Wiring, 9...electrode, 10...wiring, 11...n
+ region 12...electrode, 13...capacitor, 14
... Bipolar transistor, 15, 17... Junction vg amount, 16, 18-1'4 ode, 19.19'.
... Contact portion, 20... Light, 28... Vertical line, 30... Optical sensor cell, 31... Horizontal line,
32...Vertical shift register, 33.35...MO
S) transistor, 36.37...terminal, 38...vertical line, 39...horizontal shift register, 40...
MOS) transistor, 41...output line, 42...
・MOS) transistor, 43... end r-144...
Transistor, 44.45...Load resistance. 46...Terminal, 47...End f-, 48...MOS
Transistor, 49...terminal, 61.62.63...
・Section, 64...Collector' shift, 67...Waveform,
80.81... Capacity, 82.83... Resistance, 84.
...Current source, 100.101,102...Water shift register, 111.112...Output line, 138
...Vertical line, 140...MOS tarantista,
148...MOS transistor, 15θ, 150'・
...MOS capacitor, 152,152'...Photo sensor cell, 202.203,205...Base potential, 2
20...P+ region, 222, 225... Wiring, 25
1...P+ region, 252n+ region, 253...wiring, 300...amorphous silicon, 302...nitride n9.303...P S G It! 2.304・
...Polysilcon, 305...PSG film, 306...
・1 layer insulation. Fig. 1 Fig. 1 Fig. 2 Fig. 5 Fig. 4 (b) / Luna // Procedural amendment May 23, 1980 Kazuo Wakasugi, Commissioner of the Patent Office1, Indication of the case, Patent Application No. 1982-1207532, Name of the invention, photoelectric conversion device3, Relationship of the person making the amendment to the case Patent applicant name: Tadahiro Oomi 4, agent address: 40 Toranomon, 5-13-1 Toranomon, Minato-ku, Tokyo Mori Building Detailed explanation of the invention in the specification Column 6, Contents of amendment (1) Specification No. 19 Change rlocm”J in line 12 of the page to “
1QI31″3”. (2) Amend the statement on page 22, line 6 of the specification. (3) rl O [sec] on page 34, line 14 of the specification
Correct J to r l O”[5ecl J.
Correct the voltage V^. (5) Delete the buffer MOS transistors 33, 33' and 33''J from the 5th line to the 4th line from the bottom of page 41 of the specification. (B) “Hakutsurip” on page 45 of the specification, second line from the bottom
Correct as "clip". (7) On page 53, line 6 of the specification, before “essentially”, “
Insert "Do". (8) Insert "ni" after "midway" in the seventh line from the bottom of page 53 of the specification. (8) “Emitter 7, wa” on page 64, line 1 of the specification
is corrected as "emitter 7.7'is". (lO) In the specification, page 64, line 6, "emitter has contact hole 1" is corrected to "emitter 7 has contact hole 19". (11) “Horizontal line 3” on page 64 of the specification, line 8 from the bottom
"to" is corrected to "to horizontal line 31'." (12) "In cell 15" in the sixth line from the bottom on page 64 of the specification is corrected to "in cell 152'." (!3) "rMoS capacitor 15" on the sixth line from the bottom of page 64 of the specification is corrected to "rMOs capacitor 150". (14) “Horizontal line 3” on page 64 of the specification, line 5 from the bottom
"to" is corrected to "to horizontal line 31'." (15) In the third line from the bottom of page 64 of the specification, "photo sensor cell 15" is corrected to "photo sensor cell 152'". (16) "Photosensor cell 15" in the second line from the bottom on page 64 of the specification is corrected to "Photosensor cell 152". (17) "On horizontal line 3" in lines 6 to 7 and line 12 on page 66 of the specification is corrected to "on horizontal line 31'." (18) The optical sensor cell 15 is
Photosensor cell 152 through MoS capacitor 150'
Correct it with 'no'. (18) Second and first lines from the bottom of page 66 of the specification,
Page 67, line 8: [Correct optical sensor cell J to "optical sensor cell". (20) “Collector” on page 68 of the specification, line 5 from the bottom
is corrected as "collector". (21) "n embedded area" in the fourth line from the bottom and third line from the bottom of page 68 of the specification is corrected to "n+ embedded area". (22) Replace “(C).” on page 77, line 7 of the specification with r (
C) ). ” he corrected. (23) Amend the statement on page 78, line 1 of the specification. (24) Amend the statement on page 78, line 4 of the specification. (25) "N is the impurity concentration of the emitter, N is the base" on page 78, line 6 of the specification is corrected to "No is the impurity concentration of the emitter, N^ is the base". (2B) “N” on page 78, lines 8 and 9 of the FIA specifications
" is corrected to "N^". (27) Specification page 53 bottom line 10 c7) rsio
2, 309 is corrected to ``rsi02.309''. (28) In page 91, line 12 of the specification, ``r of the present invention'' is amended to ``r of the present invention''. (28) Change “Gron” in the fourth line from the bottom of page 96 of the specification to “
"Tron," he corrected. (30) rVp+V@+J on page 97, line 6 of the specification
Correct as VP+V@J. (31) Correct “rp” 251J on page 102, line 1θ of the specification to “p middle region 251”.

Claims (1)

[Claims] 1 The control electrode region of a semiconductor transistor consisting of two main electrode regions of the same conductivity type and the control electrode region of the opposite conductivity type to the main electrode region is brought into a floating state, and the potential of the control electrode region brought into the floating state is controlled via a capacitor to 'JFI' carriers generated by light into the floating control electrode region, and a readout operation to read out the accumulated voltage generated in the control electrode region by the accumulation operation. A photoelectric conversion device having a structure in which a refresh operation is performed to eliminate carriers accumulated in the control electrode region, characterized in that a clamp diode is provided to control the potential of the control electrode region in a floating state. conversion device.