JPS6216685A - Two-dimensional solid-state image pickup device - Google Patents

Two-dimensional solid-state image pickup device

Info

Publication number
JPS6216685A
JPS6216685A JP60155033A JP15503385A JPS6216685A JP S6216685 A JPS6216685 A JP S6216685A JP 60155033 A JP60155033 A JP 60155033A JP 15503385 A JP15503385 A JP 15503385A JP S6216685 A JPS6216685 A JP S6216685A
Authority
JP
Japan
Prior art keywords
picture element
signal
element cell
windowing
reading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60155033A
Other languages
Japanese (ja)
Other versions
JP2583485B2 (en
Inventor
Akio Kosaka
明生 小坂
Yutaka Yunoki
裕 柚木
Junichi Ishibashi
石橋 純一
Tsutomu Nakamura
力 中村
Hidetoshi Yamada
秀俊 山田
Yoshinori Oota
好紀 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP60155033A priority Critical patent/JP2583485B2/en
Publication of JPS6216685A publication Critical patent/JPS6216685A/en
Application granted granted Critical
Publication of JP2583485B2 publication Critical patent/JP2583485B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To realize a windowing with a simple constitution without providing a special circuit by providing plural vertical reading lines between picture element cell array arranged in a matrix shape and performing the windowing with reading simultaneously plural picture element cells. CONSTITUTION:Each two of vertical reading lines provided by every picture elements array sends out a signal accumulated at each picture element cell to a signal selection circuit 400. The signal sent to the signal selection circuit 400 is taken out at signal lines 411 and 412 by switching control signals H1...Hm from a horizontal scanning circuit 200 through switches 401-406, and is given to an image process part 500 by a select signal supplied to a select signal input terminal 413 through data selectors 407-410. And by changing the vertical reading line numbers of each array, the connection method of the output line of each picture element cell against the above and the number of the picture element cell that performs a simultaneous reading, it is possible to perform optionally the windowing.

Description

【発明の詳細な説明】[Detailed description of the invention]

〔産業上の利用分野〕 この発明は二次元固体撮像装置に関する。 〔従来の技術〕 一般に、二次元固体撮像装置において撮像された画像は
電気信号に変換され、二次元的にスキャンされることに
より外部装置に与えられ、画像処2゛理等の信号変換が
施されることが多い。例えば入1力された画像信号のノ
イズ除去あるいは画像強調等を行う際には、二次元的な
局所領域(ウィンドとして、その画像に8×8のコンポ
ルージョン演算を施す場合には、MxNの画像の濃度値
X1jに対して次のような処理を施し出力7月を得るよ
うにしている。 yij =Σwpq Xi+p−2,j+q−2+++
 (1)p+ q=1 t 2+ 8 (i = L21−−−、M: j ” 1121−−−、N) ここで、Wpqは荷重係数であり、例えばノイズ+5除
去の場合には第10図のような値を、画像強調の場合に
は第11図のような値がとられる。また、この荷重係数
は一般的に中心に関して円対称であることが多い。 一方、こうしたウィンドウ処理を施す従来の方20法と
しては第12図に示すようなものがある。こ1の従来例
においては、二次元固体撮像装置1から得られる一次元
データを、−行分の二本のディレィライン2a 、 2
bと8×8のディレィエレメント8a〜81とで形成し
た8×3のウィンドウ処理部−・路に供給して上記(1
)式で表わされる積和演算することによりウィンドウ処
理するものである。しかしこの方式においては、−行分
のディレィラインを二本必要とするため、構成が複雑に
なり、高価になるという問題があった。 このような問題を解決するものとして、特開昭57−9
5768号公報において、非破壊読出し可能な二次元固
体撮像装置を利用して三個の垂直方向の画素の濃度値を
同時に読出すようにしたものが提案された。 (発明が解決しようとする問題点〕 しかしながら、−り記の特開昭57−95768号公報
に開示された二次元固体撮像装置にあっては、第12図
におけるような一行分の二本のディレィラインは不要と
なるが、その代わり水平方向パの画素走査は、基本クロ
ックによって画素セルか1ら読出され、データセレクタ
により基本クロックに同期させて信号を切り換えるため
、画素セルのスイッチング特性を高速にすることが必要
であるとともに、データセレクタにおいては三本のデー
−・タラインにデータを送出するための特別な回路が必
要になるため、装置の簡略化および減価を図ることが困
難であるという問題がある。。 この発明は、このような従来の問題点に着目してなされ
たもので、簡単かつ安価な構成によりつ1
[Industrial Field of Application] The present invention relates to a two-dimensional solid-state imaging device. [Prior Art] Generally, an image captured by a two-dimensional solid-state imaging device is converted into an electrical signal, scanned two-dimensionally, and sent to an external device, where it undergoes signal conversion such as image processing. It is often done. For example, when performing noise removal or image enhancement of an input image signal, a two-dimensional local area (window) is used, and when performing an 8x8 convolution operation on that image, an MxN image The following processing is performed on the density value X1j to obtain the output July.
(1) p+ q=1 t 2+ 8 (i = L21---, M: j '' 1121---, N) Here, Wpq is a loading coefficient, and for example, in the case of noise+5 removal, as shown in FIG. In the case of image enhancement, a value such as that shown in Fig. 11 is taken.In addition, this weighting coefficient is generally circularly symmetrical about the center.On the other hand, conventional methods that perform such window processing There is a method as shown in Fig. 12 as a 20 method.In this first conventional example, the one-dimensional data obtained from the two-dimensional solid-state imaging device 1 is divided into two delay lines 2a for - rows, 2
b and 8x3 window processing section formed by 8x8 delay elements 8a to 81.
) Window processing is performed by performing the sum-of-products operation expressed by the equation. However, this method requires two delay lines for -rows, which makes the configuration complicated and expensive. As a solution to such problems, Japanese Patent Application Laid-Open No. 57-9
In Japanese Patent No. 5768, a method was proposed in which the density values of three vertical pixels were simultaneously read out using a two-dimensional solid-state imaging device capable of non-destructive readout. (Problems to be Solved by the Invention) However, in the two-dimensional solid-state imaging device disclosed in Japanese Unexamined Patent Application Publication No. 57-95768, as shown in FIG. A delay line is no longer required, but instead, horizontal pixel scanning is read out from pixel cells by the basic clock, and the data selector switches the signal in synchronization with the basic clock, so the switching characteristics of the pixel cells can be adjusted to high speed. In addition, the data selector requires a special circuit to send data to the three data lines, making it difficult to simplify and reduce the cost of the device. There is a problem. This invention was made by paying attention to such conventional problems, and has a simple and inexpensive structure.

〔発明の効果〕〔Effect of the invention〕

以上述べたように、この発明によれば一行分のディレィ
ラインを用いることなく、また特開昭57−95768
号公報におけるように、画素セ15ルのスイッチング特
性を高速にしたり、データを振分けるための特別な回路
を必要とすることなく、所望のウィンドウ処理を簡単か
つ安価な構成で容易に行うことができる。
As described above, according to the present invention, there is no need to use one line of delay line, and
As in the publication, desired window processing can be easily performed with a simple and inexpensive configuration without increasing the switching characteristics of the pixel cell 15 or requiring a special circuit for distributing data. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示す回路構成図ζ第2図
は画素セルの一例の構成を示す図、第8図はウィンドウ
処理における荷重係数の一例を示す図、 第4図および第5図は動作を説明するための信5号波形
図、 第6図は第1図に示す画像処理部の一例の回路構成図、 第7図はフンポル−ジョン演算の一例を示す図、第8図
はウィンドウ処理における荷重係数の他Illの例を示
す図、 第9図は第8図に示す荷重係数を用いる場合の画像処理
部の回路構成図、 第10図および第11図はノイズ除去処理および画像強
調処理における荷重係数の具体値の一例゛゛をそれぞれ
示す図、 第1z図は従来の技術を示す図である。 100・・・画素セル部   101〜115・・・画
素セル116〜121・・・垂直読出しライン200・
・・水平走査回路             ″゛20
1〜203・・・切換制御信号ライン800・・・垂直
走査回路 301〜805・・・制御信号ライン 400・・・信号選択回路  401〜406・・・ス
イ゛ンチ407〜410・・・データセレクタ 411、412.414.415・・・信号線418・
・・セレクト信号入力端子 500・・・画像処理部 第2図 第4図 第7図 第12図 槓#濱菫
FIG. 1 is a circuit configuration diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing the configuration of an example of a pixel cell. FIG. 8 is a diagram showing an example of a load coefficient in window processing. 5 is a waveform diagram of signal No. 5 to explain the operation, FIG. 6 is a circuit configuration diagram of an example of the image processing section shown in FIG. 1, FIG. 7 is a diagram showing an example of the Humpolsion operation, and FIG. The figure shows an example of Ill in addition to the weighting coefficient in window processing. Figure 9 is a circuit diagram of the image processing unit when using the weighting coefficient shown in Figure 8. Figures 10 and 11 are noise removal processing. FIG. 1 is a diagram showing an example of a specific value of a weighting coefficient in image enhancement processing, and FIG. 100... Pixel cell section 101-115... Pixel cells 116-121... Vertical readout line 200.
・Horizontal scanning circuit ″゛20
1-203...Switching control signal line 800...Vertical scanning circuit 301-805...Control signal line 400...Signal selection circuit 401-406...Switch 407-410...Data selector 411, 412.414.415...Signal line 418.
...Select signal input terminal 500...Image processing unit Fig. 2 Fig. 4 Fig. 7 Fig. 12

Claims (1)

【特許請求の範囲】[Claims] 1 マトリックス状に配列した非破壊読出し可能な画素
セルを有する二次元固体撮像装置において、各画素セル
列間に設けられ各列の画素セルの出力線が所定の関係で
接続された複数の垂直読出しラインと、垂直方向に連続
する複数の画素セルを同時に読出す手段とを具え、垂直
方向の連続する複数の画素セルを同時に読出しながらウ
ィンドウ処理を行い得るよう構成したことを特徴とする
二次元固体撮像装置。
1. In a two-dimensional solid-state imaging device having pixel cells arranged in a matrix that can be read out non-destructively, a plurality of vertical readouts are provided between each pixel cell column and the output lines of the pixel cells in each column are connected in a predetermined relationship. A two-dimensional solid body comprising a line and means for simultaneously reading out a plurality of vertically continuous pixel cells, and configured to perform window processing while simultaneously reading out a plurality of vertically continuous pixel cells. Imaging device.
JP60155033A 1985-07-16 1985-07-16 2D solid-state imaging device Expired - Fee Related JP2583485B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60155033A JP2583485B2 (en) 1985-07-16 1985-07-16 2D solid-state imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60155033A JP2583485B2 (en) 1985-07-16 1985-07-16 2D solid-state imaging device

Publications (2)

Publication Number Publication Date
JPS6216685A true JPS6216685A (en) 1987-01-24
JP2583485B2 JP2583485B2 (en) 1997-02-19

Family

ID=15597202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60155033A Expired - Fee Related JP2583485B2 (en) 1985-07-16 1985-07-16 2D solid-state imaging device

Country Status (1)

Country Link
JP (1) JP2583485B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5437427A (en) * 1977-07-13 1979-03-19 Hitachi Ltd Color solid state pickup element
JPS5795768A (en) * 1980-12-05 1982-06-14 Fuji Photo Film Co Ltd Two-dimensional solid-state image pickup device
JPS6012761A (en) * 1983-07-02 1985-01-23 Tadahiro Omi Photoelectric conversion device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5437427A (en) * 1977-07-13 1979-03-19 Hitachi Ltd Color solid state pickup element
JPS5795768A (en) * 1980-12-05 1982-06-14 Fuji Photo Film Co Ltd Two-dimensional solid-state image pickup device
JPS6012761A (en) * 1983-07-02 1985-01-23 Tadahiro Omi Photoelectric conversion device

Also Published As

Publication number Publication date
JP2583485B2 (en) 1997-02-19

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