JPS60120677A - Display device of picture - Google Patents

Abstract

PURPOSE:To carry out A/D conversion at low sampling frequency and to reduce power consumption and a cost by positioning sampling data for each scanning line at ternately by one dot so as to display them on one line. CONSTITUTION:A picture signal inputted from a signal line 11 is added to a synchronizing separator circuit 12, where horizontal and vertical synchronizing signals are separated and supplied to a timing control circuit 14. The timing control circuit 14 generates various types of timing signals in accordance with the synchronizing signal, and applies a sampling signal for an A/D convertor 13. The A/D convertor 13 converts a picture signal into a digital signal in accordance with the sampling signal and inputs it to a shift registor 15. The shift registor 15 writes data for one display line in a latch circuit 16 by a timing signal from the timing control circuit, and the data are transmitted from the latch circuit 16 to a display driver 17 so that data of the upper 1/2 rank and the lower rank 1/2 will be positioned alternately by one dot.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to an image display device for a liquid crystal television or the like.

[Prior art and its problems]

In recent years, liquid crystal televisions that use a four-channel liquid crystal display instead of a CRT have been put into practical use as television receivers. The display screen of the liquid crystal television is very small, and therefore, as shown in FIG. 1, for example, one out of every two scanning lines is sampled to display a video signal. Display screen 1
If the number of dots on the liquid crystal is nXm, then A/
The sampling frequency f8 of D (analog/digital) conversion is 5 times the effective video period in one scanning line of the video signal.
If it is 3μ8ee, it is expressed as 1/f s = 53/imμ8eC (1). Also, the number of effective scanning lines in one field is 240.
Since it is a book, it is sufficient to sample one every 240/n scanning lines.

Now, if we consider an LCD TV with h = 120 and m = 160, it would be sufficient to sample one out of every two scanning lines and display it on screen 1 at a sampling frequency of f8 x 3 MHz, as shown in Figure 1. I understand.

However, when sampling at a rate of 1 in 240/n lines as in the conventional method, time is wasted for the remaining scanning lines, and the sampling frequency is high.
There are problems in that power consumption increases and costs also increase.

[Purpose of the invention]

The present invention has been made in view of the above points, and provides an image display device that can be operated at a low sampling frequency during A/I conversion, and that can reduce power consumption and cost. The porpose is to do.

[Key points of the invention]

In the present invention, m pieces of data are sampled with 240/n scanning lines as one block, and the sampling data for each scanning line is displayed on one line/line by alternately positioning one dot at a time. This allows gays to lower the frequency of the signal.

[Embodiments of the invention]

The details of the case where the present invention is applied to a liquid crystal television will be explained below. In FIG. 2, 11 is a signal line into which a video signal from a previous stage video amplification circuit (not shown) is input. This video signal is sent to the sync separation circuit 12 and A
/D converter 13. The above synchronization separation circuit 12
separates the horizontal and vertical synchronization signals contained therein from the input video signal and inputs them to the timing control circuit 14. The timing control circuit 14 generates various timing signals in accordance with the synchronization signal, and provides sampling signals to the ADD converter 13. The sampling frequency f8 in this case is set by the following formula: m153 n clam m fl12 shell 〒-171MH7 (2). The ADD converter 13 is
The video signal is converted into a digital signal according to the sampling signal and input to the shift register 15. This shift register 15 has a capacity corresponding to one display line, for example, 160 dots, and the data held therein is written into the latch circuit 16 in synchronization with a timing signal from the timing control circuit 14. The data latched by this latch circuit 16 is composed of upper 1/2 data and lower 1/2 data.
data is sent to the display driver 17 so that each dot is positioned alternately. Fortunately, a brightness modulation circuit 18 is connected to this display driver 17. The brightness modulation circuit 18 provides a brightness modulation signal to the display driver 17 in accordance with the timing signal from the timing control circuit 14.

Further, the timing control circuit 14 provides a timing signal to the scanning circuit 19. Then, for example, a 120×160 dot liquid crystal display/channel 20 is driven to display by the display driver 17 and the scanning circuit 19.

Next, the operation of the above embodiment will be explained. The frequency fs of the sampling signal output from the timing control circuit 14 to the A/D converter 13 is set by the above equation (2). In this example, n=120 and m=160, so f8=n-m/12720=120X160/12720#1.5MI(y.

Therefore, the sampling frequency fs is approximately 1.5 MH
Set to z. Then, the ~width converter 13 samples the video signal according to the sampling signal,
Write to shift register 15. In this case, for example, the odd-numbered scanning lines are sampled in synchronization with the rising edge of the sampling signal, and the even-numbered scanning lines are sampled in synchronization with the falling edge of the sampling signal. do.

That is, in odd-numbered and even-numbered scanning lines, sampling is performed at shifted positions. Therefore, the sampling frequency f8 is 1/2 of the sampling frequency of 3 MHz when sampling every two scanning lines shown in FIG. Therefore, the data sampled by the A/I converter 13 is taken out at twice the interval, and the data for two scanning lines is written into the shift register 15. That is, one block consists of 240/n scanning lines, and the timing of scanning each scanning line in the block is shifted at equal intervals for each scanning line as shown in FIG. sample the data. In this embodiment, n2120, so two scanning lines constitute one block, m = 160 pieces of data are sampled, and the data is stored in the shift register 15. 1F is crowded. The data held in the shift register 15 is sent to the latch circuit 16 in synchronization with a timing signal from the timing control circuit 14. Finally, the data held in the child circuit 16 is input to the display driver 17 so that the data for the first scanning line and the data for the next scanning line are alternately positioned one dot at a time, and flannel 2
At θ, the image is displayed as shown in FIG.

That is, data for two scanning lines are displayed on one scanning electrode with dots positioned alternately.

As mentioned above, when 160 dots of data are sampled using two scanning lines as one processor, the sampling frequency f5 is approximately 1.5 Mf (z, which is 1/2
2, and it is possible to reduce the energy consumption by 11.

In the second embodiment, a liquid crystal display with a panel 20 is shown, but other dot configurations can be implemented in the same manner as in the first embodiment.

〔Effect of the invention〕

As described above, according to the present invention, multiple scanning lines can be
Since m pieces of data are sampled as a block and the sampled data for each scanning line is displayed on one line with one dot placed alternately, it is possible to operate at a low sampling frequency, and moreover, it is faster than the conventional system. Equivalent image quality can be obtained. Fortunately, by lowering the Zanf 0 ring frequency, it is possible to reduce the power consumption of the p1 system and reduce costs.

[Brief explanation of drawings]

FIG. 1 is a diagram schematically showing an image display method in a conventional liquid crystal television, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing a data sampling operation and a display operation in the same embodiment. It is a figure shown typically. 13...A/D converter, 15...shift register, 16...latch circuit, 17...display driver,
2θ...Liquid crystal display panel. 1.Konganjindai J, jjj Patent attorney Takeshi Suzue, 61
Figure 1

Claims (1)

[Claims] An image display device that samples analog image information sent from the outside, converts it into digital image information, and displays it on a display screen with an nXm dot structure, in which a plurality of scanning lines of analog image information Divide m pieces of data into one block. and means for displaying the sampling frequency for each scanning line in each block outputted by the means by alternately positioning one dot at a time on one line of the display screen. Image display device.