JPS6160088A - Picture display device - Google Patents

Abstract

PURPOSE:To improve picture quality and to display distinct pictures by switching display contents according to the first or second half of a back plate period using all information on effective scanning lines in a small-sized television receiver using a display panel with the number of scanning electrodes less than the number of effective horizontal scanning lines in a period of a field. CONSTITUTION:Gradation signals are created according to data output from a control circuit 2 and a liquid crystal display panel 11 is drived, while latch pulses -phiny are outputted in the first and second halves in a back plate period and the data kept in a shift register 4 is latched in a latch circuit 5. For example, in the timing when electrode drive signals are outputted, video signals held in a shift register 4 changed by the switch of the first and second halves in a backplate period are latched in the latch circuit 5 with latch pulse -phiny and sent to a gradation signal generation circuit 6. The gradation signal generation circuit 6 generates gradation signals to drive display on a liquid crystal display panel 11 through a maltiplexer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image display device in a small television receiver using a display panel.

[Prior art and its problems] In recent years, portable liquid crystal television receivers using liquid crystal display panels instead of CRTs have been put into practical use. Currently, the NTSC system is used in Japanese television broadcasting, and in this NTSC system, the vertical scanning period is 1
If it is a field, the number of horizontal scanning lines in that field is 262.5. For example, 120X16
When using a liquid crystal display panel with 0 pixels, the scanning side electrode is 1
The number of 20 lines is approximately 1/2 of the number of effective scanning lines for one field of a video signal, and one scanning side electrode is driven for display every two scanning periods. Therefore, in a liquid crystal television receiver using the above-mentioned liquid crystal display panel, one back plate period corresponds to two horizontal scanning periods of the video signal, but conventionally, data of only the video signal for one horizontal scanning period is sampled during that period. The data is used to display one backplate period. As described above, conventional liquid crystal television receivers accept only about half as many video signals as ordinary television receivers. For this reason,
Even if the video signal for the horizontal scanning period that is adopted by chance contains noise, it will be displayed as is over the period of one back plate. Roughly speaking, even if a series of adjacent video signals are quite different,
Since only one of them is adopted, the display quality deteriorates.

[Objective of the Invention] The present invention has been made in view of the above points, and provides a small television image reception device using a display panel in which the number of scanning side electrodes is smaller than the number of horizontal effective scanning lines in one field period. An object of the present invention is to provide an image display device capable of improving image quality and displaying a clear image in a machine.

[Key Points of the Invention] - The present invention 11.17''-/L/de period 0 horizontal 0 In a small television reception using a display panel in which the number of scanning side electrodes is smaller than the number of effective scanning lines, All or most of the information on the effective scanning line is used, and the display contents are switched between the first half and the second half of one backplate period.

[Embodiments of the Invention] A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of implementation in a 120×160 pixel liquid crystal television receiver. In the figure, reference numeral 1 converts a video signal sent from a video amplifying circuit (not shown) in front of the A/D converting circuit into 4-bit digital signals D1 to D4, and outputs the digital signals D1 to D4 to the control circuit 2. Further, 3 is a synchronization separation circuit which separates a horizontal synchronization signal and a vertical synchronization signal from the video signal sent from the video amplification circuit and outputs them to the control circuit 2. This control circuit 2 generates various timing signals shown in FIG. 3 according to the synchronization signal separated by the synchronization separation circuit 3, as will be described in detail later, and generates various timing signals shown in the segment side shift register 4 and the latch circuit 5.
, a gradation signal generation circuit 6, a segment-side analog multiplexer 7, a common-side shift register 8, and a common-side analog multiplexer 9. Shift register 5 above
has a configuration of 4 bits x 160 stages, and the 4-pit data D1 to D4 output from the control circuit 2 is processed by one clock pulse.
1 and output to the latch circuit 5. This latch circuit 5 has a configuration of 4 bits x 160 stages, reads input data in synchronization with the latch pulse tny from the control circuit 2, and outputs it to the gradation signal generation circuit 6. This gradation signal generation circuit 6 operates in synchronization with the timing signal Jny and timing signal Jc from the control circuit 2, and the latch circuit 5
A gradation signal is created according to the latch data of and output to the segment-side analog multiplexer 7. Further, the multiplexer 7 is supplied with the drive voltages Va, V2, 'V3, and ■5 from the liquid crystal drive voltage generation circuit 10, and is also supplied with the frame signal φF from the control circuit 2. The multiplexer 7 selects a liquid crystal drive voltage according to the grayscale signal and frame signal φF, and selects a liquid crystal drive voltage of 120X'160.
The segment electrodes of the liquid crystal display panel 11 of the pixels are driven for display.

On the other hand, the common side shift register 8 has a configuration of 1 bit x 120 stages, reads the timing signal r5x given from the control circuit 2 using the timing signal Jnx, and sequentially shifts it. And this common side shift register 8
The output of is sent to the common side analog multiplexer 9. Further, this multiplexer 9 receives liquid crystal driving voltages Va, Vs, V4 from the liquid crystal driving voltage generation circuit 10.
, Vs are supplied. The above liquid crystal drive voltage generation circuit 10
generates liquid crystal drive voltages from VO to ■5, supplies the drive voltages VD, V2, V3, and Vs to the multiplexer 7 as described above, and supplies the drive voltages VQ, Vt, V4, and Vs to the multiplexer 7.
s to the multiplexer 9. This multiplexer 9 drives the common electrode of the liquid crystal display panel 11 according to data from the shift register 8.

Next, details of the main parts of the control circuit 2 will be explained with reference to FIG. In the figure, 21 and 22 are timing circuits. The timing circuit 21 generates a basic clock pulse 1.12 based on the signal from the crystal oscillator 23.

Further, the timing circuit 22 generates reference clock pulses φh1 and φh2 based on the horizontal synchronizing signal φh and the vertical synchronizing signal φV from the sync separation circuit 3. The reference clock pulses φh1 and φh2 have twice the frequency of the horizontal synchronizing signal φh, and have a phase difference of 180 degrees. The clock pulse 1 outputted from the timing circuit 21 is input as a count clock to the hexadecimal counter 24, and the clock pulse 12 is input to the counter/decoder 25 as a count clock. Then, the output of the counter 24 is the flip 7
It is input to the set terminal S of the 0-tube 26, and the ζ output of this flip-flop 26 is output as the chip enable signal α. The counter 24 and flip 70 knob 26
is reset by the reference clock pulse φ old output from the timing circuit 22. Further, the output of the counter/decoder 25 is outputted via an inverter 27 as a timing signal 1c. This timing signal 1c corresponds to the timing signal 1ny outputted from the timing signal 1ny described above.
14 shots are output during each horizontal scanning period. Further, the reference clock pulse φold outputted from the timing circuit 22 is sequentially counted by a 525-base counter 28 and a binary counter 29, and outputted as a frame signal φF. Furthermore, the count contents of the counter 28 are sent to the decoder 30. This decoder 30 has a counter 2
When the count value of 8 reaches, for example, 27, a ``1'' signal is output.The decoded output is sent to the latch circuit 31, where the timing signal Cx is generated. In addition, the timing circuit 22
The reference clock pulse φh2 outputted from is inputted to the binary counter 32 and the quaternary counter 33 as a count pulse. The above binary counter 32 and quaternary counter 3
3 is reset by the output of the counter 28, and its output is inputted to the NAND circuits 34 and 35 together with the reference O-clock pulse φh1 outputted from the timing circuit 22. The output of the NAND circuit 34 is output as a timing signal Jny, and the output of the NAND circuit 35 is output as a timing signal Jnx. Also,
The output of the NAND circuit 34 is input as a reset signal to the counter/decoder 25 via the inverter 36. Further, the output of the NAND circuit 35 is input to the latch circuit 31 as an operation timing signal. This latch circuit 31 is constructed of an f flip-flop and a delay circuit, reads the output of the decoder 30 using a clock pulse 11, and transmits a timing signal fix synchronized with the vertical synchronization signal φ■ for approximately one backplate width. Output.

Next, the operation of the above embodiment will be explained. In the control circuit 2 shown in FIG. 2, the reference clock pulse φh2 outputted from the timing circuit 22 is counted by the binary counter 32, and the NAND circuit 34 is gate-controlled by the count output. As a result, the reference clock pulse φold is taken out one by one via the NAND circuit 34 and outputted as a timing signal Jny as shown in FIG. Also, the reference clock pulse φ output from the timing circuit 22
h2 is counted by a quaternary counter 33, and a NAND circuit 35 is gate-controlled by the count output. As a result, the reference clock pulse φ old is controlled in the NAND circuit 35 according to the output of the quaternary counter 33, and the timing signal ? Output as nx. Is this a timing signal?
nx is output at twice the cycle of the timing signal Jny, and one cycle corresponds to one backplate period. Further, the reference clock pulse φh1 outputted from the timing circuit 22 is outputted from the 525-base counter 28.
sent to. The 525-decimal counter 28 is reset in synchronization with the vertical synchronizing signal φV, and then starts counting in response to the reference clock pulse φh1. and,
The output of this counter 28 is counted by a binary counter 29 and output as a frame signal φF. Further, when the count value of the counter 28 reaches "27", the output of the decoder 30 becomes "1", and the clock pulse φ
1 is read into the latch circuit 31, and the timing signal f
Output as 5x. And this timing signal t
When 5x is output for approximately one backplate period, the latch circuit 31 is reset. On the other hand, the clock pulse φ1 outputted from the timing circuit 21 is counted by the hexadecimal counter 24, and the flip-flop 26 is set by the count output. This flip-flop 2C is then reset by the reference clock pulse φh2 output from the timing circuit 22, so the signal output from its Q output terminal becomes the chip enable signal α. This chip enable signal α is
As shown in FIG. 3, each horizontal period d1 of the video signal,
d2, . . .

At each output timing of the chip enable signal σ, 160 clock pulses φ1 are output from the timing circuit 21.

Further, the clock pulse φ2 outputted from the timing circuit 21 is counted by the counter/decoder 25. This counter/decoder 25 receives a clock pulse φ
Count 2, and 1111 every certain count? Output a signal. The output of this counter/decoder 25 is outputted as a timing signal IC via an inverter 27, and is outputted 14 times per horizontal period. As described above, various timing signals shown in FIG. 3 are outputted from the control circuit 2'.

Therefore, in FIG. 1, the timing signal 'f5x sent from the control circuit 2 to the common side shift register 8 is as follows.
As described above, it is output for a period of approximately one backplate in synchronization with the vertical synchronizing signal. This timing signal r5x is
The signals are read into the common side shift register 8 by the timing signal Jnx outputted from the control circuit 2 every backplate period, and are sequentially shifted within the shift register 8. Therefore, from the shift register 8, as shown in FIG.
, . . . are sequentially output and sent to the common side analog multiplexer 9. This multiplexer 9 outputs liquid crystal drive signals Vo, V according to signals from the shift register 8.
1, V4, and Vs are supplied to the liquid crystal display panel 11 to drive the common electrode. That is, the signal x1 corresponds to one backplate period a1, and the signal x2 corresponds to the next one backplate period a2. ..., each common electrode is selected in sequence.

Furthermore, the multiplexer 9 inverts the liquid crystal drive signal in synchronization with the frame signal φF.

On the other hand, the A/D conversion circuit 1 is operated by the chip enable signal α outputted from the control circuit 2, and converts the video signal sent from the video amplification circuit into three stages, each horizontal scanning period dl, as shown in the figure. d2, . . . and converts it into a 4-bit digital signal and outputs it to the control circuit 2. When data D1 to D4 are sent from the A/D conversion circuit 1, this control circuit 2 controls the data Dr to D4.
4 and a clock pulse 11 is sent to the segment side shift register 4. This shift register 4 is
11 Data D1 to D4 from circuit 2 are clock pulse z
Read sequentially in synchronization with 1. Then, when data is read into all digits of this shift register 4, a latch pulse Jny is outputted from the control circuit 2, and the data held in the shift register 4 is latched into the latch circuit 5, and the data is outputted to the gradation signal generation circuit. Sent to 6. The gradation signal generation circuit 6 generates a gradation signal by counting the clock IC according to the data from the latch circuit 5, and outputs it to the multiplexer 7. This multiplexer 7 generates liquid crystal drive signals Vo, V2, Vl, Vs according to the grayscale signal from the grayscale signal generation circuit 6.
is supplied to the liquid crystal display panel 11 to drive the segment electrodes for display. In this case, the multiplexer 7 outputs the liquid crystal drive signals Vo, V2, Vs in synchronization with the frame signal φF.
, Vs are inverted, and the liquid crystal display panel 11 is dynamically driven. As described above, a gradation signal is created according to the data output from the control circuit 2, and the liquid crystal display panel 11 is driven, but the latch pulse dny is output in the first half and the second half of one back plate period. , the data held in the shift register 4 is latched into the latch circuit 5. For example, as shown in FIG. 3, at the timing when the common electrode drive signal x 1 is output, the first half b1 is the video signal d held in the shift register 4 at that time.
1 is latched in the latch circuit 5 by the latch pulse Jny and sent to the grayscale signal generation circuit 6. A gradation signal is generated by the gradation signal generation circuit 6, and the liquid crystal display panel 11 is driven for display via the multiplexer 7. Further, in the first half b1 of the output timing of the common electrode' drive signal x1, the video signal d2 outputted from J, t and the control circuit 2 is written into the shift register 4. The data written in the shift register 4 is latched by the latch circuit 5 at the second half C1 of the output timing of the common electrode drive signal x1, and is sent to the gradation signal generation circuit 6. A gradation signal is generated by the gradation signal generation circuit 6, and the liquid crystal display panel 11 is driven for display via the multiplexer 7. As described above, the display data is switched in the first half and the second half C of one backplate period, and video signals for two horizontal scanning periods are displayed in one backplate period.

[Effects of the Invention] As detailed above, according to the present invention, in a small television receiver using a display panel in which the number of lines on the scanning bridge side is smaller than the number of effective scanning lines in one field period,
1 backplate period ago, l″!″I'4',! ″″c-ayrzP@@H
a, tlJ:5-ゞ01 - All or most of the information in the effective scan line can be used to display both adjacent video signals, even if they are quite different. It is possible to improve image quality and display clear images. Further, even if a video signal in a certain horizontal scanning period contains noise, it is not displayed as it is over one backplate period, and from this point of view as well, display quality can be improved.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a block diagram showing the circuit configuration, FIG. 2 is a diagram showing details of the control circuit in FIG. 1, and FIG. 3 is a diagram for explaining the operation. This is a timing chart. DESCRIPTION OF SYMBOLS 1...A/D conversion circuit, 2...Control circuit, 3...Synchronization separation circuit, 4...Segment side shift register, 5...
・Latch circuit, 6... Gradation signal generation circuit, 7... Segment side analog multiplexer, 8... Common side shift register, 9... Common side analog multiplexer, 10... Liquid crystal layer lll voltage generation Circuit, 11...
・Liquid crystal display panel, 21.22...timing circuit,
24... Hexadecimal counter, 25... Counter/decoder, 28... Counter, 29... Binary counter, 30... Decoder, 31... Latch circuit, 32...
... Binary counter, 33... Quaternary counter. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] In an image display device using a display panel in which the number of scanning-side electrodes is smaller than the number of effective horizontal scanning lines in one field period, one backplate period is set to a time width corresponding to two horizontal scanning lines. an A/D conversion circuit that samples the video signal in each horizontal scanning period and converts it into digital data of a predetermined number of bits;
An image display device characterized by comprising means for dividing data for each horizontal scanning line outputted from the A/D conversion circuit into the first half and the second half of the one backplate period and displaying them on the display panel, respectively.