JP2000315068A - Picture display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of picture omission generated during a picture switching by temporarily stopping the driving scanning by first and second scanning control means in the interval between immediately after an update and a supplying of new reference signals in a picture display device that conducts two picture display by video signals of two systems. SOLUTION: A picture switching control circuit 806 consists of a selection signal generating circuit 807, a 1/2 picture signal generating circuit 808 and a sampling control circuit 809. Video completion signals 1 and 2 generated by reference signal generating circuits 1 and 2 (717-1 and -2) are supplied to the circuits 808 and 809. Control signals 1 and 2 generated by a decoding circuit 804 are supplied to the circuits 807 and 809. The circuit 809 generates sampling signals 1 and 2 based on the control signals 1 and 2, the video completion signals 1 and 2 and selection signals 1 and 2 and supplies these signals to control signal obtaining circuits 1 and 2 (805-1 and -2).

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for sequentially sampling image signals input to a display screen having an aspect ratio of X: Y and displaying an image.

2. Description of the Related Art An image display device typified by a liquid crystal display device has a thin, lightweight, low power consumption characteristic, and is used as a display device of a personal computer or a word processor as a television or a car navigation system. Active matrix liquid crystal display devices, in which a switching element is electrically connected to each display pixel, are used in various fields as a display device and further as a projection type display device. It has been actively researched and
Development is taking place. In particular, in recent years, the display screen is shifting from a display screen having an aspect ratio of 3: 4 to a display screen extending in the horizontal scanning direction having an aspect ratio of 9:16 or the like in which a large screen is visually recognized. By the way, the aspect ratio 9:16
Liquid crystal display device with a display screen of
Conventionally, when a television signal having image information of 4 is displayed, the image is sequentially sampled and displayed based on a video signal on which image processing has been performed in advance by an image processing technique using a frame memory or the like. 1. Configuration of Conventional Image Display Device FIG. 9 is a schematic configuration diagram of a conventional image display device. (Input Processing Circuit 1) The input processing circuit 1 includes a demodulation circuit 103, a matrix circuit 104,
An A / D (analog / digital) conversion circuit 105 is provided. The video signals input through the input terminals 101 and 102 are converted into luminance signals Y1 and Y2 and color signals C1 and C2.
And synchronous signals S1 and S2 are demodulated by the demodulation circuit 103, and the luminance signal and the chrominance signal are demodulated by the matrix circuit 104 into three primary color signals R1, G1, B1 and R2, G2, B2. Then, the synchronization signals S1 and S2 and the video signal 1 and the video signal 2 obtained by converting the three primary color signals into digital data by the A / D conversion circuit 105 are supplied to the frame synchronization circuit 2 in FIG. (Frame Synchronization Circuit 2) The frame synchronization circuit 2 shown in FIG.
As shown in the figure, the control circuit 201 and the frame memory 202
It is composed of Control of writing and reading of the video signal 2 to and from the frame memory 202 is performed based on the synchronization signals S1 and S2 supplied to the control circuit 201, and the video signal 1 and the video signal 2 with the frame synchronization are converted into the data of FIG. It is supplied to the conversion circuit 3. (Data conversion circuit 3) The data conversion circuit 3 converts the data of the video signal 1 and the video signal 2 into data suitable for the screen display of the liquid crystal display device 7, and outputs the data to the image synthesis circuit 5. (Remaining area signal generating circuit 4) The remaining area signal generating circuit 4 is a circuit that generates a remaining area signal which is a signal in a period other than the effective display period of the image displayed on the liquid crystal display device 7. The image combining circuit 5 combines the image of the remaining area signal and the video signal input via the data conversion circuit 3, and outputs the combined image combined signal to the output circuit 6. (Output Circuit 6) The output circuit 6 performs a D / A (digital / analog) conversion process or the like, and supplies the liquid crystal display circuit 7 with the image composite signal. (Flat Display Apparatus 7) As shown in FIG. 12, the flat display apparatus 7 is electrically connected to the liquid crystal panel 701 and the liquid crystal panel 701 to sample a video signal to thereby apply a desired voltage to a signal line 705 of the liquid crystal panel 701. And a vertical scanning circuit 708 for supplying a scanning pulse to the scanning line 704 of the liquid crystal panel 701.
11 generates a common voltage (VCOM) whose level is inverted with respect to the reference voltage at each horizontal scanning period and each vertical scanning period by controlling the polarity inversion signal (POL) from the common electrode 11 and supplies it to the common electrode 706. The circuit 710 includes a circuit 710, a drive signal generation circuit 711, a video signal processing circuit 712 for performing video processing such as gamma correction to appropriately drive the liquid crystal panel 701, and a level inversion circuit 713. (Level Inverting Circuit 713) The level inverting circuit 713 converts the video signal supplied from the video signal processing circuit 712 to the level inversion of the common voltage (VCOM) by controlling the polarity inversion signal (POL) from the drive signal generation circuit 711. In synchronization, the level is inverted with respect to the reference voltage in the opposite phase and output to the horizontal scanning circuit 709. As a result, the polarity of the liquid crystal applied voltage is periodically inverted. (Liquid Crystal Panel 701) Although the liquid crystal panel 701 is not shown, the array substrate and the opposing substrate each hold a twisted nematic liquid crystal layer via an alignment film, and are held together by a sealant. In addition, a polarizing plate is disposed on the outer surface of each substrate so that its deflection axis is orthogonal. The array substrate has a plurality of data signal lines 70
5 and a plurality of scanning signal lines 704 are arranged so as to be substantially orthogonal. Each data signal line 705 and each scanning signal line 70
In the vicinity of the intersection with I.4, a switching element 703 composed of an inverted staggered thin film transistor (hereinafter abbreviated as TFT) using an amorphous silicon thin film for the active layer is used. T. O (Indim Tin O)
xide).
Although not shown, the array substrate has auxiliary capacitance lines Cj (j = 1, 2,...) Arranged substantially in parallel to the scanning signal lines 704 and having an area overlapping with the pixel electrodes 702.
..), And a storage capacitor (Cs) is formed by the pixel electrode and the storage capacitor line Cj. The counter substrate is not shown, but is used to shield each of a switching element 703 composed of a TFT formed on the array substrate, a gap between the data signal line 705 and the pixel electrode 702, and a gap between the scanning signal line 704 and the pixel electrode 702. A matrix-shaped light-shielding layer, red (R) disposed between the light-shielding layers to realize color display,
A color filter layer composed of three primary colors of green (G) and blue (B); T. O. Counter electrode 7 made of
06 is arranged. The TFT forming each switching element 703 includes a gate electrode connected to the scanning signal line 704, a drain electrode connected to the pixel electrode 702, and a source electrode connected to the data signal line. And
By the scan pulse supplied via the scan signal line 704, the source and drain electrodes become conductive, and the potential of the data signal line 705 set according to the data signal line is applied to the pixel electrode. The effective display area of the liquid crystal panel 701 includes a plurality of display pixels including a pixel electrode 702, a counter electrode 706, and a liquid crystal layer disposed between the pixel electrode 702 and the counter electrode, and the light transmittance of each display pixel. Is controlled by a potential difference between the pixel electrode 702 and the counter electrode 706. (Drive signal generation circuit 711) As described above, the drive signal generation circuit 711 of the liquid crystal panel 701 described above supplies the horizontal scan circuit 709 with the horizontal scan clock signal (CPH), the horizontal scan start signal (STH), and the signal to the display pixel. A write signal (CX) is supplied, and a vertical scanning clock signal (CPV) and a vertical scanning start signal (ST) are supplied to a vertical scanning circuit 704.
V) and a vertical scan inhibit signal (GOE). 2. Configuration of Data Conversion Circuit 3 FIG. 13 shows a configuration example of the data conversion circuit 3 and FIG. 14 shows a display mode of the liquid crystal display device 7. The configuration of FIG. 13 will be described in detail with reference to FIG. The data conversion circuit 3 includes 1H memory circuits 301, 302, 310 and a write control circuit 3
03, 311, read control circuits 304, 312, select circuits 305, 306, 307, 308 and a digital filter 309. A case where the display area of the liquid crystal panel 701 is displayed in a display mode having an aspect ratio of 9:16 as shown in FIG. Selection circuit 3
07 is a video signal 1 and a video signal 2 via the selection circuit 306.
Is supplied to the image synthesizing circuit 5. The video signal supplied in this way is the horizontal scanning period (1H) of 8
The aspect ratio is 9:16 with the 0% period as the effective display period.
14A, the display form of FIG. 14A is obtained. A case where the display area of the liquid crystal panel 701 is divided into an area A and an area B having an aspect ratio of 9: 8 as shown in FIG. 14B and a video signal is displayed in each area will be described. The write control circuit 303 transfers the two frame-synchronized video signals 1 and 2 supplied from the frame synchronization circuit 2 to the 1H memory circuits 301 and 302, respectively, based on the input synchronization signal S1 and clock signal. / 2 is controlled to be thinned out. The read control circuit 304 is controlled so as to read all data written in the 1 / 2H period based on the input synchronization signal S1 and clock signal.
The video signals read from the memory circuits 301 and 302 are selectively output through the selection circuit 305 to supply the time-division multiplexed video signals to the image synthesis circuit 5. The video signals supplied in this manner are horizontally scanned. Queries (1
H) is displayed on a screen having an aspect ratio of 9:16 with an effective display period of 80%, so that the video signal 1 and the video signal 2 or the video signal are respectively applied to the areas A and B in FIG. 2 and the video signal 1 can be displayed. Next, the display area of the liquid crystal panel 701 is changed as shown in FIG.
As shown in (d), a first display area A having an aspect ratio of 9:12 (3: 4) and a second display area B having an aspect ratio of 9: 4.
The case where the video signal is displayed in the area A and the remaining area signal is displayed in the area B will be described. The selection circuit 308 supplies one of the input video signal i and the video signal 2 to the digital filter 309. The digital filter 309 interpolates three data from the four data of the video signal supplied through the selection circuit 308 based on the interpolation operation control signal, the interpolation clock signal, and the clock signal supplied from the writing control circuit 311. Determined by processing 1
H memory circuit 310. Write control circuit 31
1 also controls the output signal of the digital filter 309 to be written into the 1H memory circuit 310 with an interpolation clock. The read control circuit 312 receives the synchronization signal S
1. Based on the clock signal, all data written by the interpolation clock is controlled to be read by the clock. The selection circuit 307 supplies the video signal supplied from the 1H memory circuit 310 to the image synthesis circuit 5. The image synthesizing circuit 5 sets a period of 80% of the horizontal scanning period (1H) of the video signal as an effective display period, and the video signal supplied from the data conversion circuit 3 subjected to the time axis compression processing during the effective display period x3 / 4. And the remaining area signal supplied from the remaining area signal generation circuit 4 during the remaining effective display period x1 / 4, and outputs the synthesized signal to the output processing circuit 6. Since the image of the effective display period is displayed on the screen having the aspect ratio of 9:16, FIG.
The video signal and the remaining area signal can be displayed in each of the area A and the area B in (d). 3.2 Description of Two-Screen Display FIG. 15 is a diagram illustrating a display form in the two-screen display. FIG. 15A is a diagram showing a display form in the two-screen display of FIG. 11B, and the displayed image is displayed such that a circle becomes a vertically long elliptical display as shown in the figure. FIG. 15B shows that the write control circuit 303 shown in FIG. 13 uses the frame synchronization circuit 2 based on the synchronization signal S1 and the clock signal.
The two video signals 1 and 2 which are frame-synchronized and are supplied to the 1H memory circuits 301 and 302, respectively, so that the number of data is halved and written to the 1H memory circuits 301 and 302. Out of all data written in 1 / 2H period based on the signal
3 or the write control circuit 303 converts the two frame-synchronized video signals 1 and 2 supplied from the frame synchronization circuit 2 based on the synchronization signal S1 and the clock signal into 1H memory circuits. Control is performed so that the number of data is thinned to 2/3 and written to 301 and 302, and the read control circuit 304 synchronous signal S
1. The method is performed by using any method of controlling to read out all data written in a 1 / 2H period based on a clock signal, and 2/3 is displayed in the horizontal direction of an image to be displayed. . For example, a screen having an aspect ratio of 9: 8 is displayed in which both sides of an image having an aspect ratio of 3: 4 are cut by 2/3 each. In this display, the circle becomes a circle as shown in the figure. FIG. 15C shows that the write control circuit 303 of FIG. 13 converts two frame-synchronized video signals 1 and 2 supplied from the frame synchronization circuit 2 based on the synchronization signal S1 and the clock signal to the 1H memory circuit 301, respectively. , 302 in such a manner that the number of data is reduced to １ ／, and the read control circuit 304 is controlled to read out all data written in the U / 2H period based on the synchronization signal S1 and the clock signal. 7 is performed by thinning-out scanning of the vertical scanning circuit 708 via the drive signal generating circuit 711 of FIG.

As described above, conventionally, a video signal having image information having different aspect ratios is displayed on a display screen having an aspect ratio of 9:16 or the like by an aspect ratio of 9: 1.
In order to display an image in an area with an aspect ratio of 9: 4, an area on the left and right sides of a display screen with an aspect ratio of 9: 8, and an area with an arbitrary aspect ratio, the data conversion circuit 3
In particular, the circuit configuration of the interpolation calculation control signal and the interpolation clock signal generation circuit of the write control circuit 311 and the digital filter 309 can be realized at low cost without increasing the circuit scale so as to correspond to an arbitrary aspect ratio. Did not.
In addition, since one of the video signals displayed on the left and right of the display panel is used as a main signal and the other video signal is read out from the memory to control the field or frame synchronization, the main signal is an unstable signal. In some cases, there has been a problem that images are not displayed stably. In particular, when a TV signal is received by a car navigation system, the TV signal may be a weak electric field.
When the V signal is used as the main signal, the image fluctuates in the horizontal direction, the screen freezes due to no vertical signal being detected, and the image fluctuates in the vertical direction due to erroneous detection of the vertical signal.
A signal such as map information generated by a car navigation system installed in the vehicle must always be used as a main signal. For this reason, only one system of the signal transmitted from outside the vehicle could be displayed. SUMMARY OF THE INVENTION It is an object of the present invention to prevent an image from being lost when switching between screens in an image display device that performs two-screen display using two video signals that are not synchronized.

According to a first aspect of the present invention, there are provided a plurality of display pixels arranged in a matrix at intersections of a plurality of scanning signal lines and a plurality of data signal lines. A display panel having a display area divided into (N ≧ 2), a vertical scanning circuit connected to the scanning signal lines, and N connected to data signal lines wired in the N divided display areas. Horizontal scanning circuits, N video signal processing means for obtaining N display signals to be displayed on the N display regions from N video signals asynchronous with each other or having different specifications, A vertical scanning clock signal, a vertical scanning start signal, and a vertical scanning clock signal to be supplied to the vertical scanning circuit and the N horizontal scanning circuits based on a synchronization signal obtained from the video signal and a display control signal input from the outside. N horizontal scans Lock signal, and a flat display device, characterized by comprising: a drive signal generating means for generating the N drive signals, such as N horizontal scanning start signal. According to a second aspect, a plurality of first scanning signal lines, a plurality of first data signal lines substantially orthogonal to the first scanning signal lines, and an intersection of each of the first scanning signal lines and the data signal lines A first display area including a first pixel electrode disposed in the vicinity via a switch element; a plurality of second scanning signal lines disposed along the first scanning signal line; 2
A plurality of second data signal lines substantially orthogonal to the scanning signal lines;
A second display area including a second pixel electrode disposed near a point of intersection of each of the second scanning signal lines and the data signal lines via a switching element; A first and a second vertical scanning circuit connected to the second scanning signal line, a first and a second video signal processing circuit connected to the first and the second data signal lines, and a driving signal generating means. The driving signal generating means outputs a first vertical control signal to the first vertical scanning circuit based on a first input video signal input from the outside, and outputs a first vertical control signal to the first video signal processing circuit. A first drive circuit unit that outputs a video signal and a first horizontal control signal; and a second drive circuit that is externally input and that is based on a second input video signal that is asynchronous or different in specifications from the first input video signal. Output the second vertical control signal and An image display device characterized by comprising a second driving circuit for outputting a second video signal and the second horizontal control signals to the second video signal processing circuit. Also, the present invention provides a display panel comprising: a plurality of display pixels arranged in a matrix at an intersection of a plurality of scanning signal lines and a plurality of data signal lines divided into two substantially at the center of the display panel; A vertical scanning circuit connected to each of the signal lines, and a horizontal scanning circuit for supplying a display signal to a plurality of data signal lines of the display pixels; and supplying a vertical scanning clock signal and a vertical scanning start signal to the vertical scanning circuit. Further, by supplying a horizontal scanning clock signal, a horizontal scanning start signal, and a video signal to the horizontal scanning circuit, an image obtained from two video signals that are not synchronized with the left and right sides of the display panel is displayed. In the flat display device, a vertical scanning clock signal, a vertical scanning start signal, and a horizontal scanning clock signal supplied to a first vertical scanning circuit and a first horizontal scanning circuit connected to the left pixel of the display panel. First scanning control means for generating a first driving signal such as a scanning clock signal and a horizontal scanning start signal; a second vertical scanning circuit and a second horizontal scanning circuit connected to the right pixel of the display panel; Vertical scanning clock signal to be supplied to
A second scan control unit for generating a second drive signal such as a vertical scan start signal, a horizontal scan clock signal, and a horizontal scan start signal; and supplying the second drive signal to the first horizontal scan circuit based on a first selection signal. A first video processing selection output unit for obtaining a first display signal to be generated from one of a first video signal and a second video signal, and supplying the first display signal to the second horizontal scanning circuit based on the second selection signal Second video processing selection output means for obtaining a second display signal to be generated from one of the first video signal and the second video signal, and a first video signal supplied from the first video processing selection output means A first clock signal which is a first reference signal synchronized with the synchronizing signal, a first video start signal indicating video start timing, and a first reference signal generating a first video end signal indicating video end timing Generation means and second video processing selection A second clock signal, which is a second reference signal synchronized with a synchronization signal of the second video signal supplied from the input means, a second video start signal indicating video start timing, and a second video signal indicating video end timing. A second reference signal generating means for generating an image end signal; a first selection signal for selecting one of the first image start signal and the second image start signal; and a first clock signal and a second clock signal. And a first signal selection unit that supplies a signal to the first scanning control unit as a first reference signal, the first video start signal and the second video start signal, and a first clock signal and a second clock signal. The second clock signal is selected based on the second selection signal, and is supplied to the second scanning control means as a second reference signal and is supplied to the second signal selection means and the first scanning control means. The first display control signal is transmitted to the first sun. A second control signal acquiring means for obtaining a second display control signal to be supplied to the first control signal obtaining means and the second scanning control means based on the ring signal based on the second sampling signal; Decoding means for obtaining a signal to be supplied to the first control signal obtaining means, the second control signal obtaining means and the screen switching control means from the displayed display control signal, and the first and the second signals based on the signal supplied from the decoding means. Selection signal generation means for generating a second selection signal; sampling control means for generating first and second sampling signals to be supplied to the first and second control signal acquisition means; first and second scanning controls The screen switching control means comprises a half screen signal generating means for generating a 1- / 2 screen signal indicating one screen display period to be supplied to the means. Further, according to the present invention, the selection signal generating means updates the first and second selection signals to new values after the drive scanning by the first and second scanning control means is completed, respectively, so that the first and second selection signals are updated. The image display device has a function of temporarily stopping the driving scan by the second scan control means immediately after the update and before a new reference signal is supplied. Further, the screen switching control from the two-screen display to the one-screen display composed of a single image by the first and second control signal obtaining means and the sampling control means of the present invention is performed by the two-screen display from the sampling control signal obtaining means. The data update of the display control signal supplied to the scanning control means, which is controlled to display any one screen display, is performed by changing the control signal supplied to the sampling control means from the timing at which the one screen display is not performed. The image display device is characterized in that the image display device is prohibited until the image data is supplied.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image table according to an embodiment of the present invention will be described.
The display device will be described with reference to the drawings. 1. First Embodiment of the Overall Configuration of the Image Display Apparatus 1
A block diagram showing a first embodiment of the image display device according to the present invention.
FIG. (Structure of the liquid crystal panel 701)
The substrate and the opposite substrate are twisted through the respective alignment films.
Holds the nematic liquid crystal layer and uses sialic material
Are held together. Also, on the outer surface of each board,
The polarizing plates are arranged so that their polarization axes are orthogonal to each other.
I have. The array substrate has a plurality of data signal lines 705 and a plurality of data signal lines.
Are arranged so as to be substantially orthogonal to the scanning signal lines 704.
You. Intersection between each data signal line 705 and each scanning signal line 704
Near the point, an amorphous silicon thin film is used for the active layer.
Inverted staggered thin film transistors (hereinafter referred to as T
Abbreviated as FT. ).
Via I. T. O (Indium Tin Oxid
The pixel electrode 702 of e) is arranged. array
The substrate is substantially parallel to the scanning signal line 704 and has an image.
Auxiliary container arranged so as to have an area overlapping with elementary electrode 702
Quantitative line Cj (j = 1, 2,...)
An auxiliary capacitance (Cs) is formed by the capacitance line Cj.
You. The opposing substrate is composed of TFTs formed on the array substrate.
Switching element 703, data signal line 705 and pixel
The gap between the electrode 702, the scanning signal line 704 and the pixel electrode 70
Matrix to shield each of the gaps with
Light-shielding layer, placed between light-shielding layers to realize color display
Red (R), green (G), and blue (B)
A color filter layer; T. O. From
Counter electrode 706 is disposed. Each switching element
The TFT constituting the element 703 is connected to the scanning signal line 704.
Gate electrode, drain connected to pixel electrode 702
Electrodes and source electrodes connected to the data signal lines.
No. Then, it is supplied via this scanning signal line 704.
The scanning signal makes the source and drain electrodes conductive, and the
Of the data signal line 705 set according to the data signal line.
Is applied to the pixel electrode. Effective display of liquid crystal panel 701
The region includes the pixel electrode 702, the counter electrode 706, and the
From the liquid crystal layer disposed between the pixel electrode 702 and the counter electrode
Composed of a plurality of display pixels,
The transmittance depends on the voltage between the pixel electrode 702 and the counter electrode 706.
It is controlled by the difference. (First Video Signal Processing Circuit 712-1) First Video Signal Processing
The circuit 712 is used for the image input through the terminal 101.
After demodulating the signal into three primary color signals R1, G1, B1,
Performs a comma process and supplies it to the first level inverting circuit 713-1
Drive signal generation circuit
711. (First Level Inverting Circuit 713-1) First Level Inverting Circuit
713-1 is supplied from the drive signal generation circuit 711
The first video signal is controlled by the control of the polarity inversion signal 1 (POL1).
Video signal supplied from the signal processing circuit 712-1
Voltage 1 VCOM1)
And the first SW circuit 714
-1 and the second SW circuit 714-2. (Second Video Signal Processing Circuit 712-2) Second Video Signal Processing
The circuit 712-2 outputs the video input through the terminal 102.
After demodulating the signal into three primary color signals R2, G2, B2,
Performs a comma process and supplies it to the second level inversion circuit 713-2.
And a driving signal generating circuit for synchronizing the video signal 1
711. (Second Level Inverting Circuit 713-2) Second Level Inverting Circuit
713-2 is supplied from the drive signal generation circuit 711
The second video signal is controlled by controlling the polarity inversion signal 2 (POL2).
Video signal supplied from the signal processing circuit 712-2
Synchronized with the level inversion of voltage 2 (VCOM2),
And the first SW circuit 714
-1 to the second SW circuit 714-2. (First SW circuit 714-1, Second SW circuit 714-2)
The first SW circuit 714-1 and the second SW circuit 714-2 are
First level inversion circuit 713-1 and second level inversion circuit 7
13-2, one of the video signals supplied from the
Selection by control signal supplied from signal generation circuit 711
And a first horizontal scanning circuit 709-U and a second horizontal scanning circuit, respectively.
Output to the inspection circuit 709-2. (First Common Voltage Generation Circuit 710-1) First Common Voltage
Generation circuit 710-1 is provided from drive signal generation circuit 711.
Each water is controlled by the control of the supplied polarity inversion signal 1 (POL1).
The level is compared with the reference potential in each of the horizontal scanning period and vertical scanning period.
To generate a common voltage 1 (VCOM1)
1 Supply to the counter electrode. (Second common voltage generation circuit 710-2) Second common voltage
Generation circuit 710-2 is provided from drive signal generation circuit 711.
Each water is controlled by the supplied polarity inversion signal 2 (POL2).
The level is compared with the reference potential in each of the horizontal scanning period and vertical scanning period.
To generate a common voltage 2 (VCOM2)
2 Supply to the counter electrode. (Drive signal generation circuit 711) Drive signal generation circuit 711
Are the screen display control circuit 715 and the first scanning control circuit 716
-1 and a second scanning control circuit 716-2. (Screen display control circuit 715) Screen display control circuit 715
Is supplied from the first video signal processing circuit 712-1.
1st H reference signal and 1st V reference signal
And supplied from the second video signal processing circuit 712-2.
From the synchronization signal 2, the second H reference signal and the second V reference signal
appear. And a screen display supplied from the terminal 100
Based on the control signal, the same or different H reference signal and V
The first scanning control circuit 716-1 is selected by selecting a reference signal.
It is supplied to the two-scan control circuit 716-2. Also, screen display
The control circuit 715 controls the screen display supplied from the terminal 100.
A screen display signal based on the control signal is supplied to the first scanning control circuit 716.
-1 to the second scan control circuit 716-2. (First Scan Control Circuit 716-1) First Scan Control Circuit 71
6-1 is the screen display signal, the H reference signal, and the V reference signal.
Scanning start signal (STH1), horizontal scanning
Clock signal (CPH1), write signal to display pixel
(CX1) and supplies it to the first horizontal scanning circuit 709-1.
And the vertical scanning clock signal (VCK1)
The direct scan start signal (STV1) and the vertical scan inhibit signal (G
OE11 to OE13) to generate the first vertical scanning circuit 708-
Feed to 1. (Second scanning control circuit 716-2) In the second scanning control circuit.
16-2 is the screen display signal, H reference signal, V reference
Horizontal scanning start signal (STH2), horizontal scanning
Clock signal (CPH2), write signal to display pixel
(CX2), and the second horizontal scanning circuit 709-2
And a vertical scanning clock signal (VCK2),
Vertical scan start signal (STV2) and vertical scan inhibit signal
(GOE21-23), and the second vertical scanning circuit 70
8-2. (First vertical scanning circuit 708-1, second vertical scanning circuit 70
8-2) First vertical scanning circuit 708-1 and second vertical scanning circuit
The path 708-2 is a scan divided substantially at the center of the display panel.
Driving operation for supplying a scanning signal to each of the signal lines 704
I do. The first vertical scanning circuit 708-1 and the second vertical scanning circuit
The scanning circuit 708-2 corresponds to the plurality of scanning signal lines 704,
The vertical scanning start signals 1 and 2 (STV1 and 2) are transmitted, respectively.
Multiple flip-flops connected in series to send
This shift having a shift register circuit composed of
The register circuit operates the vertical scanning clock signals 1,.
Vertical scanning start signals 1 and 2 (STV) in response to
1) and 2), and the vertical scanning start signals 1 and 2
Supports flip-flops that latch (STV1,2)
A scanning signal is output to the scanning signal line 704 to be scanned. Also before
The scanning signal is a vertical scanning inhibition signal (GOE11-13, GE
OE21 to GOE23) output to scanning signal line 704
You are limited in the period of time. (First horizontal scanning circuit 709-1, second horizontal scanning circuit 70
9-2) First horizontal scanning circuit 709-1 and second horizontal scanning circuit
The path 709-2 is a level-reversed video signal.
1 and 2 are sampled and held sequentially as data signals.
Of the scanning signal line 704 divided substantially at the center of the display panel.
A video signal is applied to each of a plurality of divided pixel electrodes 702.
To supply multiple data signals according to the data signal
A driving operation for driving the line 705 is performed. This first horizontal scan
The circuit 709-1 and the second horizontal scanning circuit 709-2 are respectively
And transmits horizontal scanning start signals 1 and 2 (STH1, 2).
Composed of multiple flip-flops connected in series
At least one shift register. Each
The horizontal register has horizontal scanning clock signals 1 and 2 (CPH).
In response to the horizontal scanning start signals 1 and 2 (STH
Perform the shift operation of (1), (2).
Tie for outputting flat scan start signals 1 and 2 (STH1, 2)
Sample and hold the video signal during
A data signal is applied to the data signal line 705 corresponding to the flop.
Supply. 2. FIG. 2 is a diagram showing a configuration example of the screen display control circuit 715.
You. FIG. 3 shows a first configuration example of the reference signal generation circuit 717.
FIG. 4 is a diagram showing a second example of the reference signal generation circuit 717.
It is a figure showing the example of composition. The present invention will be described with reference to FIGS.
The operation of the related screen display control circuit 711 will be described in detail.
You. The screen display control circuit 715 includes a first reference signal generation circuit
717-1, the second reference signal generation circuit 717-2, and the control circuit
It is constituted by a road 718. Also, the first reference signal generation time
Path 717-1 and the second reference signal generation circuit 717-2
Each has the configuration of FIG. 3 or FIG. (First Configuration Example of Reference Signal Generating Circuit 717) Reference of FIG.
The signal generation circuit 717 includes a PLL circuit 719 and a V synchronization detection.
Circuit 724, V counter 725, H reference signal generation circuit 7
26 and a V reference signal generation circuit 727.
The PLL circuit 719 includes a loop filter 720 and a voltage control generator.
Vibrator (VCO) 721 Phase comparison circuit 722, H counter
723. In the PLL circuit 719, the phase comparison
The circuit 722 is the same as that supplied from the video signal processing circuit 712.
Supplied from the H counter 723 and the horizontal synchronizing signal of the
Phase difference from the reference horizontal signal
Generates an error signal. The loop filter 720 has a phase
From the error signal obtained from the comparison circuit 722,
Generates a signal voltage from which noise has been removed. VC0721
Generates a reference clock signal based on the signal voltage
The reference clock signal is supplied to the H counter 723 and
V synchronization detection circuit 724, V counter 725, H
Reference signal generation circuit 726 and V reference signal generation circuit 727
And so on. The H counter 723 calculates the number of pixels for one row.
Count and a reference clock signal corresponding to this number of pixels.
Divides the frequency and supplies it to the phase comparison circuit 722 as a reference horizontal signal
I do. The H counter 723 requires each circuit block
A second reference horizontal signal having a frequency fH having a different phase,
The third reference horizontal signal having the frequency nxfH is supplied to the V counter 725.
And H reference signal generation circuit 726 and V reference signal generation circuit 7
27. The H reference signal generation circuit 726 is
Various horizontal drive control signals are generated based on the reference signals.
And generates an H reference signal as a reference for the control circuit 718.
Supply. The V synchronization signal detection circuit 724 performs video signal processing.
The vertical synchronizing signal is obtained from the synchronizing signal supplied from the circuit 712.
Detected and supplied to the V counter 725. V counter 72
5 is, for example, when the self-running cycle is the NTSC system,
Counter with a function of 525H / 2
Is done. The V counter 725 includes the H counter
723 to supply a reference horizontal signal of 2 × fH,
When the vertical synchronization signal is not supplied from the synchronization detection circuit 724,
In case of self-reset, self-run at 525H / 2 cycle
Operates as if the vertical sync signal is supplied.
Value to pull in phase based on the signal and the reference horizontal signal
Operate to be reset. The V counter is vertical
V reference signal generation circuit 7
27. The V reference signal generation circuit 727 is
Generates various vertical drive control signals based on quasi-vertical signals
A V reference signal which serves as a reference for
8 That is, the reference signal according to the configuration of FIG.
The generation circuit 717 detects the vertical synchronization signal by the V synchronization detection circuit 724.
Signal is input when the signal cannot be detected.
Can stably supply the V reference signal to the control circuit 71-8.
You. In this embodiment, the H reference signal generation circuit 726 and the V
The H reference signal and the V reference signal are converted by the reference signal generation circuit 727.
Generated from reference horizontal signal and reference vertical signal supplied respectively
However, the first scanning control circuit is controlled via the control circuit 715.
Signal supplied to the second scanning control circuit 716-1 and the second scanning control circuit 716-2.
The signal is a horizontal timing signal and a vertical timing signal.
If the signal is composed of the same kind of information,
Without using the raw circuit 726 and the V reference signal generation circuit 727,
The reference horizontal signal and the reference vertical signal are transmitted through the control circuit 715.
The first scanning control circuit 716-1 and the second scanning control circuit 7
It may be configured to directly supply 16-2. (Second Configuration Example of Reference Signal Generating Circuit 717) Reference of FIG.
The signal generation circuit 717 corresponds to the reference signal generation circuit 717 shown in FIG.
The vertical reference signal detected by the V synchronization detection circuit 724 of
The configuration is such that it is directly supplied to the V reference signal generation circuit 727.
Except for the above, the other configuration is the same. This configuration is
Signal is supplied to the reference signal generation circuit 717 stably.
Used and requires a smaller circuit scale than the configuration of FIG.
There is an advantage. (Control Circuit 718) The control circuit 718 performs three roles.
I'm sorry. The first role is a screen display signal, an H reference signal
And the V reference signal with the first scan control circuit 716-1 and the second scan control circuit 716-1.
Supply to the inspection control circuit 716-2. Also, the selected video
The signals are a first horizontal scanning circuit 709-1 and a second horizontal scanning circuit
709-2 to be supplied to the first SW circuit 714-1.
The second SW circuit 714-2 is controlled. The second role is
One level inversion circuit 713-1, second level inversion circuit 71
3-2, first common voltage generation circuit 710-1, second common
Supply a control signal to the power supply voltage generation circuit 710-2.
is there. These are output from the first video signal processing circuit 712-1.
Synchronized signal 1 supplied, second video signal processing circuit 712-
Synchronous signal 2 paid from 2 and image supplied from outside
It is controlled based on the surface display control signal. About the first role
I will explain it in more detail. In this role,
The control circuit 718 has four kinds of signals based on the image display control signal.
Perform the operation. Then, the first operation and the second operation are displayed on one screen.
Control, the third operation and the fourth operation are performed on two screens.
This is the control for display. In addition, about this display method
Will be described later in detail. (1) First Operation First Scan Control Circuit 716-1, Second Scan Control Circuit 716
-2 to the screen display signal of video signal 1, H reference signal and V base
Provides a quasi-signal. The video signal 1 is transmitted to the first horizontal scanning circuit 7
09-1 and the second horizontal scanning circuit 709-2.
The first SW circuit 714-1 and the second SW circuit 71
4-2 is controlled. (2) Second Operation First Scan Control Circuit 716-1, Second Scan Control Circuit 716
-2 is the screen display signal of video signal 2, H reference signal and V base
Provides a quasi-signal. The video signal 2 is transmitted to the first horizontal scanning circuit 7
09-1 and the second horizontal scanning circuit 709-2.
The first SW circuit 714-1 and the second SW circuit 71
4-2 is controlled. (3) Third Operation A screen display signal of the video signal 1 is sent to the first scanning control circuit 716-1.
Signal, an H reference signal and a V reference signal. Second scanning system
Screen display signal of video signal 2, H reference
Supply signal and ぴ V reference signal. Video signal 5 is the first horizontal
The video signal 2 is supplied so as to be supplied to the scanning circuit 709-1.
The first S is supplied to the second horizontal scanning circuit 709-2.
It controls the W circuit 714-1 and the second SW circuit 714-2.
You. (4) Fourth Operation A screen display signal of the video signal 2 is sent to the first scanning control circuit 716-1.
Signal, an H reference signal and a V reference signal. Second scanning system
Screen display signal of video signal 1, H reference
Supply signal and ぴ V reference signal. Video signal 2 is the first horizontal
The video signal 1 is supplied to the scanning circuit 709-1.
The first S is supplied to the second horizontal scanning circuit 709-2.
It controls the W circuit 714-1 and the second SW circuit 714-2.
You. 3.1 Description of One-Screen Display FIG. 5 is a diagram showing a display form in one-screen display. This
The description of the one-screen display will be described below. Single screen display
Is performed, the first video signal processing circuit 712-1 and
Are two input signals to the second video signal processing circuit 712-2.
One of the video signals is selected and the video signal is selected.
Only the screen reproduced from the issue is displayed. screen
The display control circuit 715 performs the above-described first operation or
This is a case where the second operation is performed. That is, screen display control
The circuit 715 is provided from the first video signal processing circuit 712-1.
The first H reference signal generated from the supplied synchronization signal 1 and the second
1 V reference signal and the second video signal processing circuit 712-2.
Second H reference signal generated from synchronization signal 2 supplied from
And one of the second V reference signals from terminal 100
Select based on the supplied screen display control signal and
Of the first scanning control circuit 716-
1 and the second scan control circuit 716-2. In addition,
The selected video signal is supplied to the first horizontal scanning circuit 709-1 and the second horizontal scanning circuit 709-1.
The first SW circuit is supplied to the flat scanning circuit 709-2.
714-1 and the second SW circuit 714-2. First
The scanning control circuit 716-1 controls the screen display control circuit 715.
Screen display signal supplied via the H reference signal, V reference
A horizontal scanning start signal (STH1) based on the
Scan clock signal (CPH1), writing to display pixels
The first horizontal scanning circuit 709-1 generates a signal (CX1).
And a vertical scanning clock signal (VCK).
1), vertical scanning start signal (STV1) and vertical scanning inhibition
Signal (GOE11-13) and a first vertical scanning circuit
708-1. Second scanning control circuit 716-2
Is a screen table supplied via the screen display control circuit 715.
Signal, the H reference signal, and the V reference signal.
Scan start signal (STH2), horizontal scan clock signal (CP
H2), generates a write signal (CX2) to the display pixel
And supplies it to the second horizontal scanning circuit 709-2.
Direct scan clock signal (VCK2), vertical scan start signal
(STV2) and a vertical scanning inhibition signal (GOE21-2)
3) is generated and supplied to the second vertical scanning circuit 708-2.
You. (First Display Example) FIG. 5A shows an image having an aspect ratio of 3: 4.
Image signal is directly displayed on a display panel with an aspect ratio of 9:16
It is a diagram showing a form to be displayed, the displayed image is a figure
As shown, the circle is displayed as a horizontal oval display
You. In this display, the first scanning control circuit 716-1 and
Either one of the second scan control circuits 716-2 is generated
Horizontal scanning start signal (STH1) or horizontal scanning start signal
(STH2) is a scan divided substantially at the center of the display panel.
A plurality of pixel electrodes 702 divided into two by a signal line 704
The video signal supplied to the
It is generated so that the sampling period becomes constant. Ma
In addition, the first scanning control circuit 716-1 and the second scanning control circuit 7
Horizontal scanning clock signal (CPH1) generated by 16-2
Alternatively, the horizontal scanning clock signal (CPH2) is the same signal.
Signal waveform or outside the period of sampling by the horizontal scanning circuit
Prohibit sampling by keeping the waveform unchanged
Is generated as a waveform. In addition, writing to display pixels
Signal (CX1) or a write signal (C
X2) is the horizontal scanning clock signal (CPH1) or
When the horizontal scanning clock signal (CPH2) is the same signal
In this case, the first horizontal scanning circuit 709-1 and the second scanning control circuit 7
09-2 finishes sampling and holding the video signal,
The sample-and-hold circuit then samples the video signal
At the same or different timing during the
Generated as a signal. Further, the horizontal scanning clock signal
Signal (CPH1) and horizontal scanning clock signal (CPH2)
Outside the period of sampling the video signal with each other, the waveforms
Use a waveform that inhibits sampling without changing
Sampled and held the video signal
Instead, the sample-and-hold circuit then outputs the video signal.
The signal of the timing within the period to start sample and hold and
Is generated. (Second display example) In FIG. 5B to FIG.
01 or a video signal 1 or
Or the video signal 2 is determined in advance by using the video signal and the display time of the remaining area.
It is supplied as a signal obtained by combining the remaining area signal with the video signal.
FIG. 5B shows that, for example, the first horizontal scanning circuit 709-1 is
The left side of the screen, the second horizontal scanning circuit 709-2 is the right side of the screen
Is displayed. First horizontal scanning circuit 709
-1 means that after sampling the remaining area signal,
The first half T1 of the display period (T) is sampled.
The second horizontal scanning circuit 709-2 is connected to the remaining second half 2: TT.
After sampling one period, the remaining area signal is sampled.
To (Third display example) FIG. 5C shows, for example, the first horizontal scanning.
The circuit 709-1 is located on the left side of the screen, the second horizontal scanning circuit 709.
-2 is a case where the image on the right side of the screen is displayed. First water
The flat scanning circuit 709-1 is used for the display period (T) of the video signal.
Sampling 2T / 3 period approximately equal to the first half T1
You. The second horizontal scanning circuit 709-2 outputs the remaining second half T2 =
After sampling the T-T1 period, the remaining area signal is sampled.
Pull. (Fourth Display Example) FIG. 5D shows, for example, the first horizontal scanning.
The circuit 709-1 is located on the left side of the screen, the second horizontal scanning circuit 709.
-2 is a case where the image on the right side of the screen is displayed. First water
The flat scanning circuit 709-1 samples the remaining area signal.
Is substantially equal to T1 in the first half of the display period (T) of the video signal
The 2T / 3 period is sampled. Second horizontal scanning circuit 7
09-2 sample the remaining second half 2 = TT1 period
To run. (Fifth display example) In the display mode of FIG.
The difference from the configuration of (a) is that the first scanning control circuit 716
-1 and the first scanning control signal from the second scanning control circuit 716-2.
The direct scanning circuit 708-1 and the second vertical scanning circuit 708-2
Supplied vertical scanning clock signal (VCK1), vertical scanning
Test start signal (STV1) and vertical scan inhibit signal (GOE)
11-13) and the vertical scanning clock signal (VCK2),
The direct scan start signal (STV2) and the vertical scan inhibit signal (G
OE21 to 23), 2 lines only once in 3 lines
Scans simultaneously and expands the image 4/3 times in the vertical direction
And display it. Therefore display
The resulting image has a 3: 4 aspect ratio as shown in the figure.
An image missing 0.75: 4 in total, up and down the image signal
Displayed on a liquid crystal panel 701 having an aspect ratio of 9:16.
You. 4.2 Explanation of display on screen FIG. 6 shows a display panel having an aspect ratio of 9:16.
The area is divided into two areas with a ratio of 9: 8, and
Display when displaying a video signal with a aspect ratio of 3: 4
It is a figure showing a form. FIGS. 6A to 6C show the first run.
Inspection control circuit 716-1 and second scanning control circuit 716-2
This shows a display mode when the same scanning control is performed.
You. The input video signals 1 and 2 are asynchronous signals with each other.
There are cases. The input video signals 1 and 2 are P
Specifications such as AL TV signal and NTSC TV signal
Or different signals. Screen display control circuit 71
5 performs the third operation or the fourth operation described above.
Is the case. (First Display Example) FIG. 6A shows, for example, a first horizontal scan.
The circuit 709-1 sends the video signal 11 to the left side of the screen,
Flat scan circuit 709-2 displays video signal 2 on the right side of the screen
Each half of the number of pixels in the horizontal direction.
Sampling during the effective display period of the video signal
Thus, a circle as shown in the figure is displayed in a vertically long oval display.
In this case, the video signal 1 and the video signal 2 are not
Synchronous, one without any special signal processing
Can display two screens. Ma
In addition, video signals 1 and 2 are PAL TV signal and NTS
The same applies to signals with different specifications, such as C-system TV signals.
It is like. This corresponds to each pixel electrode 70 of the liquid crystal panel 701.
2 can be displayed because they are electrically independent
And cannot be realized with a CRT display device.
The display method. The second and third display methods described below
The same applies to the display method and other display methods. (Second display example) FIG. 6B shows the sample of FIG.
When the sampling frequency is f, sampling is performed at a frequency of 3f / 2.
This shows the display mode when a ring is displayed.
Left and right of the image displayed with the aspect ratio of 2
The image with the missing 9: 4 aspect ratio image
It is displayed in each area. (Third display example) In the display form of FIG.
The difference from the configuration of (a) is that the first scanning control circuit 716-
1 and the second vertical scanning control circuit 716-2.
Scanning circuit 708-1 and the second vertical scanning circuit 708-2.
Supplied vertical scanning clock signal (VCK1), vertical scanning
A start signal (STV1) and a vertical scanning inhibit signal (GOE1)
1 to 13), the vertical scanning clock signal (VCK2),
The direct scan start signal (STV2) and the vertical scan inhibit signal (G
OE21 to 23), one line out of three lines
Performs thinning-out scanning and compresses the image 2/3 times in the vertical direction.
That is, it operates to display in a reduced size. In addition,
The remaining area signal synthesized outside the image signal sampling period is
Display of remaining area as shown in the figure by sampling
Is displayed on liquid crystal panel # 701. (Other Display Examples) FIGS. 6D to 6I show the first scanning control.
Control circuit 716-1 and second scanning control circuit 716-2
Shows the display form when different scanning control is performed.
Yes, the first scan control circuit 716-1 and the second scan control circuit
Each operation of 716-2 is performed in the case of FIGS.
The operation is omitted because it is the same as the case. 5. Second Embodiment of Overall Configuration of Image Display Device FIG. 7 shows an image display device according to a second embodiment of the present invention.
FIG. 7, the same configuration as in FIG. 1 is used.
Are given the same reference numerals. The common voltage generation circuit 710 is
A common voltage (VCOM) is generated and the first counter electrode and the second
Supply to counter electrode. In addition, this common voltage (VCO
M) is a first level inverting circuit 713-1 and a second level inverting circuit
It is also supplied to the circuit 713-2. First level inversion circuit 7
13-1 is a polarity inversion signal from the drive signal generation circuit 711;
Signal (POL), the first video signal processing circuit 71
The video signal supplied from 2-1 is converted to a common voltage (VCO
M) as a reference voltage, and level inversion with respect to this reference voltage
And outputs the result to the first SW circuit 714-1. 2nd level anti
The inverter circuit 713-2 also receives the pole from the drive signal generation circuit 711.
The second video signal processing is performed by controlling the sex reversal signal (POL).
The video signal supplied from the circuit 712-2 is converted to a common voltage
(VCOM) as a reference voltage.
The signal is inverted and output to the second SW circuit 714-2. this
As a result, the polarity of the liquid crystal applied voltage is periodically inverted. This
In the configuration of FIG. 1, unlike FIG.
The dynamic range of the image signal increases, but the counter electrode
You do not need to release them. Other configurations are the same as those in FIG.
Description is omitted. 6. Third Embodiment of Overall Configuration of Image Display Device FIG. 8 shows an image display device according to a third embodiment of the present invention.
FIG. 8, the same configuration as in FIG. 1 is used.
Is given the same symbol. 8 differs from the configuration of FIG.
The point will be described. Supplied to terminals 101 and 102
The video signal 1 and the video signal 2 are supplied to the first SW circuit 71, respectively.
4-1 and the second SW circuit 714-2. 1st S
The W circuit 714-1 and the second SW circuit 714-2 are connected to the
One of the image signals is supplied from the drive signal generation circuit 711
And the first video signal processing
Processing circuit 712-1 and the second video signal processing circuit 712-2.
Output. The first video signal processing circuit 712-1 includes a first S
The video signal supplied via the W circuit 714-1 is
After demodulation into color signals R1, G1, and B1, gamma processing is performed.
To the first level inverting circuit 713-1
Supply synchronization signal of video signal 1 to drive signal generation circuit 711
I do. The first level inversion circuit 713-1 generates a drive signal.
Polarity inversion signal 1 (POL1) supplied from the circuit 751
Control from the first video signal processing circuit 712-1.
The supplied video signal is leveled at a common voltage 1 (VCOM1).
Level inversion with respect to the reference voltage
And supplies it to the first horizontal scanning circuit 709-1. 2nd movie
The image signal processing circuit 712-2 includes a second SW circuit 714-2.
Are supplied to the three primary color signals R2, G
After demodulation to 2, B2, gamma processing is performed and the second level
The signal is supplied to the inverting circuit 713-2, and the
The period signal is supplied to the drive signal generation circuit 711. 2nd level
The inversion circuit 713-2 is provided from the drive signal generation circuit 711.
By controlling the supplied polarity inversion signal 2 (POL2),
The video signal supplied from the second video signal processing circuit 712-2
Signal is synchronized with the level inversion of the common voltage 2 (VCOM2).
The level is inverted with respect to the reference voltage in the opposite phase, and the second horizontal
The signal is supplied to the scanning circuit 709-2. The other configuration is the configuration of FIG.
Therefore, the description is omitted. 7. Modification of the present embodiment In the above embodiment, when there are two asynchronous signals to be input,
However, the present invention is not limited to this.
If you prepare four, you can respond to four signals, the screen display to four
Can be split. Furthermore, preparing a plurality of scanning line control circuits, etc.
Correspondingly increase the number of signals input asynchronously.
Can be made. 8. Example of application of the present embodiment As described above, according to the present embodiment, a two-screen display
An image display device can be provided at low cost. Sand
That is, the image displayed on the left and right of the display panel in the two-screen display
Even if one of the image signals is an unstable signal
It is not affected by the other label, so
If the other video signal is not a stable signal,
Because there is no need for a configuration that does not display stably,
It is possible to provide an inexpensive two-screen display device.
You. Therefore, in car navigation systems, etc.
Is the car navigation system installed in the car
Without constantly using signals such as map information generated in
It is possible to display the two signals that can be received
Was. Also, two video signals of different broadcasting systems are displayed in the same way.
Thus, an inexpensive image display signal can be provided. An example
For example, regions where PAL TV signals can be received, such as Europe
In NTS, NTS without using a signal processing circuit such as scanning line conversion
Of the car navigation system reproduced in the C system
It is possible to simultaneously display signals such as map information and TV broadcasts.
Wear. As another application example of this embodiment, T
V when applied to a flat screen display device with a large screen display such as
You. In other words, when displaying on one screen, the large screen
The display shown in FIG. 5 can be used. On the other hand, 2 strokes
When displaying on the screen, for example, different synchronization
You can easily display TV signals on channels that do not
Wear. Also, a flat screen with a large screen and many display pixels
If it is a device, it is not limited to two screens, but four screens and more
A screen may be displayed. FIG. 16 shows an image according to the present invention.
FIG. 4 is a block diagram showing one embodiment of a display method. Drive signal
The generation circuit 711 has a horizontal scanning circuit 1709-1 and a vertical scanning circuit.
A scanning control circuit for controlling driving scanning by the circuit 1708-1
Path 1716-1, horizontal scanning circuit 2709-2, and vertical scanning
Scan control circuit for controlling drive scan by the circuit 2708-2
Path 2716-2, video signal 1 and video signal 2
And the scanning control circuit 17
16-1, Screen list supplied to scanning control circuit 2716-2
And a display control circuit 715. Video signal processing circuit 1
712-1 is a video signal 1 input via the terminal 101
Is demodulated into three primary color signals R1, G1, and B1, and then gamma
Processing is performed to make the SW circuit 1714-1 and the SW circuit 2714
-2, and the synchronization signal of the video signal 1
To the screen display control circuit 715 of the signal generation circuit 711.
You. The video signal processing circuit 2712-2 is connected via a terminal 102.
The input video signal 2 is divided into three primary color signals R2, G2, B
After demodulation to 2, SW circuit 1714 performs gamma processing.
-1 and the SW circuit 2714-2, and
No. 1 synchronization signal on the screen display system of the drive signal generation circuit 711
It is supplied to the control circuit 715. SW circuit 1714-1 and SW
The circuit 2714-2 is provided separately from the screen display control circuit 715.
Based on the supplied selection signal 1 and selection signal 2,
Signal processing circuit 1712-1 and video signal processing circuit 2712-
2 Select one of the video signals supplied from
Output to the inverting circuit 1713-1 and the level inverting circuit 2 respectively.
Power. The level inverting circuit 1713-1 is a screen display control circuit.
By controlling the polarity inversion signal 1 supplied from the path 715,
Video signal supplied from SW circuit 1714-1 is common
Synchronized with the level inversion of voltage 1 (VCOM1),
The level is inverted with respect to the reference voltage by the horizontal scanning circuit 170.
9-1. The level inversion circuit 2713-2 is a screen
Control of the polarity inversion signal 2 supplied from the display control circuit 715
The video signal supplied from the SW circuit 2714-2 is controlled by the
Signal is synchronized with the level inversion of the common voltage 2 (VCOM2).
Horizontal scanning by inverting the level with respect to the reference voltage in the opposite phase.
The signal is supplied to a circuit 2709-2. Common voltage generation circuit 17
10-1 is the polarity supplied from the screen display control circuit 715
Each horizontal scanning period and vertical scanning period by controlling the inversion signal
Common voltage 1 whose level is inverted with respect to the reference potential every time
(VCOM1) is generated and supplied to the counter electrode 1. Como
The screen voltage control circuit 715
Horizontal scanning by controlling the polarity inversion signal 2 supplied from the
Level inversion with respect to the reference potential every period and vertical scanning period
To generate a common voltage 2 (VCOM2)
Feed to 2. The screen display control circuit 715 performs video signal processing.
From the synchronization signal 1 supplied from the circuit 1712-1 to the first
Clock signal, first reference H signal, and first reference V signal
And supplied from the video signal processing circuit 2712-2.
From the synchronization signal 2 to the second clock signal and the second reference H signal.
And a second reference V signal. And terminal 10
0 based on the screen display control signal supplied from
Or different clock signals, reference H signal and reference V signal
Select the scan control circuit 1716-1 and scan control circuit 27
Supplied as reference signal 1 and reference signal 2 to 16-2
I do. The screen display control circuit 715 is connected to the terminal 100 via the terminal 100.
Screen display control signal based on the supplied screen display control signal
Is generated, and the scan control circuit 1716-1 and the scan control circuit 2
716-2, the display control signal 1 and the display control signal 2, respectively.
Supply as The scanning control circuit 1716-1 is provided with the display
A horizontal scanning start signal based on the control signal 1 and the reference signal 1
(STH1), horizontal scanning clock signal (CPH1), table
A write signal (CX1) to the indicated pixel is generated and horizontal scanning is performed.
Circuit 1709-1 and a vertical scan clock
Signal (VCK1), vertical scanning start signal (STV1) and
Generates vertical scanning inhibit signals (GOE11-13) and outputs
It is supplied to the scanning circuit 1708-1. Scan control circuit 271
6-2 is based on the display control signal 2 and the reference signal 2,
Horizontal scanning start signal (STH2), horizontal scanning clock signal
(CPH2) and the write signal (CX2) to the display pixel
And supplies it to the horizontal scanning circuit 2709-2,
Vertical scan clock signal (VCK2), vertical scan start signal
(STV2) and a vertical scanning inhibition signal (GOE21-2)
3) is generated and supplied to the vertical scanning circuit 2708-2.
Vertical scanning circuit 1708-1 and vertical scanning circuit 2708-2
Denotes a scanning signal line divided substantially at the center of the display panel 701
704 to perform a driving operation for supplying a scanning signal to each of them.
U. The vertical scanning circuit 1708-1 and the vertical scanning circuit 27
08-2 corresponds to the plurality of scanning signal lines 704, and
For transmitting the vertical scanning start signals 1 and 2 (STV 1 and 2)
Composed of multiple flip-flops connected in series
Having a shift register circuit. This shift register
The circuit applies the vertical scanning clock signals 1 and 2 (CPV1, 2)
In response, the vertical scanning start signals 1 and 2 (STV 1 and 2)
The vertical scanning start signals 1 and 2 (STV1,
Scanning signal corresponding to flip-flop that latched 2)
A scan signal is output on line 704. The scanning signal is
Vertical scan inhibit signals (GOE11-13, GOE21-G
OE23) controls the period of outputting to the scanning signal line 704.
Limited. Horizontal scanning circuit 1709-1 and horizontal scanning circuit 2
709-2 are video signals 1 and 2 whose levels are inverted, respectively.
Are sequentially sampled and held as data signals, and the display panel
The scanning signal line 704 divided substantially at the center of the
Image signals to a plurality of pixel electrodes 702 divided into two.
Multiple data signals according to the data signal to supply
A driving operation for driving the signal line 705 is performed. This horizontal scanning cycle
The path 1709-1 and the horizontal scanning circuit 2709-2 are respectively
For transmitting the horizontal scanning start signals 1 and 2 (STH1, 2)
Composed of multiple flip-flops connected in series
At least one shift register. Each shift
The register has horizontal scanning clock signals 1 and 2 (CPH1,
2), the horizontal scanning start signals 1 and 2 (STH1,
Perform the shift operation of 2), and each flip-flop is horizontal.
Timing for outputting scan start signals 1 and 2 (STH1, 2)
Sample and hold the video signal with this flip-flop.
Data signal line 705 corresponding to the
Supply. FIG. 17 shows one configuration of the screen display control circuit 715.
FIG. 18 is a diagram showing an example, and FIG.
It is a figure showing an example of 1 composition. Screen display control circuit 1715
Are the same as the control circuit 718 and the PLL circuit 719 of FIG.
Period detection circuit 724, V counter 725, reference H signal generation
And a reference V signal generation circuit 727.
Reference signal generation circuit 1717-1 and reference signal generation circuit 2
717-2. The PLL circuit 719 is
Filter 720, voltage controlled oscillator (VCO) 721
It comprises a phase comparison circuit 722 and an H counter 723. P
In the LL circuit 719, the phase comparison circuit 722 controls the video signal processing.
Horizontal synchronization signal of the synchronization signal supplied from the logic circuit 712 and
Phase with reference horizontal signal supplied from H counter 723
The difference is detected, and an error signal corresponding to the phase difference is generated.
The loop filter 720 is obtained from the phase comparison circuit 722.
Signal voltage obtained by removing high frequency components and noise from the error signal
Occurs. The VCO 721 performs a clock based on the signal voltage.
A lock signal is generated, and this clock signal is
23, a control circuit 718, and a V synchronization detection circuit if necessary.
Path 724, V counter 725, reference H signal generation circuit 72
6 and the reference V signal generation circuit 727. H Cow
The counter 723 counts the number of pixels for one row, and this pixel number
Divides the clock signal in response to
It is supplied to the phase comparison circuit 722. H counter 723
Is the frequency f of different phases required by each circuit block.
The second reference horizontal signal of H1 and the third base of frequency n × fH
V counter 725 and reference H signal generation circuit 7
26 and the reference V signal generation circuit 727. Standard H
The signal generation circuit performs various horizontal driving based on the reference signal.
Generates a reference H signal that is used as a reference for generating control signals
Then, the data is supplied to the control circuit 718. V synchronization detection circuit 724
From the synchronization signal supplied from the video signal processing circuit 712
A vertical synchronization signal is detected and supplied to a V counter 725.
The V counter 725 has a self-running cycle of the NTSC system, for example.
In this case, it has the function of 525H / 2 of the field cycle.
It consists of two counters. This V counter 725 has
The H counter 723 supplies a 2 × fH reference horizontal signal.
And a vertical synchronization signal is supplied from the V synchronization detection circuit 724.
If not supplied, self-reset to 525H / 2
Operates in a self-propelled cycle and is supplied with a vertical synchronization signal
Phase based on the vertical sync signal and the reference horizontal signal.
The operation is performed so that the value is reset so that the value is read. In addition, V
The counter uses the reference vertical signal synchronized with the vertical synchronization signal as the reference V
The signal is supplied to the signal generation circuit 727. Reference V signal generation circuit 7
27, various vertical drive controls based on the reference vertical signal
Generating a reference V signal that is a reference for generating a signal;
It is supplied to the control circuit 718. That is, the configuration of FIG.
A reference signal generation circuit 717 is a V synchronization detection circuit 724.
Input a sync signal that cannot detect the vertical sync signal.
The reference V signal to the control circuit 718 in a stable manner
Can be paid. In this embodiment, the reference H signal generation circuit 726
And a reference H signal and a reference V signal in a reference V signal generation circuit 727.
Are the supplied reference horizontal signal and reference vertical signal, respectively.
From the reference H signal generation circuit 726.
Without using the quasi-V signal generation circuit 727, the reference horizontal signal
And a reference vertical signal via a control circuit 718 to a scanning control circuit.
1716-1 and the scan control circuit 2716-2.
May be adopted. FIG. 19 shows one configuration of the control circuit 718.
It is a figure showing an example. The control circuit 718 generates the POL1 signal
Circuit 801-1, POL2 signal generation circuit 801-2, S
W circuit 3802-1, SW circuit 4802-2, signal selection
Circuit 1803-1, signal selection circuit 2803-2, decoding
Circuit 804, control signal acquisition circuit 1805-1, control signal
Signal acquisition circuit 2805-2, screen switching control circuit 806
Be composed. The POL1 signal generation circuit 801-1 has a reference signal.
Of the signals supplied from the signal generation circuit 1717-1
At least a polarity inversion signal based on the reference H signal and the reference V signal
POL1 is generated, and SW circuit 3802-1 and SW circuit 4 are generated.
802-2. POL2 signal generation circuit 801-
2 is a signal supplied from the reference signal generation circuit 2717-2.
At least based on the reference H signal and the reference V signal.
Generates a sex inversion signal POL2,
It is supplied to the SW circuit 4802-2. SW circuit 3802-
1 displays either the polarity inversion signal POL1 or POL2 on the screen
Based on selection signal 1 supplied from switching control circuit 806
And a common voltage generation circuit 1 as the polarity inversion signal 1.
710-1 and supply it to the level inversion circuit 1713-1.
SW circuit 4802-2 has polarity inversion signals POL1 and POL.
2 is supplied from the screen switching control circuit 806.
Select based on selection signal 2 and copy as polarity inversion signal 2.
Mont voltage generation circuit 2710-2, level inversion circuit 271
3-2. The signal selection circuit 1803-1 turns off the screen.
Based on the selection signal 1 supplied from the conversion control circuit 806.
Selected reference signal generation circuit 1717-1 and reference signal generation
A clock signal supplied from one of the circuits 2717-2;
Scanning control using reference H signal and reference V signal as reference signal 1
The signal is supplied to the circuit 1716-1. Signal selection circuit 2803-
2 is a selection signal 2 supplied from the screen switching control circuit 806
The reference signal generation circuit 1717-1 selected based on
The clock supplied from one of the quasi-signal generation circuits 2717-2.
Signal, reference H signal and reference V signal are referred to as reference signal 2.
To the scan control circuit 2716-2. Decoding circuit
804 is a control signal acquisition circuit! Scan control via 805-1
Display control signal 1 to be supplied to the control circuit 1716-1,
Scan control circuit 271 via signal acquisition circuit 2805-2
The display control signal 2 to be supplied to 6-2 is supplied from the terminal 100.
From each screen display control signal
Control signal acquisition circuit 1805-1 and control signal acquisition circuit 280
5-2 is supplied as a mode signal. Also, selection signal 1
And a control signal that is switching information that is the basis of the selection signal 2.
1 and control signal 2 are supplied from terminal 100
The control signal is supplied to the screen switching control circuit 806.
FIG. 20 shows a specific configuration example of the screen switching control circuit 806.
FIG. The screen switching control circuit 806 controls the generation of the selection signal.
807-1 / 2 screen signal generation circuit 808, sampler
The configuration is made up of a power control circuit 809. Reference signal generation circuit 1
Of the first reference V signal generated in step 717-1
Indicates the timing when the display of No. 1 on the display panel ends
Video end signal 1 and generated by reference signal generation circuit 2717-2
The display panel of the video signal 2 of the generated second reference V signal
Video end signal 2 indicating the timing when display on the video ends
Is a selection signal generation circuit 807-1 / 2 screen signal generation circuit
808, supplied to the sampling control circuit 809. Ma
The control signal 1 generated by the decode circuit 804, the control
Signal 2 is selected signal generation circuit 807, sampling control
The signal is supplied to a circuit 809. The selection signal generation circuit 807
Control signal 1, control signal 2, video end signal 1, video end signal
2 to generate a selection signal 1 and a selection signal 2,
Signal 1 is sampled by 1/2 screen signal generation circuit 808
Control circuit 809, SW circuit 1714-1, SW circuit 38
02-1, the signal is supplied to the signal selection circuit 1803-1.
The selection signal 2 is supplied to the 1/2 screen signal generation circuit 808 and the sampler.
Control circuit 809, SW circuit 2714-2, SW circuit
4802-2, the signal is supplied to the signal selection circuit 2803-2.
The sampling control circuit controls the control signal 1, control signal 2, video
End signal 1, video end signal 2, selection signal 1, selection signal 2
Generates sampling signal 1 and sampling signal 2 based on
And each signal is sent to a control signal acquisition circuit 1805-1.
Is supplied to the control signal acquisition circuit 2805-2. 1/2 stroke
The surface signal generation circuit 808 selects the selection signal 1, the selection signal 2,
Display panel 70 based on end signal 1 and video end signal 2
1/2 screen signal which is a control signal for 1 screen display period to 1
Is generated, and the scan control circuit 1716-1 and the scan control circuit 2
716-2. Run with scan control circuit 1716-1
The inspection control circuit 2716-2 converts the supplied 1/2 screen signal
In the case of one screen display period, the horizontal scanning clock signal
The frequency of 1, 2 (CPH1, 2) is about 1 when displaying two screens.
/ 2, and a horizontal scanning circuit 1709-2
And images scanned by the horizontal scanning circuit 2709-2, respectively.
The horizontal scanning start signal is adjusted so that
Nos. 1 and 2 (STH1, 2) are generated with the phases shifted.
The control signal acquisition circuit 1805-1 is the screen switching control circuit 80
6 based on the sampling signal 1 supplied from
The decode signal supplied from the
Scanning control circuit 1716-1 as the display control signal 1.
To supply. The control signal acquisition circuit 28052 is a screen switching system.
Based on the sampling signal 2 supplied from the control circuit 806,
The decoding signal supplied from the decoding circuit 804
Sampling is performed and the scanning control circuit 2 is used as the display control signal 2.
716-2. 21 to 23 show the control circuit 71.
8 is a timing chart for explaining an operation example of FIG.
The operation of the present invention will be described in detail with reference to the drawings. In addition,
For simplicity, the two-screen display control period is controlled by the control signal 1
Control signal 2, select signal 1 and select signal 2 with different polarities
And the display panel 701 displays the video signal 1 and the video signal 2
The operation timing for displaying different images
You. The polarities of the control signal 1 and the control signal 2 shown by the solid line
The operation waveform when the polarity is opposite is indicated by the dotted waveform.
However, this operation is easier than the operation indicated by the solid line.
The explanation is omitted because it can be understood. In the figure, the video start signal
1. The video end signal 1 is a first signal indicating a video period of the video signal 1.
Is the vertical timing signal which is the reference V signal of
Signal 2 and video end signal 2 indicate the video period of video signal 2
This is a vertical timing signal serving as a second reference V signal. Ma
The first and second reference H signals, the first and second clock signals;
Although not shown, the first and second reference V signals are not shown.
Generated in synchronization with the issue. Screen switching system of control circuit 718
The selection signal generation circuit 807 forming the control circuit 806
Video end signal supplied from signal generation circuit 1717-1
1, when the control signal 1 is at the H level, the selection signal 1
When the control signal 2 is at the H level, the selection signal 2
And the reference signal generation circuit 27
Control signal by video end signal 2 supplied from 17-2
When 1 is at the L level, the selection signal 1
Level, set the selection signal 2 to L level.
To The SW circuit 1714-1 sets the selection signal 1 to the L level.
Output signal of the level inversion circuit 1713-1
At the H level, the level inversion circuit 2713-2
An operation is performed to select each output signal, and the SW circuit 27 operates.
14-2: level inversion when the selection signal 2 is at L level
When the output signal of the circuit 2714-2 is at the H level,
Output signals of the inverting circuits 1714-1 are selected.
Works as follows. Also, the SW circuit 3802-1 has a selection signal.
When 1 is at the L level, the POL1 signal generation circuit 801-
1 is the H level, the POL2 signal generation cycle
Operate to select each output signal of the path 801-2
When the selection signal 2 is at L level, the SW circuit 4
The output signal of the L2 signal generation circuit 801-2 is changed to an H level field.
In this case, the output signal of POL1 signal generation circuit 801-1 is applied to
Operate to select each. Further, the signal selection circuit 18
03-1 is a video start signal when the selection signal 1 is at the L level.
No. 1 and the video start signal 2 in the case of H level.
The signal selection circuit 2 operates so that the selection signal 2 is at L level.
In the case of a bell, the video start signal 2 is output.
An operation is performed to select each of the image start signals 1. FIG.
Switches from two-screen display to one-screen display with video signal 1.
Switching operation and switching from this one-screen display to two-screen display
FIG. 21 (1) is a timing chart showing the operation of
A period BC between the end signal 1 and the video end signal
The mode signal is composed of a video signal 1 from a two-screen display.
Switch to screen display, one screen display in next period bc
Timing when switching from 2 to 2 screen display
FIG. FIG. 21 (2) shows the image from the video end signal 2.
During the period AB, which is a question up to the image end signal 1, the mode signal is
Switching from two-screen display to one-screen display consisting of video signal 1
Then, in the next period ab, from one screen display to two screen display
FIG. 9 is an operation timing diagram when switching is performed. FIG.
The selection signal 1 of (1) is the L level control signal 1 and the time C,
Set to L level by the video signal 2 of E, c, e
You. The selection signal 2 is the control signal 2 at the H level and the time B.
Is set to H level by the video end signal 2 of
Level control signal and video end signal 2 at time C, E, c
Is set to a lower level, and furthermore, a control signal of an H level is set.
2 and set to H level by video signal 1 at time d
You. The signal selection circuit 1803-1 is a low-level selection signal.
Scan control based on 1 using video start signal 1 as reference signal 1
Circuit 1716-1, and the signal selection circuit 2
The video start signal 2 is referred to as the reference signal 2 based on the selection signal 2.
And operates to supply it to the scan control circuit 2716-2.
You. Also, the control signal acquisition circuit 1805-1 and the control signal acquisition circuit
The obtaining circuit 2805-2 is provided from the sampling control circuit 809.
Sampling signal 1 and sampling supplied respectively
The mode supplied from the decoding circuit 804 based on the signal 2
The scan control circuit 1716-1
And the scan control circuit 2716-2 respectively.
Is supplied as the display control signal 2. This sampling system
The sampling signal generated by the control circuit 809 is a selection signal.
1 and the selection signal 2, the sampling signal 1
The same timing as the video end signal 1
The pulling signal 2 is the video end signal 1 in the period Cd,
In the other period, the timing is the same as that of the video end signal 2.
You. Therefore, the scan control circuit 1716-1 outputs the image at the time D.
Until the end signal 1, the image of the video signal 1 is displayed in the two-screen display operation.
It operates so that it is displayed as one side, and after the period D,
Display control signals 1, 1 supplied at the timing of interval D
/ 2 screen signal, image of video signal 1 based on reference signal 1
Is displayed on one screen. And after time d
Is a display control signal supplied at the timing of time d.
1, 1/2 screen signal, video signal 1 based on reference signal 1
To display the image as one of the two screen display operations
I do. On the other hand, the scanning control circuit 2716-2 outputs the image at time C.
In the period T2 until the end signal 2, two images of the video signal 2 are displayed.
It operates to display as the other of the display operation, and
Immediately after video end signal 2, switch from H level to L level
The scanning is temporarily stopped by the obtained selection signal 2.
After that, the table supplied at the timing of time D
Display control signal 2, 1/2 screen signal, reference signal 2
It operates to display the image of the video signal 1 on one screen. time
After d, is the L level immediately after the video end signal 1 at time d?
Scanning is performed by the selection signal 2 switched to the H level from
After a temporary stop, at time e
Display control signal supplied from 2, 1/2 screen signal, reference
The image of the video signal 2 is displayed based on the signal 2 in the two-screen display operation.
It operates to display on the other side. Selection of Fig. 21 (2)
The selection signal 1 is an L-level control signal 1 and an image of time C, a, c.
Set to L level by image signal 2. Also, select
No. 2 is an H level control signal and a video end signal 2 at time B.
After being set to the H level, the control signal 2 of the L level
And set to L level by video end signal 2 at time C and a
And the H-level control signal 2 and the video signal at time b.
Set to H level by 1 Sampling control times
The sampling signal 1 generated in the path 809 is a control signal
End of video immediately after both 1 and control signal 2 go to L level
Prohibit signal 1 from becoming sampling signal 1.
Is the same as the video end signal 1 except for the period AB.
And the sampling signal 2 is projected in the period Cb.
Image end signal 1; same as image end signal 2 in other periods
This is one timing. Therefore, the scan control circuit 1716
-1 is the image of the video signal 1 until the video end signal 1 at time D
Is displayed as one of the two screen display operations.
In addition, after the period D, it is supplied at the timing of the time D.
Based on display control signal 1, 1/2 screen signal, reference signal 1
To display the image of the video signal 1 on one screen. So
Then, after time b, power is supplied at the timing of time b.
Display control signal 1, 1/2 screen signal, reference signal 1
The image of video signal 1 as one of the two screen display operations
Operate to display. On the other hand, the scanning control circuit 2716-
2 is a time T2 until a video end signal 2 at time C is a video signal
To display the second image as the other of the two-screen display operation
It operates, and immediately after the video end signal 2 at the time C, it changes from the H level.
The scanning is temporarily performed by the selection signal 2 switched to the L level.
After a temporary stop, the time D
Display control signal 2, 1/2 screen signal, reference signal
No. 2 to display the image of the video signal 1 on one screen
Operate. After time b, the video end signal 1 at time b is
After that, the selection signal 2 is switched from the L level to the H level.
After the scanning is temporarily stopped by the
Display control signal 2, 1/2 supplied at the timing of
The image of the video signal 2 is changed to 2 based on the screen signal and the reference signal 2.
An operation is performed to perform display as the other of the screen display operations. Figure
22 is a transition from the two-screen display to the one-screen display by the video signal 1
Switching operation and switching from single-screen display to dual-screen display
FIG. 22A is a timing chart showing the switching operation, and FIG.
Video end signal! Period B from the time until the video end signal
In C, the mode signal consists of the video signal 2 from the two-screen display
Switching to single screen display, one screen display in next period bc
Operation when switching from two-screen display to two-screen display
FIG. FIG. 21 (2) shows the video end signal 2
During a period AB which is a period until the video end signal 1, the mode signal
Switches from a two-screen display to a one-screen display consisting of video signal 2.
In other words, from one screen display to two screen display in the next period ab
FIG. 7 is an operation timing chart when the switching is made to the operation mode. FIG.
2 (1) selection signal 1 is H level control signal 1 and time
After being set to the H level by the video signal 1 of D and b,
L level control signal 1 and time C, e video end signal 2
It is set to L level. The selection signal 2 is at H level.
Bell control signal 2 and time B, D, b, d video end signals
Set to H level by 1 Signal selection circuit 180
3-1 is a video start signal based on the L-level selection signal 1
1 is supplied to the scan control circuit 1716-1 as the reference signal 1
Then, the signal selection circuit 2 is based on the selection signal 2 having the H level.
Scan control circuit 271 using video start signal 2 as reference signal 2
6-2. Sampling control circuit
The sampling signal 1 generated at 809 is the period Dc
Is the video end signal 2, and the video end signal 1 in other periods
And the sampling signal 2 is controlled
Video immediately after signal 1 and control signal 2 both have H level
Prohibit end signal 2 from becoming sampling signal 2
As a result, the same as the video end signal 2 except for the period BC
Timing. Therefore, the scanning control circuit 1716-
1 is a time T1 until a video end signal 1 at time D is a video signal
Display one image as one of two screen display operations
Operates, and immediately after the video end signal 1 at the time D, the L level is applied.
The scanning is temporarily performed by the selection signal 1 switched to the H level.
After a temporary stop, the timing of time E
Display control signal 1, 1/2 screen signal, reference signal
No. 1 to display the image of the video signal 2 on one screen
Operate. After time c, the video end signal 2 at time c
After that, the selection signal 1 is switched from the H level to the L level.
After the scanning is temporarily stopped by the
Display control signal 1, 1/2 supplied at the timing of
The image of the video signal 1 is changed to 2 based on the screen signal and the reference signal 1.
It operates to display as one of the screen display operations. one
On the other hand, the scanning control circuit 2716-2 outputs a video end signal at time E.
Up to 2, the image of video signal 2 is used as the other of the two-screen display operation.
The time E is displayed after the period E.
Display control signal supplied by imaging, 1/2 screen
One screen of the image of the video signal 2 based on the signal and the reference signal 2
Operate to display. And time. After that time.
Display control signal 2, 1/2 supplied at the timing of
The image of the video signal 2 is changed to 2 based on the screen signal and the reference signal 2.
It operates to display the other of the screen display operations. FIG.
2 (2) selection signal 1 is H level control signal 1 and time
Set to H level by video signal 1 of B, d, b
Later, L level control signal 1 and time. Video end signal 2
It is set to L level. The selection signal 2 is at H level.
Bell control signal 2 and time B, D, b, d video end signals
2 sets it to the H level. Sampling control times
The sampling signal 1 generated in the path 809 has a period Bc
Then, the video end signal 2, otherwise, the video end signal
1 and the sampling signal 2
The timing is the same as the video end signal 2 during the period. Follow
Then, the scanning control circuit 1716-1 outputs the video end signal at time B.
In the period T1 up to 1, the image of the video signal 1 is displayed on two screens.
Of the image at time B
Immediately after the signal 1, the level was switched from the L level to the H level.
Scanning was temporarily stopped by selection signal 1.
Thereafter, the display control signal supplied at the timing of time c
1, 1/2 screen signal, video signal 2 based on reference signal 1
Is operated to display one image on one screen. After time c
Immediately after the video end signal 2 at the time c, the H level changes to the L level.
Scanning is temporarily stopped by the selection signal 1 switched to
After that, the power is supplied at the timing of time d.
Display control signal 1, 1/2 screen signal, reference signal 1
The image of video signal 1 as one of the two screen display operations
Operate to display. On the other hand, the scanning control circuit 2716
-2 is the image of the video signal 2 until the video end signal 2 at time C
Is displayed as the other of the two-screen display operation.
In addition, after the period C, it is supplied at the timing of the time C.
Based on display control signal 2, 1/2 screen signal, reference signal 2
To display the image of the video signal 2 on one screen. So
And time. After that time. Supplied by the timing of
Display control signal 2, 1/2 screen signal, reference signal 2
The image of video signal 2 as the other of the two-screen display operation
Operate to display. FIG. 23 shows the left side of the two-screen display.
It is a timing chart which shows the operation | movement which replaces a right image.
The selection signal 1 in FIG. 23A is the same as the control signal 1 at the L level.
After being set to L level by the image signal 2, the H level
Set to H level by control signal 1 and video end signal 1.
It is. Also, the selection signal 2 is the control signal 2 of H level and the video signal.
After being set to the H level by the end signal 1, the L level
Set to L level by control signal 2 and video end signal 2
Is done. Samples generated by the sampling control circuit 809
The pulling signal 1 is a video end signal while the selection signal 1 is at the L level.
Signal 1 and the same as video end signal 2 in other periods.
Timing, and the sampling signal 2
H-level period is video end signal 2, otherwise
The timing is the same as that of the video end signal 1. Therefore, run
The inspection control circuit 1716-1 controls the image of the video signal 1 during the period T1.
Operation to display an image as one of two screen display operations
Then, the scanning in the period T4 is temporarily performed by the change of the selection signal 1.
After being in a stopped state, in a period T2 following the period T4,
Display control supplied by timing of video end signal 2
Two images of video signal 2 are generated based on signal 1 and reference signal 1.
An operation is performed to perform display as one of the surface display operations. one
On the other hand, the scanning control circuit 2716-2 outputs the video signal in the period T2.
To display the second image as the other of the two-screen display operation
It operates and temporarily scans the period T3 by the change of the selection signal 2.
Period T1 following the period T3 after being temporarily stopped
In the display supplied by the timing of the video end signal 1
An image of the video signal 1 is generated based on the control signal 2 and the reference signal 2.
An operation is performed so as to display as the other of the two-screen display operation. Figure
The selection signal 1 of 23 (2) is an L level control signal 1 and a video signal.
After being set to L level by signal 2, control of H level
Set to H level by control signal 1 and video end signal 1.
You. In addition, the selection signal 2 is the control signal 2 at the H level and the video end.
After being set to H level by the end signal 1,
Set to L level by control signal 2 and video end signal 2.
It is. Sample generated by sampling control circuit 809
Ring signal 1 ends video while selection signal 1 is at L level
Signal 1 and the same timer as video end signal 2 in other periods
And the sampling signal 2 is H
During the level period, the video end signal 2 is displayed.
The timing is the same as that of the image end signal 1. Therefore, scanning
The control circuit 1716-1 controls the image of the video signal 1 in the period T1.
To display as one of the two-screen display operation,
The scanning in the period T4 is temporarily stopped by the change of the selection signal 1.
In the period T2 following the period T4,
Display control signal supplied at the timing of the end signal 2
1 screen and 2 screen images of video signal 2 based on reference signal 1
The display operation is performed as one of the display operations. Meanwhile, running
The inspection control circuit 2716-2 outputs the image of the video signal 2 in the period T2.
Operation to display an image as the other of the two-screen display operation
Then, the scanning of the period T3 is temporarily stopped by the change of the selection signal 2.
After being in a stopped state, in a period T1 following the period T3,
Display control supplied by timing of video end signal 1
Two images of video signal 1 are generated based on signal 2 and reference signal 2.
It operates to display as the other of the surface display operations. FIG.
Is a block diagram showing another embodiment of the image display device of the present invention.
FIG. In FIG. 24, the same configuration as that of FIG.
Are denoted by the same reference numerals, and description thereof is omitted. Video signal processing
The circuit 1712-1 outputs the image input through the terminal 101.
After demodulating signal 1 into three primary color signals R1, G1, B1,
Performs gamma processing and supplies it to the level inversion circuit 1713-1
And a driving signal generating circuit for synchronizing the video signal 1
711 is supplied to the screen display control circuit 715. Video signal
The processing circuit 2712-2 is input via the terminal 102.
Video signal 2 is demodulated into three primary color signals R2, G2, B2
Thereafter, gamma processing is performed and the result is output to the level inversion circuit 2713-2.
Supply and generate drive signal for synchronization signal of video signal 1
It is supplied to the screen display control circuit 715 of the circuit 711. Lebe
The inversion circuit 1713-1 is provided from the screen display control circuit 715.
The video signal is controlled by the supplied polarity inversion signal POL1.
The video signal supplied from the signal processing circuit 1712-1.
In synchronization with the level inversion of the input voltage 1 (VCOM1)
SW circuit 1714 inverts the level with respect to the reference voltage in the phase
-1 and the SW circuit 2714-2. Level inversion times
The path 2713-2 is supplied from the screen display control circuit 715.
The video signal processing circuit is controlled by the polarity inversion signal POL2.
The video signal supplied from the path 2712-2 to the common voltage 2
Synchronous with the level inversion of (VCOM2)
The level is inverted with respect to the voltage, and the SW circuit 1714-1 and S
It is supplied to the W circuit 2714-2. SW circuit 1714-1
And the SW circuit 2714-2 from the screen display control circuit 715
Based on the selection signals 1 and 2 supplied respectively,
Level inversion circuit 1713-1 and level inversion circuit 2713
-2 to select one of the video signals supplied from
The scanning circuit 1709-1 and the horizontal scanning circuit 2709-2
Output each. The screen display control circuit 715 is shown in FIG.
As described above, the reference signal generation circuit 1717-1, the reference signal generation
It comprises a circuit 2717-2 and a control circuit 718.
FIG. 25 is a screen display control circuit 71 of the image display device of FIG.
5 is a diagram illustrating a configuration example of a control circuit 718 included in the control circuit 5;
The same components as those in FIG. 19 are denoted by the same reference numerals. Figure
25 differs from the configuration of FIG.
14-1 and the output from the SW circuit 2714-2.
Instead of the polarity inversion signal 1 and the polarity inversion signal 2,
Signal generation circuit 801-1 and POL2 signal generation circuit 801
-2, the polarity inversion signal POL1 output from
The polarity inversion signal POL2 is connected to the level inversion circuit 1713-1.
Configurations supplied to the bell inverting circuit 2713-2, respectively.
The other configuration is the same as that of FIG.
Therefore, the description is omitted. As described above, according to the present invention,
One-screen display is also possible, and
Even if multiple signals or multiple signals with different specifications are input, multiple
Screen display is possible, and this image display device
Price can be provided.

As described above, according to the image display device of the present invention, an image display device for displaying an image obtained from two video signals that are not synchronized with the left and right of the display panel is provided at low cost. I can do it. Further, even if one of the video signals displayed on the left and right sides of the display panel in the two-screen display is an unstable signal, it is not affected by the other display. The problem that the image is not displayed stably unless the video signal is a stable signal is eliminated. Therefore, a car navigation system or the like can display two types of signals that can be received without constantly using signals such as map information generated by the car navigation system installed in the vehicle. Was. Further, it is possible to provide an inexpensive image display device that simultaneously displays two video signals having different broadcasting systems. For example, in an area such as Europe where a PAL system TV signal can be received, a signal such as map information of a car navigation system reproduced by the NTSC system and a TV broadcast are used without using a signal processing circuit such as a scanning line conversion. Can be displayed at the same time. Further, when switching from displaying two unsynchronized video signals on the left and right sides of the display panel to displaying only one of the video signals, only one of the left and right images on the display panel is displayed in half. Thus, the problem caused by the two systems of video signals being not synchronized can be solved.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an image display device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a screen display control circuit of the image display device of FIG. 1;

FIG. 3 is a diagram illustrating a first configuration example of the reference signal generation circuit of FIG. 2;

FIG. 4 is a diagram illustrating a second configuration example of the reference signal generation circuit of FIG. 2;

FIG. 5 is a diagram showing a display mode in one-screen display of the image display device of FIG. 1;

FIG. 6 is a diagram showing a display mode in a two-screen display of the image display device of FIG. 1;

FIG. 7 is a diagram showing a second embodiment of the image display device of FIG. 1;

FIG. 8 is a diagram showing a third embodiment of the image display device of FIG. 1;

FIG. 9 is a schematic configuration diagram of a conventional image display device.

10 is a schematic configuration diagram of an input processing circuit of the image display device of FIG.

11 is a schematic configuration diagram of a frame synchronization circuit of the image display device of FIG.

12 is a schematic configuration diagram of a liquid crystal display device of the image display device of FIG.

13 is a schematic configuration diagram of a data conversion circuit of the image display device of FIG.

FIG. 14 is a diagram showing one display mode of the image display device of FIG. 9;

FIG. 15 is a diagram showing a display mode in a two-screen display of the image display device in FIG. 9;

FIG. 16 is a schematic configuration diagram of an image display device according to an embodiment of the present invention.

FIG. 17 is a diagram illustrating a configuration example of a screen display control circuit of the image display device in FIG. 16;

FIG. 18 is a diagram showing one configuration example of a reference signal generation circuit of FIG. 17;

FIG. 19 is a diagram illustrating an example of a configuration of a control circuit in FIG. 17;

FIG. 20 is a diagram showing one configuration example of a screen switching control circuit of FIG. 19;

FIG. 21 is a timing chart showing the switching operation of the control circuit of FIG. 19 from the two-screen display to the one-screen display by the video signal 1, and the switching operation from the one-screen display to the two-screen display.

FIG. 22 is a timing chart showing the switching operation of the control circuit of FIG. 19 from the two-screen display to the one-screen display by the video signal 2, and the switching operation from the one-screen display to the two-screen display.

FIG. 23 is a timing chart showing the operation of the control circuit of FIG. 19 for switching the left and right images in a two-screen display.

FIG. 24 is a block diagram showing another embodiment of the image display device of the present invention.

FIG. 25 is a diagram showing a configuration example of a control circuit 718 forming a screen display control circuit 715 of the image display device of FIG. 24;

[Explanation of symbols]

 7 Liquid crystal display device 701 Display panel 702 Pixel electrode 703 Switching element 704 Scan signal line 705 Data signal line 706 Counter electrode 708, 708-1, 708-2 Vertical scanning circuit 709, 709-1, 709-2 horizontal scanning circuit 710, 710-1, 710-2 common voltage generation circuit 711 drive signal generation circuit 712, 712-1, 712-2 video signal processing circuit 713, 713-1, 713-2 ... Level inverting circuits 714-1 and 714-2 ... SW circuits 715 ... Screen display control circuits 716-1 and 716-2 ... Scan control circuits 717-1 and 717-2 ... Reference signal generation circuits 803-1 and 803-2 ... Signal selection circuit 804 ... Decoding circuits 805-1 and 805-2 ... Control signal acquisition circuit 806 ... Screen switching control circuit 807 ... Selection signal Raw circuit 808 ... 1/2 screen signal generation circuit 809 ... the sampling control circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H04N 5/45 H04N 5/45 5/46 5/46 5/66 102 5/66 102B

Claims (9)

[Claims] 1. A display comprising a plurality of display pixels arranged in a matrix at intersections of a plurality of scanning signal lines and a plurality of data signal lines, and divided into N (N ≧ 2) electrically independent pixels. A display panel having an area, a vertical scanning circuit connected to the scanning signal lines, and N horizontal scanning circuits respectively connected to data signal lines wired to the N divided display areas, Or, N video signal processing means for obtaining N display signals to be displayed in the N display areas from N video signals having different specifications, and synchronization signals respectively obtained from the N video signals When,
A vertical scanning clock signal, a vertical scanning start signal, N horizontal scanning clock signals, and N vertical scanning clock signals supplied to the vertical scanning circuit and the N horizontal scanning circuits based on a display control signal input from the outside. A driving signal generating means for generating N driving signals such as a horizontal scanning start signal. 2. The driving signal generating means includes a selecting means, which selects the N video signals or the N display signals based on the display control signal. And outputs each of the N horizontal video signals. Alternatively, the N video signals, or one video signal among the N display signals, or one display signal is output to the N horizontal video signals. 2. The flat panel display according to claim 1, wherein all the signals are supplied to a scanning circuit. 3. A vicinity of an intersection between a plurality of first scanning signal lines, a plurality of first data signal lines substantially orthogonal to the first scanning signal lines, and each of the first scanning signal lines and the data signal lines. A first display region including a first pixel electrode disposed via a switch element, a plurality of second scanning signal lines disposed along the first scanning signal line, and a second display region. A plurality of second data signal lines that are substantially orthogonal to the scanning signal lines, and a second pixel electrode that is arranged via a switch element near an intersection of each of the second scanning signal lines and the data signal lines. A display panel comprising: a second display region; and a first and a second connected to the first and second scanning signal lines.
A vertical scanning circuit; first and second video signal processing circuits connected to the first and second data signal lines; and a driving signal generating unit. The driving signal generating unit is externally input. A first driving circuit that outputs a first vertical control signal to the first vertical scanning circuit and outputs a first video signal and a first horizontal control signal to the first video signal processing circuit based on the first input video signal. A second vertical control circuit for outputting a second vertical control signal to the second vertical scanning circuit based on a second input video signal which is input from outside and has an asynchronous or different specification from the first input video signal.
An image display device, comprising: a second driving circuit for outputting a second video signal and a second horizontal control signal to a video signal processing circuit. 4. The driving signal generating means outputs a second vertical control signal to the second vertical scanning circuit, and outputs a second video signal and a second video signal to the second video signal processing circuit.
Whether to output a horizontal control signal or to output a first vertical control signal to the second vertical scanning circuit and to output a first video signal and a first horizontal control signal to the first video signal processing circuit. The image display device according to claim 3, further comprising a selection unit for selecting. 5. The first and second vertical control signals include a vertical scan clock signal and a vertical scan start signal, and the first and second horizontal control signals include a horizontal scan clock signal and a horizontal scan start signal. The image display device according to claim 3, wherein: 6. A display panel comprising: a plurality of third scanning signal lines; a plurality of third data signal lines substantially orthogonal to the third scanning signal lines; and a plurality of third scanning signal lines and a data signal. A third display region including a third pixel electrode disposed in the vicinity of the intersection with the line via a switch element;
A third vertical scanning circuit connected to a scanning signal line; and a third video signal processing circuit connected to the third data signal line. A third driving circuit unit that outputs a third vertical control signal to the third vertical scanning circuit based on the input video signal and outputs a third video signal and a third horizontal control signal to the third video signal processing circuit; The image display device according to claim 3, further comprising: 7. A plurality of display pixels arranged in a matrix at an intersection of a plurality of scanning signal lines and a plurality of data signal lines divided into two substantially at the center of the display panel, and the plurality of scanning signals divided into two. Vertical scanning circuits respectively connected to the lines,
A horizontal scanning circuit for supplying a display signal to a plurality of data signal lines of the display pixels, supplying a vertical scanning clock signal and a vertical scanning start signal to the vertical scanning circuit, and a horizontal scanning clock to the horizontal scanning circuit. A flat display device that displays an image obtained from two video signals that are not synchronized with the left and right sides of the display panel by supplying a signal, a horizontal scanning start signal, and a video signal. First drive signals such as a vertical scan clock signal, a vertical scan start signal, a horizontal scan clock signal, and a horizontal scan start signal to be supplied to the first vertical scan circuit and the first horizontal scan circuit to be connected are generated. A first scanning control unit, a second vertical scanning circuit connected to a pixel on the right side of the display panel, and a vertical scanning clock signal supplied to the second horizontal scanning circuit; Scanning control means for generating a second driving signal such as a clock signal, a horizontal scanning clock signal, and a horizontal scanning start signal; and a first scanning control means for supplying the first horizontal scanning circuit to the first horizontal scanning circuit based on a first selection signal. A first video processing selection output unit for obtaining a display signal of the first video signal or the second video signal, and a second video signal supplied to the second horizontal scanning circuit based on the second selection signal. And a second video processing selection output unit for obtaining the display signal from the first video signal and the second video signal, and a synchronizing signal of the first video signal supplied from the first video processing selection output unit A first clock signal as a first reference signal synchronized with the first, a first video start signal indicating a video start timing, and a first reference signal generating means for generating a first video end signal indicating a video end timing; From the second video processing selection output means. A second clock signal, which is a second reference signal synchronized with a synchronization signal of the supplied second video signal, a second video start signal indicating a video start timing, and a second video end signal indicating a video end timing Second reference signal generating means for generating the first video start signal and the second video start signal,
A first signal selecting unit that selects one of a first clock signal and a second clock signal based on a first selection signal and supplies the selected signal to a first scanning control unit as a first reference signal; One of the first video start signal and the second video start signal, and one of the first clock signal and the second clock signal is selected based on the second selection signal.
First control signal acquiring means for obtaining a first display control signal to be supplied to the first scanning control means based on the first sampling signal and second signal selecting means for supplying the reference signal as a reference signal, and second scanning. A second control signal acquisition unit for obtaining a second display control signal to be supplied to the control unit based on the second sampling signal, and a first control signal acquisition unit from a display control signal input from the outside, a second control A decoding means for obtaining a signal to be supplied to the signal acquisition means and the screen switching control means, and a selection signal generating means for generating the first and second selection signals based on the signal supplied from the decoding means;
Sampling control means for generating first and second sampling signals to be supplied to the second control signal acquisition means, and 1/1 indicating one screen display period to be supplied to the first and second scanning control means.
Screen switching control means comprising a half screen signal generating means for generating a two screen signal, wherein when the half screen signal indicates a two screen display period, the first scanning control means and the second scanning signal
Scan control means generates first and second drive signals so as to display images obtained from two systems of video signals which are not synchronized with the left and right pixels of the display panel, respectively. When the / 2 screen signal indicates one screen display period, the first scanning control means and the second scanning control means
The frequency of the horizontal scanning clock signal supplied to each of the second horizontal scanning circuits is set to about half the frequency in displaying two screens, and the horizontal scanning clock signals supplied to the first horizontal scanning circuit and the second horizontal scanning circuit are further supplied. An image display device wherein a phase of a scanning start signal is generated such that a combined image scanned by the first horizontal scanning circuit and the second horizontal scanning circuit becomes an image of one screen. . 8. A single and a second reference signal supplied to the first and second scanning control means are selected from the same or different reference signals and supplied to the display panel. Alternatively, in the image display device that performs display including a plurality of images, the selection signal generating unit sets the first and second selection signals to new values after the drive scanning by the first and second scanning control units is completed. The driving scan by the first and second scanning control means is temporarily stopped during the period from immediately after the update to the supply of a new reference signal by updating the data to a new reference signal. The image display device as described in the above. 9. A method according to claim 1, wherein the first and second reference signals respectively supplied to the first and second scanning control means are switched from different reference signals to the same reference signal, so that a two-screen display can be used to convert a single image. In the image display device having the function of switching the screen to the single screen display, the switching to the single image is controlled by the first and second control y signal acquiring means and the sampling control means from the sampling control signal acquiring means. The data update of the display control signal supplied to the scanning control means controlled to display both the screen display and the single screen display is performed by changing the data of the display control signal supplied to the sampling control means from the timing at which the control signal supplied to the sampling control means changes. The image display device according to claim 7, wherein the image display device is prohibited until the video end signal is supplied.