JPS6088666U - display device - Google Patents
display deviceInfo
- Publication number
- JPS6088666U JPS6088666U JP17933483U JP17933483U JPS6088666U JP S6088666 U JPS6088666 U JP S6088666U JP 17933483 U JP17933483 U JP 17933483U JP 17933483 U JP17933483 U JP 17933483U JP S6088666 U JPS6088666 U JP S6088666U
- Authority
- JP
- Japan
- Prior art keywords
- display
- video
- frame period
- video data
- display panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal Display Device Control (AREA)
- Transforming Electric Information Into Light Information (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の表示装置のブロック図、第２図ａ−ｇは
第１図の動作説明用タイミングチャート、第３図以下の
図面はこの考案の表示装置の１実施例を示し、第３図は
ブロック図、第４図は第３図の一部の詳細なブロック図
である。
・ １・・・・・・映像入力端子、５，６・・・・・・
第１、第２デジタルシフトレジスタ、７，９・・・・・
・第１、第２ラツチ、８，１０・・・・・・第１、第２
表示ドライバ、１１・・・・・・同期分離回路、１３・
・・・・・階調制御回路、１４・・・・・・スキャンド
ライバ、１５・・・・・・分割マトリックス液晶表示パ
ネル、１６・・・・・・アナログゲート回路、１７・・
・・・・アナログシフトレジスタ回路、１８・・・・・
・映像信号保持出力部、１９・・・・・・アナログ／デ
ジタ、ル変換回路、２０・・・・・・同期制御回路、２
１゜２２・・・・・・第１．第２ゲート入力端子、２３
，２４、２５．２６・・・・・・第１ないし第４アナロ
グスイツチ、２７．２８・・・・・・アナログシフトレ
ジスタ。FIG. 1 is a block diagram of a conventional display device, FIGS. 2a to 2g are timing charts for explaining the operation of FIG. The figure is a block diagram, and FIG. 4 is a detailed block diagram of a part of FIG. 3.・ 1...Video input terminal, 5, 6...
First and second digital shift registers, 7, 9...
・1st, 2nd latch, 8, 10... 1st, 2nd
Display driver, 11... Synchronization separation circuit, 13.
... Gradation control circuit, 14 ... Scan driver, 15 ... Divided matrix liquid crystal display panel, 16 ... Analog gate circuit, 17 ...
...Analog shift register circuit, 18...
・Video signal holding output unit, 19...Analog/digital conversion circuit, 20...Synchronization control circuit, 2
1゜22...1st. Second gate input terminal, 23
, 24, 25.26...first to fourth analog switches, 27.28...analog shift register.
Claims (1)
下半分とが分割表示駆動される表示パネルを備え、映像
信号の再生画面を前記表示パネルに表示する表示装置に
おいて、入力された映像信号の各フレーム期間の前半お
よび後半に前記各フレーム期間の前半および後半の映像
信号をそれぞれラッチし、前記各フレーム期間の前半ま
たは後半からの１フレ一ム期間に前記前半および後半の
映像信号を同時にくり返し出力する映像信号保持出力部
と、該保持出力部から出力された前記前半および後半の
映像信号を同時にデジタル変換し時系列の前半映像デー
タ信号および後半映像データ信号をそれぞれ形成するデ
ジタル変換部と、前記前半映像データ信号にもとづき前
記表示パネルの上半分を表示駆動するとともに、前記後
半映像データ信号にもとづき前記表示パネルの下半分を
上半分の表示駆動タイミングと同一タイミングで表示駆
動する分割表示駆動部とを備えた表示装置。In a display device that is equipped with a display panel in which a plurality of display electrodes are arranged in a matrix and an upper half and a lower half are driven for split display, a reproduction screen of a video signal is displayed on the display panel. The video signals of the first half and the second half of each frame period are latched in the first half and the second half of each frame period, respectively, and the video signals of the first half and the second half are simultaneously repeated in one frame period from the first half or the second half of each frame period. a video signal holding output unit to output, and a digital conversion unit that simultaneously digitally converts the first half and second half video signals outputted from the holding output unit to form time-series first half video data signals and second half video data signals, respectively; a split display drive unit that drives the upper half of the display panel to display based on the first half video data signal, and drives the lower half of the display panel to display at the same timing as the display drive timing of the upper half based on the second half video data signal; A display device equipped with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17933483U JPS6088666U (en) | 1983-11-19 | 1983-11-19 | display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17933483U JPS6088666U (en) | 1983-11-19 | 1983-11-19 | display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6088666U true JPS6088666U (en) | 1985-06-18 |
Family
ID=30389127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17933483U Pending JPS6088666U (en) | 1983-11-19 | 1983-11-19 | display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6088666U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1987006755A1 (en) * | 1986-04-24 | 1987-11-05 | Fanuc Ltd | Display system of plasma display |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5263014A (en) * | 1975-11-19 | 1977-05-25 | Hitachi Ltd | Driving system of multiple matrix liquid crystal panel |
| JPS5528671A (en) * | 1978-08-23 | 1980-02-29 | Seiko Epson Corp | Liquid crystal display unit |
-
1983
- 1983-11-19 JP JP17933483U patent/JPS6088666U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5263014A (en) * | 1975-11-19 | 1977-05-25 | Hitachi Ltd | Driving system of multiple matrix liquid crystal panel |
| JPS5528671A (en) * | 1978-08-23 | 1980-02-29 | Seiko Epson Corp | Liquid crystal display unit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1987006755A1 (en) * | 1986-04-24 | 1987-11-05 | Fanuc Ltd | Display system of plasma display |
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