WO1987006755A1 - Display system of plasma display - Google Patents

Display system of plasma display Download PDF

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Publication number
WO1987006755A1
WO1987006755A1 PCT/JP1987/000227 JP8700227W WO8706755A1 WO 1987006755 A1 WO1987006755 A1 WO 1987006755A1 JP 8700227 W JP8700227 W JP 8700227W WO 8706755 A1 WO8706755 A1 WO 8706755A1
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Prior art keywords
data
plasma display
display
ram
shift register
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PCT/JP1987/000227
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French (fr)
Japanese (ja)
Inventor
Seiichi Hattori
Kunio Kanda
Original Assignee
Fanuc Ltd
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Publication of WO1987006755A1 publication Critical patent/WO1987006755A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes

Definitions

  • the present invention relates to a plasma display method used for a numerical controller or the like, and particularly to a plasma display method in which transfer of display data and display of a plasma display are made independent.
  • Plasma displays are thinner than CRT displays, and are widely used by taking advantage of their features.
  • the external shape is thin, the cabinet and the like are small, and the weight of the entire unit is small.
  • FIG. 3 a circuit as shown in FIG. 3 is used as a display method of such a plasma display.
  • reference numeral 20 denotes a PU
  • reference numeral 21 denotes a ROM in which a control program is stored
  • reference numeral 22 denotes a work RAM
  • reference numeral 23 denotes a video RAM that stores video information
  • reference numeral 24 reads information from the video RAM 23.
  • This is a display control circuit for writing to the plasma display 25, and 25 is a plasma display device.
  • the display control circuit 24 constantly reads out the information from the video RAM 23 at a fixed period and writes the information into the plasma display 25, so that the operation was constantly repeated. Therefore, the display control circuit 2 is always
  • the CPU 20 In order to access the video RAM 23, the CPU 20 must access the video RAM 23 and synchronize with the display control circuit 2 so that they do not access the video RAM 23 at the same time. However, there is a problem that the circuit configuration becomes complex. Disclosure of the invention
  • An object of the present invention is to solve the above problems and to provide a display method of a plasma display having a simple circuit configuration by focusing on the operation of the plasma display.
  • the plasma display since the plasma display has a memory function in the display device itself, it is not necessary to always write display data. Writing at the next time data is transferred ensures that the data stored in the new RAM is always displayed.
  • FIG. 1 is a block diagram of an embodiment of the present invention.
  • FIG. 2 is a diagram showing a timing chart of an embodiment of the present invention
  • FIG. 3 is a block diagram of a conventional plasma display display system.
  • FIG. 1 shows a block diagram of an embodiment of the present invention.
  • 1 is a CPU
  • 2 is a R ⁇ M in which an it control program is stored
  • 3 is a character RAM which stores character information
  • 4 is a character RAM.
  • Character RAM 5 for converting character data to display data
  • graphic RAM 6 for storing graphic information
  • a synthesizing circuit for synthesizing character data and graphic data.
  • Reference numeral 10 denotes a plasma display, which is displayed by drive signals in the X-axis and Y-axis directions.
  • Reference numeral 1 denotes a shift register which serially accepts display data and, at the same time, determines the data position in the X-axis direction of the plasma display in synchronism with the display register.12 receives the display data of the shift register 11; This is a driver for driving the plasma display.
  • Reference numeral 13 denotes an address generator in the Y-axis direction of the plasm display. Receives the Y-axis address signal simultaneously with the transfer of the display data to the shift register 11.
  • Reference numeral 14 denotes a driver which drives a corresponding Y-axis line in response to a signal from an address generator 13.
  • Reference numeral 15 denotes a timing generation circuit that generates a timing pulse having a constant period.
  • a signal BUSY is output to the bus line, and the next timing pulse is output to the plasma display.
  • Output as a write signal HSYNC, and then drop the signal BUSY.
  • FIG. 2 shows a time chart of this embodiment.
  • a signal HT is a timing pulse that is automatically generated at regular intervals inside the timing generation circuit 15.
  • the signal HSYNC is a timing signal for writing the display data of the shift register 11 to the plasma display 10.
  • the signal DATA is a signal indicating an operation in which the CPU 1 reads the display data signal from the synthesis circuit 6 and writes the display data signal into the shift register 11, where the R portion is read and the W portion is the data of the shift register 11.
  • the signal W.END is a signal that notifies the timing generation circuit of the end of the write after the CPU writes the display data into the shift register 11.
  • the signal BUSY is a signal indicating that the next data transfer signal cannot be received until the timing generation circuit 15 receives the data transfer completion signal W.END and generates a write signal.
  • Time t, in CPU 1 transfers the display data read out, this in time t 2 to the shift register 1 1. Turn at time t 3 1 Transmission ends, and the transfer end signal W. END is sent to the timing generation circuit. Thailand Mi ring generating circuit 1 5 is to output the signal between BUSY from the time t 4 until the occurrence of the next of the write signal HSYNC. During this time, the next data transfer will not be accepted
  • next timing pulse HT is output as the write signal HSYNC, and the driver 12 is driven by the signal HSYC to display the display data of the shift register 11 on the plasma display 12. Then, a signal BUSY is turned off at time t 6 will be waiting for the transfer of the next display data.
  • the character information and the graphic information are combined and displayed. However, it is needless to say that only one of them can be displayed. Although the transfer of the display data to the shift register 11 is transferred to all the bits of the shift register at one time, it can be transferred every several bits.
  • the present invention is configured so that display data transfer and display are performed separately by focusing on the memory operation of the plasma display, so that the CPU performs display regardless of the display operation on the plasma display side. Since data can be transferred, the hardware configuration is simplified, the CPU processing speed is improved, and the CPU

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)

Abstract

A plasma display system which displays characters and graphics. Data are transferred from RAM's (3, 5) that store data to be displayed to a shift register (11) via a character generator (4) and a synthesizing circuit (6). When the transfer of data is finished, a transfer finish signal (W. END) is given to a timing generating circuit (15) which is so constructed as to generate a write timing pulse to the plasma display upon receipt of the transfer finish signal (W. END) and to write the data of the shift register (11) onto the plasma display. Since the display device itself has a storage function, the data to be displayed need not be written ont the plasma display (10) at all times. If the data is written at a timing next to the timing when the data to be displayed is transferred to the shift register (11), the new data stored in the RAM's (3, 5) can be displayed.

Description

明 書 プラズマディ スプレイ の表示方式 技 術 分 野  Description Plasma display display method
本発明は数値制御装置等に使用されるプラズマディスブレ ィの表示方式に関し、 特に、 表示データの転送とプラズマデ イスプレイの表示を独立にするようにしたプラズマディスプ レイの表示方式に閼する。 背 景 技 術  The present invention relates to a plasma display method used for a numerical controller or the like, and particularly to a plasma display method in which transfer of display data and display of a plasma display are made independent. Background technology
プラズマディスプレイ は C R T表示装置に比較して、 その 厚さが薄く、 その特徴を生かして広-く使用されている。 特に 外形が薄く 、 キャビネ ッ ト等が小さ く ュニッ ト全体の重量が 小さいという利点がある。  Plasma displays are thinner than CRT displays, and are widely used by taking advantage of their features. In particular, there are advantages that the external shape is thin, the cabinet and the like are small, and the weight of the entire unit is small.
このようなプラズマディスプレイの表示方式として従来第 3図のような回路が使用されている。 図において、 2 0 はじ P U、 2 1 は制御プログラムが記憶される R O M、 2 2 はヮ ーク R A M、 2 3 はビデオ情報を記憶するビデオ R A M、 2 4はビデオ R A M 2 3の情報を読出し、 プラズマディスプレ ィ 2 5に書込むディスプレイ制御回路であり、 2 5 はプラズ マディ スプレイ表示装置である。  Conventionally, a circuit as shown in FIG. 3 is used as a display method of such a plasma display. In the figure, reference numeral 20 denotes a PU, reference numeral 21 denotes a ROM in which a control program is stored, reference numeral 22 denotes a work RAM, reference numeral 23 denotes a video RAM that stores video information, and reference numeral 24 reads information from the video RAM 23. This is a display control circuit for writing to the plasma display 25, and 25 is a plasma display device.
ディ スプレイ制御回路 2 4は一定周期でビデオ R A M 2 3 の情報を読出し、 これをプラズマディスプレイ 2 5に書込む という動作を常に操り返しおこなっていた。 このため、 ディ スプレイ制御回路 2 が常にビデオ R A MThe display control circuit 24 constantly reads out the information from the video RAM 23 at a fixed period and writes the information into the plasma display 25, so that the operation was constantly repeated. Therefore, the display control circuit 2 is always
2 3をアクセスするので C P U 2 0 はビデオ R A M 2 3にァ クセスするためにはディ スプレイ制御回路 2 と相互に同期 をとつて同時に両者がビデオ R A M 2 3をアクセスしないよ うに制御する必要があり、 回路構成が複維になるという問題 点,があった。 発 明 の 開 示 In order to access the video RAM 23, the CPU 20 must access the video RAM 23 and synchronize with the display control circuit 2 so that they do not access the video RAM 23 at the same time. However, there is a problem that the circuit configuration becomes complex. Disclosure of the invention
本発明の目的は上記問題点を解決し、 プラズマディスプレ ィの記億:作用に着目して、 回路構成が簡単なプラズマデイス プレイの表示方式を提供することにある。  SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide a display method of a plasma display having a simple circuit configuration by focusing on the operation of the plasma display.
本発明では上記の問題点を解決するために、 キャラクタ やグラフィ フ クを表示するプラズマデイスプレイの表示方式 において、  In the present invention, in order to solve the above problems, in a plasma display display method for displaying characters and graphics,
表示すべきデータが記億された R A Mからデータを転送し - 転送終了で転送終了信号を発生する手段と、 該データをシリ アルに受け入れるシフ ト レジスタと、 常時一定周期毎に前記 プ'ラズマデイスプレイへの書込タイ ミ ングバルスを発生し、 前記転送終了信号の次にく る該タイ ミ ングパルスで前記ブラ ズマディ スプレイへ前記シフ ト レジスタのデータを書込むよ うにしたタイ ミ ング発生回路と、 を有することを特徴とする プラズマディスプレイ の表示方式が、  Means for transferring data from a RAM in which data to be displayed is stored, a means for generating a transfer end signal at the end of transfer, a shift register for serially receiving the data, and the above-mentioned plasma display at regular intervals. And a timing generating circuit that generates a write timing pulse to the shift register and writes the data of the shift register to the plasma display with the timing pulse following the transfer end signal. The display method of the plasma display characterized by having
提供ざれる。  Can not be provided.
本発明ではプラズマディスプレイ は表示装置そのものに記 憶作用があるので常に表示データを書込む必要はな く、 表示 データが転送された次のタ イ ミ ングで書込みを行えば、 常に 新しい R A Mに記憶されたデータを表示することができる。 In the present invention, since the plasma display has a memory function in the display device itself, it is not necessary to always write display data. Writing at the next time data is transferred ensures that the data stored in the new RAM is always displayed.
図 面 の 簡 単 な 説 明 第 1図は本発明の一実施例のプロ ク構成図、 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of the present invention.
第 2図は本発明の一実施例のタ イ ムチヤ一 トを示す図、 第 3図は従来のプラズマディ スプレイ表示方式のブロ ック 構成図である。 発明を実施するための最良の形態 以下本発明の一実施例を図面に基ずいて説明する。  FIG. 2 is a diagram showing a timing chart of an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional plasma display display system. BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.
第 1図に本発明の一実施例のプロ ッ ク構成図を示す。 図に おいて、 1 は C P U、 2 it制御プロ グラ ムが記憶される R 〇 M、 3 はキ ャ ラ ク タ情報を記憶するキ ャ ラ ク タ R A M、 4は キ ャ ラ ク タ情報を表示デ一タ に変換するキ ャ ラ ク タ ジ ヱネ レ ータ、 5 はグラフィ ッ ク情報を記憶するグラフ ィ ッ ク R A M 6 はキャラクタデータとグラフ ィ フ クデータを合成する合成 回路である。  FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure, 1 is a CPU, 2 is a R〇M in which an it control program is stored, 3 is a character RAM which stores character information, and 4 is a character RAM. Character RAM 5 for converting character data to display data, graphic RAM 6 for storing graphic information, and a synthesizing circuit for synthesizing character data and graphic data.
1 0 はプラズマディ スプレイ であり X軸及び Y軸方向の ド ライ ブ信号によって表示が行われる。 1 1 はシフ ト レジスタ であり、 表示データをシ リ アルに受け入れ、 同時にプラ ズマ ディ スプレイ の X軸方向のデータ位置も同期して定められる 1 2 はシフ 卜 レジスタ 1 1 の表示データを受け、 プラズマデ イ スプレイを駆動するための ドライバである。 1 3 はプラズ マディ スプレイ の Y軸方向のァ ドレスジエネレイ タであり、 表示データのシフ ト レジスタ 1 1への転送と同時に Y軸のァ ドレス信号を受ける。 1 4 は ドライバであり、 ア ドレスジヱ ネレイ タ 1 3の信号をうけ該当する Y軸のライ ンをドライブ する。 1 5はタイ ミ ング発生回路であり、 一定周期のタイ ミ ングパルスを発生させており、 入力信号 W . E N Dがく ると、 信号 B U S Yをバスライ ンに出力し、 次のタイ ミ ングパルス をプラズマディ スプレイ の書込信号 H S Y N Cとして出力し、 その後で信号 B U S Yを落とす。 Reference numeral 10 denotes a plasma display, which is displayed by drive signals in the X-axis and Y-axis directions. Reference numeral 1 denotes a shift register which serially accepts display data and, at the same time, determines the data position in the X-axis direction of the plasma display in synchronism with the display register.12 receives the display data of the shift register 11; This is a driver for driving the plasma display. Reference numeral 13 denotes an address generator in the Y-axis direction of the plasm display. Receives the Y-axis address signal simultaneously with the transfer of the display data to the shift register 11. Reference numeral 14 denotes a driver which drives a corresponding Y-axis line in response to a signal from an address generator 13. Reference numeral 15 denotes a timing generation circuit that generates a timing pulse having a constant period. When an input signal W. END is received, a signal BUSY is output to the bus line, and the next timing pulse is output to the plasma display. Output as a write signal HSYNC, and then drop the signal BUSY.
次に本実施例の動作について説明する。 第 2図に本実施例 のタイムチャー トを示す。 図において、 信号 H Tはタイ ミ ン グ発生回路 1 5の内部で自動的に一定周期毎に発生されるタ ィ ミ ングパルスである。 信号 H S Y N Cはシフ ト レジスタ 1 1の表示データをプ'ラズマディスプレイ 1 0に書込むための タイ ミ ング信号である。 信号 D A T Aは C P U 1が合成回路 6から表示データ信号を読み、 シフ ト レジスタ 1 1 に書込む 動作を表す信号であり、 Rの部分が読出し、 Wの部分がシフ ト レジスタ 1 1へのデータの書込み （シリ アル入力） である。 信号 W . E N Dは C P U 1が表示データをシフ ト レジスタ 1 1へデータを書込んだあとに書込み終了をタィ ミ ング発生回 路に知らせる信号である。 信号 B U S Yはタイ ミ ング発生回 路 1 5がデータ転送完了信号 W . E N Dを受けて書込信号を 発生する迄の間次のデータ転送信号を受けられないことを示 す信号である。  Next, the operation of this embodiment will be described. FIG. 2 shows a time chart of this embodiment. In the figure, a signal HT is a timing pulse that is automatically generated at regular intervals inside the timing generation circuit 15. The signal HSYNC is a timing signal for writing the display data of the shift register 11 to the plasma display 10. The signal DATA is a signal indicating an operation in which the CPU 1 reads the display data signal from the synthesis circuit 6 and writes the display data signal into the shift register 11, where the R portion is read and the W portion is the data of the shift register 11. Write (serial input). The signal W.END is a signal that notifies the timing generation circuit of the end of the write after the CPU writes the display data into the shift register 11. The signal BUSY is a signal indicating that the next data transfer signal cannot be received until the timing generation circuit 15 receives the data transfer completion signal W.END and generates a write signal.
時刻 t , において、 C P U 1 は表示データを読出し、 時刻 t 2 でこれをシフ ト レジスタ 1 1へ転送する。 時刻 t 3 で転 1 送が終了し、 転送終了信号 W. E N Dがタイ ミ ング発生回路 へ送られる。 タイ ミ ング発生回路 1 5 は時刻 t 4 から次の書 込信号 H S Y N Cを発生するまでのあいだ信号 B U S Yを出 力する。 この間次のデータ転送があっても受け入れられないTime t, in, CPU 1 transfers the display data read out, this in time t 2 to the shift register 1 1. Turn at time t 3 1 Transmission ends, and the transfer end signal W. END is sent to the timing generation circuit. Thailand Mi ring generating circuit 1 5 is to output the signal between BUSY from the time t 4 until the occurrence of the next of the write signal HSYNC. During this time, the next data transfer will not be accepted
5 ことを示す。 時刻 1； 5 で次のタイ ミ ングパルス H Tを書込み 信号 H S Y N Cとして出力し、 ドライ バ 1 2を信号 H S Y Cで駆動してシフ ト レジスタ 1 1 の表示データをプラズマデ イ スプレイ 1 2 に表示する。 そして、 時刻 t 6 で信号 B U S Yをオフにして次の表示データの転送を待つことになる。5 Indicates that At time 1; 5 , the next timing pulse HT is output as the write signal HSYNC, and the driver 12 is driven by the signal HSYC to display the display data of the shift register 11 on the plasma display 12. Then, a signal BUSY is turned off at time t 6 will be waiting for the transfer of the next display data.
10 以上の実施例ではキャ ラク タ情報とグラフィ ック情報を合 成して表示するようにしたが、 勿論いずれか一方のみの表示 も可能である。 又、 シフ ト レジスタ 1 1 への表示データの転 送はシフ ト レジスタの全ビッ トへ一回に転送するようにした が、 数ビッ ト毎に転送することもできる。 In the embodiments described above, the character information and the graphic information are combined and displayed. However, it is needless to say that only one of them can be displayed. Although the transfer of the display data to the shift register 11 is transferred to all the bits of the shift register at one time, it can be transferred every several bits.
15 以上説明したように本発明ではプラズマディ スプレイ の記 億作用に着目して表示データの転送と表示を別途に行うよう に構成したから、 C P Uはプラズマディ スプレイ側の表示動 作と無関係に表示データの転送ができるので、 ハー ドウェア の構成が簡単とな.り、 C P Uの処理速度が向上し、 C P U側 15 As described above, the present invention is configured so that display data transfer and display are performed separately by focusing on the memory operation of the plasma display, so that the CPU performs display regardless of the display operation on the plasma display side. Since data can be transferred, the hardware configuration is simplified, the CPU processing speed is improved, and the CPU
20 とプラズマディ スプレイ惻の互換性をもたせることができる 20 and plasma display compatibility

Claims

請 求 の 範 囲 The scope of the claims
1 . キャラクタやグラフィ ックを表示するプラズマデイ ス プレイ の表示方式において、  1. In a plasma display system that displays characters and graphics,
表示すべきデータが記億された R A Mからデータを転送し、 転送終了で転送終了信号を発生する手段と、  Means for transferring data from the RAM in which data to be displayed is stored, and generating a transfer end signal at the end of transfer;
該データをシリ アルに受け入れるシフ ト レジスタと、 常時一定周期毎に前記プラズマデイ スプレイへの書込タィ ミ ングパルスを究生し、 前記転送終了信号の次に く る該タイ ミ ングパルスで前記プラズマディ スプレイ へ前記シフ ト レジ スタのデータを書込むようにしたタイ ミ ング発生回路と、 を有するこどを特徵とするプラズマディ スプレイ の表示方 式。  A shift register for serially receiving the data and a write timing pulse to the plasma display are constantly generated at regular intervals, and the plasma pulse is generated by the timing pulse following the transfer end signal. A timing generation circuit for writing the data of the shift register to a display, and a display method for a plasma display featuring a child having the following.
2 . 前記データを記憶する R A Mはキャ ラクタ-を記憶する R A Mとグラフィ ックを記億する R A Mから構成されること を特徵とする特許請求の範囲第 1項のプラズマディ スプレイ の表示方式。  2. The display method for a plasma display according to claim 1, wherein the RAM for storing the data includes a RAM for storing characters and a RAM for storing graphics.
3 . 前記データを記憶するキャ ラク タを記憶する R A Mと グラフイ クを記憶する R A Mの出力を合成する合成回路を有 することを特徵とする特許請求の範囲第 2項記載のプラズマ ディ スプレイ の表示方式。  3. The plasma display display according to claim 2, further comprising a synthesis circuit that synthesizes an output of a RAM that stores a character that stores the data and a RAM that stores a graphic. method.
4 . データのシフ ト レジスタへの転送は全ビッ トを転送す るように構成したことを特徵とする特許請求の範囲第 1項記 載のプラズマデイ スプレイ の表示方式。  4. The display method for a plasma display according to claim 1, wherein data is transferred to the shift register so that all bits are transferred.
5 . データのシフ ト レジスタへの転送は一部のビッ トを転 送するように構成したことを特徵とする特許請求の範囲第 1 項記載のプラズマディ スプレイ の表示方式 5. The first aspect of the present invention is characterized in that data is transferred to the shift register by transferring a part of the bits. Display method of plasma display described in section
PCT/JP1987/000227 1986-04-24 1987-04-10 Display system of plasma display WO1987006755A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP61/095403 1986-04-24
JP61095403A JPS62251792A (en) 1986-04-24 1986-04-24 Display system for plasma display

Publications (1)

Publication Number Publication Date
WO1987006755A1 true WO1987006755A1 (en) 1987-11-05

Family

ID=14136701

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1987/000227 WO1987006755A1 (en) 1986-04-24 1987-04-10 Display system of plasma display

Country Status (3)

Country Link
EP (1) EP0266429A4 (en)
JP (1) JPS62251792A (en)
WO (1) WO1987006755A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5260031A (en) * 1975-11-12 1977-05-18 Fujitsu Ltd Graphic display system
JPS54162930A (en) * 1978-06-14 1979-12-25 Fujitsu Ltd Display system for low-speed display unit
JPS557596B2 (en) * 1973-11-15 1980-02-26
JPS58105191A (en) * 1981-12-17 1983-06-22 富士通株式会社 Driving of ac type plasma display panel
JPS6088666U (en) * 1983-11-19 1985-06-18 三洋電機株式会社 display device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4266225A (en) * 1978-12-05 1981-05-05 Burnett Bradley W Display panel interface circuit
JPS572089A (en) * 1980-06-06 1982-01-07 Nippon Electric Co Plasma display information transfer control ststem
US4445501A (en) * 1981-05-07 1984-05-01 Mccormick Laboratories, Inc. Circuits for determining very accurately the position of a device inside biological tissue
US4639721A (en) * 1982-10-09 1987-01-27 Sharp Kabushiki Kaisha Data selection circuit for the screen display of data from a personal computer
DE3484448D1 (en) * 1983-03-07 1991-05-23 Ibm SYSTEM FOR CONTROLLING PLASMA SCREENS.
JPS60225894A (en) * 1984-04-25 1985-11-11 ソニー株式会社 Sequential selection circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS557596B2 (en) * 1973-11-15 1980-02-26
JPS5260031A (en) * 1975-11-12 1977-05-18 Fujitsu Ltd Graphic display system
JPS54162930A (en) * 1978-06-14 1979-12-25 Fujitsu Ltd Display system for low-speed display unit
JPS58105191A (en) * 1981-12-17 1983-06-22 富士通株式会社 Driving of ac type plasma display panel
JPS6088666U (en) * 1983-11-19 1985-06-18 三洋電機株式会社 display device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0266429A4 *

Also Published As

Publication number Publication date
JPS62251792A (en) 1987-11-02
EP0266429A4 (en) 1989-04-12
EP0266429A1 (en) 1988-05-11

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