JPS54162930A - Display system for low-speed display unit - Google Patents

Display system for low-speed display unit

Info

Publication number
JPS54162930A
JPS54162930A JP7196778A JP7196778A JPS54162930A JP S54162930 A JPS54162930 A JP S54162930A JP 7196778 A JP7196778 A JP 7196778A JP 7196778 A JP7196778 A JP 7196778A JP S54162930 A JPS54162930 A JP S54162930A
Authority
JP
Japan
Prior art keywords
speed
address
rewriting
writing
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7196778A
Other languages
Japanese (ja)
Other versions
JPS6210436B2 (en
Inventor
Koichi Kawamoto
Shigeru Kasahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7196778A priority Critical patent/JPS54162930A/en
Publication of JPS54162930A publication Critical patent/JPS54162930A/en
Publication of JPS6210436B2 publication Critical patent/JPS6210436B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

PURPOSE: To increase the overall writing speed for the display system featuring a lower writing speed to the display unit than the transfer speed to the memory by setting up the flag at the rewriting bit memory only when the rewriting is required to control the rewriting.
CONSTITUTION: The data given from CPU is memorized temporarily in register 11 and then sent to high-speed memory RAM13 based on the address of address counter 12. The data is then compared at comparator 15 with the contents of the address. And if an agreement is obtained, no rewriting is required for the contents of RAM13. While in case no agreement is obtained, flag 1 is set up at the corresponding bit of rewriting bit memory 14 via the disagreement signal to control counter 12 and RAM control circuit 12. Thus the data is rewritten for the address of RAM13. Then the data of the address where the flag is set up is sent via counter 12 to writing control circuit 18 of AC-type plasma display unit PDP. Thus, a low- speed writing is given to PDP. In such way, the writing data quantity is reduced to increase the overall writing speed.
COPYRIGHT: (C)1979,JPO&Japio
JP7196778A 1978-06-14 1978-06-14 Display system for low-speed display unit Granted JPS54162930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7196778A JPS54162930A (en) 1978-06-14 1978-06-14 Display system for low-speed display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7196778A JPS54162930A (en) 1978-06-14 1978-06-14 Display system for low-speed display unit

Publications (2)

Publication Number Publication Date
JPS54162930A true JPS54162930A (en) 1979-12-25
JPS6210436B2 JPS6210436B2 (en) 1987-03-06

Family

ID=13475741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7196778A Granted JPS54162930A (en) 1978-06-14 1978-06-14 Display system for low-speed display unit

Country Status (1)

Country Link
JP (1) JPS54162930A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1987006755A1 (en) * 1986-04-24 1987-11-05 Fanuc Ltd Display system of plasma display
JPS6374095A (en) * 1986-09-18 1988-04-04 富士通株式会社 Color display device
JPS6374096A (en) * 1986-09-18 1988-04-04 富士通株式会社 Plasma display device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1987006755A1 (en) * 1986-04-24 1987-11-05 Fanuc Ltd Display system of plasma display
JPS6374095A (en) * 1986-09-18 1988-04-04 富士通株式会社 Color display device
JPS6374096A (en) * 1986-09-18 1988-04-04 富士通株式会社 Plasma display device

Also Published As

Publication number Publication date
JPS6210436B2 (en) 1987-03-06

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