JPS60238928A - Display controller - Google Patents

Abstract

PURPOSE:To reduce the scale of hardware so as to be integrated large scale in a display controller, by separating a process for processing the access time of a displaying picture data memory as a unit from another process for processing the time of dot clocks as a unit. CONSTITUTION:A frequency dividing circuit 7 gives a timing pulse necessary to the reading out time of a displaying picture data memory 2 to a counter by dividing a dot clock. Therefore, the counter 9 updates the content of the counter 9 by using the reading out time of the memory 2 as a unit. The data of the memory 2 read out to an output register 8 are selected in accordance with the content of the counter 9 and sent to another output register 3. The register 3 is shifted by the dot clock and its output is inputted in series in a shift register 4. Therefore, display can be started from an aimed optional bit position when an optional bit output of the register 4 is appropriately selected.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a control device for a rask scan type CRT display, which is one of the output devices of an information processing system.

(Conventional structure and its problems) In recent years, CRT display devices have become indispensable as output devices for information processing systems, and in order to improve man-machine interfaces, high-resolution CRT display devices have been used as control devices. There is a demand for a device that has display and control functions for each display pixel (dot).

A conventional CRT display control device will be explained below.

FIG. 1 shows the configuration of a conventional CRT display control device, in which 1 is a memory address register (MAR), 2 is a memory address register (MAR);
is the display image data memory (VM), 3 is the output shift register (SHRO), 4 is the buffer shift register (SHRI), 5 is the output selector (SEL), and 6 is the display start bit position register (SP).
), 7 is a dot clock frequency divider circuit (DIV).

The operation of the conventional CRT display control device configured as described above will be described below.

The frequency divider circuit 7 is provided for the purpose of matching the number of dots constituting the read data of the display image data memory, and the contents of the memory address register 1 are updated every time the output signal of the frequency divider circuit 7 is output. Data is read from memory 2 and sent to shift register 3. The buffer shift register 4 receives the output of the shift register 3 in series in units of display dot clocks, and always holds display image driver 1 data corresponding to the access time of the display memory 2. By selecting the output of each bit of the shift register constituting this buffer shift register 4 from the bit position specified by the display start bit position register 6 and sending it to the CRT device, the display image data memory 2 is A method is adopted in which display data is sent to a display device from an arbitrary bit position constituting the read data, regardless of the boundaries (referred to as word boundaries) of read data 3- (1 word).

FIG. 2 is a timing diagram explaining the above operation,
This figure shows how read data at an arbitrary address A in the display image data memory 2 is shifted by shift registers 3 and 4 during the read period at address A-14.

However, the above configuration requires a control circuit corresponding to the read data length of the display image data memory 2, and the hardware cost of the high-speed operation circuit increases for the high-frequency dot clock in high-definition CRT control. There are problems in that it is difficult to process the data into an LSI, and when controlling the start of one display, an overhead corresponding to the two-word display time is generated.

(Object of the Invention) The present invention solves the above-mentioned conventional problems, and provides a high-speed readout of a display image memory that stores display image data. It is an object of the present invention to provide a CRT display control device that can largely eliminate operating hardware and can be easily integrated into an LSI through normal processes.

(Structure of the Invention) The present invention provides a frequency dividing circuit that receives a display dot clock as an input, a first counter that operates based on the output of the frequency dividing circuit, and a second counter that operates based on a carry signal of the counter. a storage device for storing display image data whose address is the contents of this counter; and a storage device for storing display image data read out from this device in synchronization with the timing of the carry signal of the first counter. 1 register, a first selector that takes out a part of the output of this register according to the contents of the first counter, and a first selector that stores the output of this selector in synchronization with the output timing of the frequency dividing circuit, and a first shift register for shifting data, and a second shift register for serially inputting the shift output data.

The display control device includes a second selector that takes out 1-bit 5-data of the parallel output of the second shift register, and a second register that outputs a selection signal to this selector, and the second register outputs a selection signal to the selector. By sequentially selecting a part of the output of the first register that holds display image data and transferring it to the first shift register according to the contents of An efficient control device that can reduce the amount of hardware required for the shift register mechanism that requires high-speed operation to start displaying, and separate parts that require high-speed operation from parts that operate at low speed. can be realized.

(Description of Embodiment) FIG. 3 shows the configuration of a display control device in an embodiment of the present invention. In FIG. 3, 1 is a memory address register (MAR), 2 is a display image data memory (V
M), 3 is the output shift register (SHRO), 4 is the buffer shift register (SHRI), 5 is the bit position selector (SHLl), 6 is the bit position designation register (BP), and 6-7 are the frequency divider circuits ( DIV), 8 is an output register (BUF) that holds one word of display image data, 9 is a counter (DCNT) operated by the output of the frequency dividing circuit 7, and 10
is a selector that takes out a part of the output register 8 according to the contents of the counter 9.

The operation of the display control device of this embodiment configured as described above will be explained.

The frequency dividing circuit 7 divides the dot clock and supplies the timing pulse necessary for the readout time (memory access time) of the display image data memory 2 to the counter 9 . Therefore,
The counter 9 calculates the readout time of the display image data memory 2 (
The contents are updated in units of (access time).

When a carry signal is output from the counter 9, the memory address register 1 is counted up and the data in the display image data memory 2 corresponding to this updated address is read out, and after the memory access time has elapsed, the data is output. Stored in register 8. The data read into the output register 8 is selected according to the contents of the counter 9, and is sent to the output shift register 3 after the memory access time has elapsed. The output shift register 3 is shifted by the dot clock, and its output is serially input to the buffer shift register 4. This buffer shift register 4 continues a shift operation using the dot clock, and by appropriately selecting an arbitrary bit output of the shift register, display can be started from a desired arbitrary bit position.

The bit position selector 5 and bit position designation register 6 are provided for this purpose.

FIG. 4 is a detailed diagram for explaining the operations of the output selector 10 and the bit position selector 5.

In FIG. 4, counter 9 is an m-bit counter, and bit position designation register 6 is n-bit. In this case, the data length (word length) read out at one time from the display image data memory 2 is 2I11·2n bits. The selector 10 selects 2n bits of data from the read data and sends it to the output shift register 3.

Further, the bit position selector 5 selects 1 bit from the 2-bit data 8 and sends it to the CRT device.

FIG. 5 is a timing diagram explaining the above operation,
This figure shows how the contents of address A in the display image memory 2 are output to the output register 8 and shifted by the output shift register 3 and the buffer shift register 4 up to the display start timing.

In FIG. 5, Do, Di, D2. D3 represents data time relationships, each corresponding to the contents of the counter 9.

As described above, according to this embodiment, a counter that operates in units of time required for accessing the display image data memory that stores display image data is placed in the front stage of the display memory address register, and By providing an output register that holds the read data of No. 2 and a selector that selects and outputs the output of this output register based on the contents of a counter placed before the display image memory address register, the access time of the display image data memory can be reduced. It is possible to separate the process (process) in which data is processed as a unit (=9-) and the process (process) in which the data output from the selector is processed using a shift register in units of dot clock time, and the process (process) in which the data output from the selector is processed using a shift register is possible. Furthermore, hardware that operates in units of time of the dot clock can be realized on a minimum scale.

In the embodiment, the counter 9 may be configured using a shift register, and the output register 8 and the output shift register 3 may be configured independently of the dot clock (asynchronously) at the timing of each storage control signal. ), but it goes without saying that it may also be synchronized with the dot clock.

(Effects of the Invention) The display control device of the present invention has a first counter that operates in units of time required for accessing the display image data memory, and a second counter that operates based on the carry signal of the counter. (in the example, the memory address register), a first register (output register) that temporarily holds data read out from the display image memory using the contents of the second counter as an address, and 10 - part of the contents of this first register. By providing a first selector (output selector) that selects and outputs the data according to the contents of the first counter, the process of processing the access time of the display image data memory as a unit and the process of processing the access time of the display image data memory as a unit, and It is possible to separate the process of processing data using the first and second shift registers (output shift register and buffer shift register) in units of dot clock time. The scale of processing hardware can be minimized by using shift registers that operate in units of time, and at the same time, in LSI implementation, the above two processing steps can be performed using high-speed element processes and low-speed element processes. By configuring each of them, efficient chip formation can be achieved, and the practical effects thereof are significant.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional display control device, FIG. 2 is a timing diagram explaining the operation of the conventional display control device, and FIG.
The figure is a configuration diagram of a display control device according to an embodiment of the present invention, and FIGS. 4 and 5 are detailed diagrams and timing charts for explaining the same operation. 1...Memory address register, 2...Display image data memory, 3...Output shift 1-register,
4...Buffer shift register, 5...
Bit position selector, 6... Bit position designation register, 7... Frequency dividing circuit, 8... Output register, 9... First counter, 1o... Output selector. Patent Applicant: Matsushita Electric Industrial Co., Ltd. Figure 3 Displayed in Figure 4 - Data Memory 2

Claims (1)

[Claims] A frequency dividing circuit that inputs a clock corresponding to a display dot;
a memory for storing display image data; a first counter that receives the output of the frequency dividing circuit as an input and operates in units of access time of the memory; a second counter that operates based on a carry signal of the counter; A first register that stores the read display image data in synchronization with the carry signal, with the contents of the counter as the read address of the memory, and a part of the output of this register are selected by the contents of the first counter. a first selector, a first shift register that operates with a dot clock and stores the output of the first selector in synchronization with the output of the frequency divider circuit, and a second shift register that receives the shift output in series. A register, a second selector that selects a part of the parallel output of the second shift register and sends it to the display device, and a second register that sends selection information to the second selector. A display control device characterized by: