JPH0475623U - - Google Patents
Info
- Publication number
- JPH0475623U JPH0475623U JP11851590U JP11851590U JPH0475623U JP H0475623 U JPH0475623 U JP H0475623U JP 11851590 U JP11851590 U JP 11851590U JP 11851590 U JP11851590 U JP 11851590U JP H0475623 U JPH0475623 U JP H0475623U
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- crystal panel
- electrodes
- control means
- peak value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004973 liquid crystal related substance Substances 0.000 claims description 9
- 239000011159 matrix material Substances 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Accessories And Tools For Shearing Machines (AREA)
- Punching Or Piercing (AREA)
Description
第１図ないし第６図は本考案の実施例を示すも
ので、第１図は第１実施例の構成を示すブロツク
図、第２図は同実施例の動作を説明するためのタ
イミングチヤート、第３図は第２実施例の構成を
示すブロツク図、第２図は同実施例の動作を説明
するためのタイミングチヤート、第５図は第３実
施例の構成を示すブロツク図、第６図は同実施例
の動作を説明するためのタイミングチヤート、第
７図は従来の液晶パネル駆動方式を説明するため
のタイミングチヤートである。
１０……走査電極駆動回路、１１……走査電極
用シフトレジスタ、１２……マルチプレクサ、１
３ａ〜１３ｄ，１７ａ，１７ｂ……ゲート回路、
２０……信号電極駆動回路、２１……信号電極駆
動用シフトレジスタ、２２……ラツチ＆階調信号
作成回路、２３……マルチプレクサ、２４ａ〜２
４ｄ……ゲート回路、３０……液晶パネル。
1 to 6 show embodiments of the present invention. FIG. 1 is a block diagram showing the configuration of the first embodiment, and FIG. 2 is a timing chart for explaining the operation of the embodiment. 3 is a block diagram showing the configuration of the second embodiment, FIG. 2 is a timing chart for explaining the operation of the same embodiment, FIG. 5 is a block diagram showing the configuration of the third embodiment, and FIG. 6 7 is a timing chart for explaining the operation of the same embodiment, and FIG. 7 is a timing chart for explaining the conventional liquid crystal panel driving system. 10...Scanning electrode drive circuit, 11...Scanning electrode shift register, 12...Multiplexer, 1
3a to 13d, 17a, 17b...gate circuit,
20...Signal electrode drive circuit, 21...Signal electrode drive shift register, 22...Latch & gradation signal creation circuit, 23...Multiplexer, 24a-2
4d...gate circuit, 30...liquid crystal panel.
Claims (1)
置されてなる液晶パネルを駆動する液晶パネル駆
動回路において、各走査電極の選択期間をｍ分割
してｍ回同一データによる表示を行なう表示制御
手段と、上記各走査電極に対する駆動信号の波高
値を上記分割期間毎に異ならせる波高値制御手段
とを具備したことを特徴とする液晶パネル駆動回
路。 (2) 走査電極と信号電極とがマトリクス状に配
置されてなる液晶パネルを駆動する液晶パネル駆
動回路において、各走査電極の選択期間をｍ分割
してｍ回同一データによる表示を行なう表示制御
手段と、上記各信号電極に対する駆動信号の波高
値を上記分割期間毎に異ならせる波高値制御手段
とを具備したことを特徴とする液晶パネル駆動回
路。 (3) 走査電極と信号電極とがマトリクス状に配
置されてなる液晶パネルを駆動する液晶パネル駆
動回路において、各走査電極の選択期間をｍ分割
してｍ回同一データによる表示を行なう表示制御
手段と、上記走査電極及び信号電極に対する駆動
信号の波高値を上記分割期間毎に異ならせる波高
値制御手段とを具備したことを特徴とする液晶パ
ネル駆動回路。[Claims for Utility Model Registration] (1) In a liquid crystal panel drive circuit that drives a liquid crystal panel in which scanning electrodes and signal electrodes are arranged in a matrix, the selection period of each scanning electrode is divided into m, and the selection period of each scanning electrode is divided into m, and the selection period of each scanning electrode is 1. A liquid crystal panel drive circuit comprising: display control means for displaying data; and peak value control means for varying the peak value of a drive signal for each of the scanning electrodes for each of the divided periods. (2) In a liquid crystal panel drive circuit that drives a liquid crystal panel in which scan electrodes and signal electrodes are arranged in a matrix, a display control means that displays the same data m times by dividing the selection period of each scan electrode into m parts. and a peak value control means for varying the peak value of the drive signal for each of the signal electrodes for each of the divided periods. (3) In a liquid crystal panel drive circuit that drives a liquid crystal panel in which scanning electrodes and signal electrodes are arranged in a matrix, a display control means that displays the same data m times by dividing the selection period of each scanning electrode into m. and a peak value control means for varying the peak value of the drive signal for the scanning electrode and the signal electrode for each of the divided periods.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11851590U JPH0810438Y2 (en) | 1990-11-14 | 1990-11-14 | Turret punch press table equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11851590U JPH0810438Y2 (en) | 1990-11-14 | 1990-11-14 | Turret punch press table equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0475623U true JPH0475623U (en) | 1992-07-02 |
| JPH0810438Y2 JPH0810438Y2 (en) | 1996-03-29 |
Family
ID=31866439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11851590U Expired - Lifetime JPH0810438Y2 (en) | 1990-11-14 | 1990-11-14 | Turret punch press table equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810438Y2 (en) |
-
1990
- 1990-11-14 JP JP11851590U patent/JPH0810438Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0810438Y2 (en) | 1996-03-29 |
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