JPH0262491U - - Google Patents
Info
- Publication number
- JPH0262491U JPH0262491U JP13877288U JP13877288U JPH0262491U JP H0262491 U JPH0262491 U JP H0262491U JP 13877288 U JP13877288 U JP 13877288U JP 13877288 U JP13877288 U JP 13877288U JP H0262491 U JPH0262491 U JP H0262491U
- Authority
- JP
- Japan
- Prior art keywords
- pixels
- display panel
- scanning line
- video signal
- shifted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000005070 sampling Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 1
Landscapes
- Liquid Crystal Display Device Control (AREA)
Description
図面は本考案の一実施例を示すもので、第１図
は回路構成を示すブロツク図、第２図は第１図に
おける遅延回路の詳細を示すブロツク図、第３図
は動作を説明するためのタイミングチヤート、第
４図はアクテイブ・マトリクス型液晶表示パネル
の画素配列を示す図である。
１１ａ，１１ｂ……遅延回路、１２ａ，１２ｂ
，……，１３ａ，１３ｂ……，……サンプル回路
、１４ａ，１４ｂ……シフトレジスタ、１６ａ，
１６ｂ……ゲート駆動回路、１７……液晶表示パ
ネル。
The drawings show one embodiment of the present invention; FIG. 1 is a block diagram showing the circuit configuration, FIG. 2 is a block diagram showing details of the delay circuit in FIG. 1, and FIG. 3 is a diagram for explaining the operation. 4 is a diagram showing the pixel arrangement of an active matrix type liquid crystal display panel. 11a, 11b...delay circuit, 12a, 12b
,..., 13a, 13b...,...sample circuit, 14a, 14b...shift register, 16a,
16b...gate drive circuit, 17...liquid crystal display panel.
Claims (1)
画素配列した表示パネルを用いた画像表示装置に
おいて、上記表示パネルの１走査ライン毎に１．
５画素ずれた画素に供給する原映像信号を１．５
画素分の時間だけ遅延させる遅延手段と、この手
段により遅延された映像信号と原映像信号とを１
走査ライン毎に交互に選択する選択手段と、この
手段により選択された信号をサンプリングして表
示パネルのデータラインに供給する手段とを具備
したことを特徴とする画像表示装置。 In an image display device using a display panel in which pixels are arranged in a delta shape by shifting 1.5 pixels for each scanning line, 1.5 pixels are shifted for each scanning line of the display panel.
The original video signal supplied to pixels shifted by 5 pixels is 1.5
A delay means for delaying a time corresponding to a pixel, and a video signal delayed by this means and an original video signal.
An image display device comprising: selection means for alternately selecting each scanning line; and means for sampling a signal selected by the selection means and supplying the sampled signal to a data line of a display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13877288U JPH0262491U (en) | 1988-10-25 | 1988-10-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13877288U JPH0262491U (en) | 1988-10-25 | 1988-10-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0262491U true JPH0262491U (en) | 1990-05-10 |
Family
ID=31401424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13877288U Pending JPH0262491U (en) | 1988-10-25 | 1988-10-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0262491U (en) |
-
1988
- 1988-10-25 JP JP13877288U patent/JPH0262491U/ja active Pending
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