JPS63136473U

JPS63136473U -

Info

Publication number: JPS63136473U
Application number: JP2824187U
Authority: JP
Priority date: 1987-02-27
Filing date: 1987-02-27
Publication date: 1988-09-07
Anticipated expiration: 2002-02-27
Also published as: JPH0628863Y2

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例におけるアクテイブ
・マトリクス型液晶表示装置の回路構成を示すブ
ロツク図、第２図は第１図の動作を説明するため
のタイミングチヤート、第３図はＴＦＴ液晶表示
パネルの電気的構成を示す図、第４図は従来にお
けるアクテイブ・マトリクス型液晶表示装置の回
路構成を示すブロツク図、第５図は第４図の液晶
表示装置に入力する映像信号の順番を切換える切
換回路の構成を示すブロツク図、第６図はＴＦＴ
液晶表示パネルのカラー画素配列順序を示す図、
第７図は第４図の動作を説明するためのタイミン
グチヤートである。２１ａ，２１ｂ，〜……サンプル回路、２２…
…シフトレジスタ、２３ａ，２３ｂ，〜……第１
のホールド回路、２４ａ，２４ｂ，〜……第２の
ホールド回路、２５ａ，２５ｂ，〜……切換スイ
ツチ、２６……ＴＦＴ液晶表示パネル、２７……
奇数側ゲート駆動回路、２８……偶数側ゲート駆
動回路。 Fig. 1 is a block diagram showing the circuit configuration of an active matrix liquid crystal display device according to an embodiment of the present invention, Fig. 2 is a timing chart for explaining the operation of Fig. 1, and Fig. 3 is a TFT liquid crystal display device. A diagram showing the electrical configuration of the panel, Figure 4 is a block diagram showing the circuit configuration of a conventional active matrix type liquid crystal display device, and Figure 5 shows how to switch the order of video signals input to the liquid crystal display device in Figure 4. A block diagram showing the configuration of the switching circuit, Figure 6 is a TFT
A diagram showing the color pixel arrangement order of a liquid crystal display panel,
FIG. 7 is a timing chart for explaining the operation of FIG. 4. 21a, 21b, ~...sample circuit, 22...
...shift register, 23a, 23b, ~...first
hold circuit, 24a, 24b, ~... second hold circuit, 25a, 25b, ~... changeover switch, 26... TFT liquid crystal display panel, 27...
Odd number side gate drive circuit, 28...Even number side gate drive circuit.

Claims

[Claims for Utility Model Registration] In an active matrix liquid crystal display device that displays a video signal of N scanning lines sent in an interlaced manner on a liquid crystal display panel having approximately 2N scanning lines, the liquid crystal display panel described above a first hold circuit that samples and holds a video signal to be displayed on the nth (n is an odd or even number) scanning line;
A second hold circuit holds the same information as the hold circuit, and the charge charged in the first hold circuit is discharged and charged to the nth pixel of the liquid crystal display panel, and at the next timing, the n+1th pixel is charged. 1. A flicker prevention circuit for an active matrix liquid crystal display device, comprising means for performing line sequential scanning by discharging charges charged in the second hold circuit for the pixels.