JPH10191210A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent display character deformation and the occurrence of flicker owing to thinning with inexpensive circuit constitution by controlling the timing of thinning scanning with a sift clock signal and enable signals and changing respective scanning electrode positions where thinning scanning is executed at every frame. SOLUTION: The shift clock signal CNB inputted to a scanning line side driving circuit 22 from a controller through an interface circuit and the enable signals EN1 and EN2 of the scanning timing control of scanning electrodes for odd and even lines are provided. The supply timing of thinning scanning is controlled by the enable signals EN1 and EN2 changing the supply timing of more than one signals to the scanning side driving circuit 22 at every frame. At the time of 1/6 thinning, video information for one scanning electrode is thinned in scanning lines X3, X8,.... Thus, the scanning timing of the scanning electrodes X1-X10 is set and the scanning electrode positions where thinning scanning is executed are changed at every frame.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device. The present invention relates to a liquid crystal display device that sequentially performs thinning-out scanning at a ratio of one scanning electrode line.

[0002]

2. Description of the Related Art Conventionally, NTSC (National Television)
System Committee) system and PAL (Phase Alternation)
In a liquid crystal display device that displays an image on a liquid crystal display panel based on a video input signal of the "Line by color television" system, the number of scanning lines (common lines) provided on the liquid crystal display panel is based on the video input signal. When the number of scanning lines of an image is large, thinning-out scanning is performed at a predetermined ratio, and an image based on the image input signal is displayed on a liquid crystal display panel.

FIG. 6 is a diagram showing a circuit configuration of a conventional scanning line side driving circuit. In FIG. 1A, the scanning line side driving circuit 30 includes a shift register circuit 31 and a driver circuit 3.
2.

The shift register circuit 31 includes flip-flops FF0, FF1, FF2... And an inverter INV1.
To INV3. Each of the flip-flops FF1, FF2, FF3,.
T, a scan start signal CDB for setting a scan start timing and a selection width (one horizontal scan period) of a scan line, and the outputs of the inverters INV1 to INV3 of the shift clock signal CNB are input, and the flip-flops FF1, FF2, and FF are input.
.. Correspond to the corresponding tri-state circuits TS1, TS2, TS3 of the driver circuit 32 by sequentially shifting the scanning start signal CDB in accordance with the shift clock signal CNB.
Output to

The driver circuit 32 includes tristate circuits TS1, TS2, TS3,... And an inverter INV4.
S2, TS3,... Have the circuit configuration shown in FIG. As shown in FIG. 6B, the tri-state circuit T
S denotes NAND gates 41 and 42, level shifter 4
3, 44, 45 and P-type MOSs 46, 47.

The tri-state circuit TS has a P-type MO connected to two signal lines (0, 2) of three signal lines (0, 1, 2) extending from a V terminal to an OUT terminal.
S46 and S47 are provided. Each P-type MOS4
The signals (0, 0,
Or 1) and the outputs of the NAND gates 41 and 42 of the signal input to the IN terminal are converted to a predetermined voltage level by level shifters 43 and 44 and supplied, whereby the two signal lines (0, 2) Is turned on and off.

Further, the remaining 1 from the V terminal to the OUT terminal
The signal input to the IN terminal is converted into a predetermined voltage level by the level shifter 45 and supplied to the signal line (1).

Therefore, each of the tri-state circuits TS1, TS2, TS3,... Shown in FIG. In addition, three types of drive voltages V0, V2, and V4 are applied to the V terminal,
FB and the inverter INV4 of the pole positive / inverted signal CFB
The output is input to the E terminal, and each tristate circuit TS
1, TS2, TS3,... Generate a scan drive signal for selectively driving each scan line based on these inputs,
Output from the terminal to each of the scanning lines X1, X2, X3...

FIGS. 7 and 8 are timing charts showing operation timings in the scanning line driving circuit 30. FIG. As shown in FIGS. 7 and 8, the scanning line side driving circuit 30
Is supplied with the scan start signal CDB, the scan start timing is determined in synchronization with the next fall of the shift clock signal CNB waveform, and the respective scan lines X1, X2, X3 are determined by the pulse width of the scan start signal CDB. .. Are selected (one horizontal scanning period).

Then, hereinafter, the shift clock signal CNB
Each scanning line X1, X2, X corresponding to each scanning drive signal having the determined selection width in synchronization with each falling edge of the waveform.
3 are sequentially supplied.

Therefore, in each period having a pulse width three times as large as that of the shift clock signal CNB, each scanning line (for example, scanning lines X3 and X3 in FIG.
6, X9) is delayed by a predetermined period, and video information for one scanning line is thinned out.

In the timing chart shown in FIG. 7, the number of selected scanning lines in one horizontal scanning period is set to four, and the video information for one scanning line is thinned out. In the timing chart shown in FIG. 8, the number of selected scanning lines in one horizontal scanning period is set to three, and the video information for one scanning line is thinned out. In particular,
In FIG. 7, scanning lines X3, X6, X9 and FIG.
In the case of X2, X4, X6 and X8, video information for one scanning line is thinned out.

As described above, in the conventional scanning line driving circuit 30, the timing control of the thinning-out scanning is performed based only on the shift clock signal CNB.

[0014]

However, in such a conventional liquid crystal display device, as described above, since the timing of the thinning-out scanning is controlled only based on the shift clock signal CNB, the thinning-out scanning in the liquid crystal display panel is performed. Is performed, the position of each scanning line is fixed, and for example, when characters are displayed, deformation of displayed characters due to thinning out becomes noticeable, or flicker occurs. .

The present invention has been made in view of the above problems, and provides a liquid crystal display device capable of changing the position of each scanning line on which thinning-out scanning is performed every predetermined period with an inexpensive circuit configuration. It is to be.

[0016]

According to the first aspect of the present invention,
A liquid crystal display panel in which a plurality of scanning electrode lines and a plurality of signal electrode lines are arranged opposite to each other in a matrix; a scanning start signal for setting a scanning start timing and one horizontal scanning period of the plurality of scanning electrode lines; A scan control signal for setting the number of the scan electrode lines to be selectively driven in each scan period and a thinning scan at a ratio of one scan electrode line for each of a predetermined number of the scan electrode lines; Each scanning timing is set, and a plurality of adjacent scanning electrode lines set by the scanning control signal are sequentially selected and driven for each horizontal scanning period, and a predetermined number of adjacent scanning electrode lines set by the scanning control signal are set. A liquid crystal display device comprising: a scanning side driving unit that sequentially performs thinning-out scanning at a rate of one scanning electrode line for each scanning electrode line; and a signal side driving unit that drives the plurality of signal electrode lines. Controlling means for generating a scan timing control signal for controlling a scan timing of each of the scan electrode lines, and changing a supply timing of the scan timing control signal to the scan-side drive means at predetermined time intervals; The scanning-side driving unit sets each scanning timing of the plurality of scanning electrode lines based on the scanning start signal and the scanning control signal, and the scanning timing control signal supplied from the control unit, thereby setting the scanning timing. In the liquid crystal display panel, the position of each scanning electrode line on which thinning-out scanning is performed at a rate of one scanning electrode line for each of the predetermined number of adjacent scanning electrode lines is changed every predetermined period.

According to the first aspect of the present invention, the control means generates a scan timing control signal for controlling the scan timing of each scan electrode line, and supplies the scan timing control signal to the scan side drive means. Is changed every predetermined period, and the scanning-side driving unit adjusts the scanning timing of each of the scanning electrode lines based on a scanning start signal and a scanning control signal, and the scanning timing control signal supplied from the control unit. Set. With such a configuration, it is possible to easily change the position of each scanning line on which the thinning-out scanning is performed in the liquid crystal display panel every predetermined period, and it is possible to use a low-cost circuit configuration without requiring a complicated control configuration. Deformation of display characters due to thinning and occurrence of flicker can be prevented. As a result, the image quality of the liquid crystal display device can be improved.

According to a second aspect of the present invention, in the liquid crystal display device according to the first aspect, the scan timing control signal includes a first scan for controlling a scan timing of each of the scan electrode lines in an odd-numbered row. A timing control signal, and a second scanning timing control signal for controlling a scanning timing of each scanning electrode line in an even-numbered row,
The supply timing of one or more of the first and second scan timing control signals to the scan-side drive unit is changed every predetermined period, and the scan-side drive unit changes the scan start signal and the scan control signal. By setting respective scan timings of the plurality of scan electrode lines based on a signal and the first and second scan timing control signals, the position of each scan electrode line on which the thinning scan is performed is determined by the predetermined value. It is effective to change every period.

According to the second aspect of the present invention, the control means includes: a first scan timing control signal for controlling a scan timing of each of the scan electrode lines in the odd rows; A second scan timing control signal for controlling the scan timing is generated, and the supply timing of one or more of the first and second scan timing control signals to the scan side driving unit is determined every predetermined period. In other words, the scanning-side driving unit sets each scanning timing of the plurality of scanning electrode lines based on a scanning start signal and a scanning control signal, and the first and second scanning timing control signals. With such a configuration, the position of each scanning line on which the thinning-out scanning is performed is easily changed at predetermined intervals by a combination pattern according to the supply timing of the two scanning timing control signals for each odd-numbered row and even-numbered row. be able to.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to FIGS. First, the configuration will be described. FIG. 1 is a block diagram of a liquid crystal television 1 to which the present invention is applied.

In FIG. 1, a liquid crystal television 1 includes an antenna 11, a tuner 12, a receiving circuit 13, and a synchronizing circuit 1.
4, a display control system including an A / D converter 15, a gradation control circuit 16, a controller 17, an interface circuit 18, and the like, and a liquid crystal module including a liquid crystal display panel 20, a signal side drive circuit 21, a scan side drive circuit 22, and the like. 19.

An antenna 11 transmits a received radio wave to a tuner 12.
The tuner 12 selects a designated channel according to a tuning control signal TC input from the controller 17, converts a received radio wave supplied from the antenna 11 into an intermediate frequency signal, and outputs the intermediate frequency signal to the receiving circuit 13.

The receiving circuit 13 comprises an intermediate frequency amplifier, a video detector, a video amplifier, a chroma circuit (both not shown), and the like. In this receiving circuit 13,
The intermediate frequency signal input from the tuner 12 is video-detected by a video detection circuit to extract a color video signal, an audio signal is extracted from the color video signal, and output to an audio circuit (not shown). Further, the color video signal is amplified by a video amplifier circuit and output to a chroma circuit. The chroma circuit separates each color video signal of R, G, and B (red, green, and blue) from the color video signal to A / A.
Output to the D converter 15.

The synchronizing circuit 14 extracts a horizontal synchronizing signal Hsync and a vertical synchronizing signal Vsync from the color video signal and outputs them to the controller 17.

The A / D converter 15 includes a sampling circuit,
It comprises a comparator circuit, an encoder circuit (both not shown), and the like. In the A / D converter 15, R, G, and B analog signals are sampled by a sampling circuit based on a sampling clock signal supplied from the controller 17, and compared with a reference voltage in a comparator circuit to perform A / D conversion. After that, the data is converted into digital display data of each of R, G, and B by an encoder circuit and output to the gradation control circuit 16.

The gradation control circuit 16 generates a gradation data signal based on the R, G, B digital display data input from the A / D converter 15 according to the basic clock signal supplied from the controller 17. It outputs to the signal side drive circuit 21.

The controller 17 has a CPU (Central Pr
Ocessing Unit), and controls the operation of the entire liquid crystal television 1. FIG. 2 is a block diagram showing the internal configuration of the controller 17 shown in FIG. 1, and the controller 17 includes a pulse signal generation circuit 17a and a timing switching circuit 17b.

The pulse signal generation circuit 17a receives a reset signal RST and a reset signal RST based on an instruction from a CPU (not shown).
A circuit for generating various scan-side drive control signals such as a scan start signal CDB, a polar positive / inverted signal CFB, a shift clock signal CNB, and enable signals EN1 and EN2 for performing timing control of thinning-out scanning. Among the control signals, the reset signal RST, the scan start signal CDB, and the polar inversion signal CFB are output to the interface circuit 18, and the remaining shift clock signal CNB, enable signal EN1, and enable signal EN2 are output to the timing switching circuit 17b. Output.

The timing switching circuit 17b is provided with a shift clock signal CN input from the pulse signal generation circuit 17a.
B, enable signal EN1, and enable signal EN2
Is a circuit for switching and controlling the supply timing of both enable signals EN1 and EN2 to the interface circuit 18 with respect to the shift clock signal CNB. The enable signal EN1 and the enable signal EN2 for which the supply timing is switched and the shift clock signal CNB are Output to the interface circuit 18.

Here, the enable signal EN1 is a signal for controlling the scanning timing of each scanning electrode in an odd-numbered row, and the enable signal EN2 is a signal for controlling the scanning timing of each scanning electrode in an even-numbered row. Timing switching circuit 17b
Then, for each frame, both enable signals EN1, EN1,
The supply timing of one or more signals of EN2 to the interface circuit 18 is changed.

The controller 17 also includes a sampling clock signal,
A basic clock signal or the like is generated and supplied to the A / D converter 15 or the interface circuit 18, or an image based on a received color video signal is generated according to a horizontal synchronization signal (Hsync) and a vertical synchronization signal (Vsync). The image is displayed on the liquid crystal display panel 20.

The interface circuit 18 supplies a horizontal synchronization signal and a vertical synchronization signal input from the controller 17 or various scanning-side drive control signals to the signal-side drive circuit 21 and the scan-side drive circuit 22 of the liquid crystal module 19. The interface circuit 18 generates three types of drive voltages V0, V2, and V4 based on a power supply voltage supplied from a power supply circuit (not shown), and supplies the drive voltages V0, V2, and V4 to the scan side drive circuit 22.

The liquid crystal display panel 20 encloses an STN liquid crystal between two transparent substrates formed of, for example, glass plates,
ITO (indium oxide film: Indium T)
signal electrodes (segment electrodes) Y1 to
A simple matrix type liquid crystal display panel in which Yn and scanning electrodes (common electrodes) X1 to Xm are arranged in a grid in the orthogonal direction is used, and is displayed by a signal side driving circuit 21 and a scanning side driving circuit 22 which will be described later. Driven.

The signal side drive circuit 21 is provided with a gradation control circuit 16.
A liquid crystal driving pulse (display driving signal) having a voltage waveform suitable for AC driving the liquid crystal is generated based on the grayscale data signal supplied from the LCD device, and the liquid crystal driving pulse is applied to each of the signal electrodes Y1 to Yn. Supply at the timing.

The scanning-side drive circuit 22 includes various scanning-side drive control signals (reset signal RST, scan start signal CDB, shift clock signal CNB, and polar positive inversion signal C) input from the controller 17 through the interface circuit 18.
FB, enable signals EN1, EN2, etc.) and three types of drive voltages V supplied from the interface circuit 18.
A liquid crystal drive pulse (scanning drive signal) suitable for AC driving the liquid crystal is generated based on 0, V2, and V4, and the liquid crystal drive pulse is sequentially supplied to each of the scanning electrodes X1 to Xm to be in a selected state. A predetermined voltage is applied to the liquid crystal at each pixel position that intersects with each of the signal electrodes Y1 to Yn, and the liquid crystal is AC-driven.

FIG. 3 is a diagram showing a circuit configuration of the scanning side drive circuit 22. In the figure, the same components as those of the circuit configuration of the scanning side drive circuit 30 shown in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted. In the figure, the scanning line side driving circuit 22 includes a shift register circuit 31, an AND
It comprises a circuit 23 and a driver circuit 32.

The AND circuit 23 includes AND gates 1, 2, 2,
3 and each of the AND gates 1, 2, 2,
3 are flip-flops FF1, FF2, FF3 ...
And each of the tri-state circuits TS1, TS2, TS3 ...
And is provided between them.

Here, one of two input terminals of each of the AND gates 1, 2, 3,..., One of which receives a sequentially shifted scanning start signal CDB from each of the corresponding flip-flops FF1, FF2, FF3,. The enable signal EN1 and the enable signal EN2 are input to every other input terminal. The output terminals of the AND gates 1, 2, 3,... Are connected to the IN terminals of the corresponding tristate circuits TS1, TS2, TS3,.

Therefore, each of the AND gates 1, 2, 3,...
.. Correspond to the corresponding flip-flops FF1, FF2,
Scanning start signal CDB sequentially shifted from FF3
And the enable signal EN1 or the enable signal EN
2 is input, and in each of the AND gates 1, 2, 3,...
The AND output of both signals is output to the corresponding tristate circuits TS1, TS2, TS3,.

With such a circuit configuration, the scanning line side driving circuit 22 controls the timing of thinning scanning based on the shift clock signal CNB and the two newly provided enable signals EN1 and EN2. The above is the configuration of the liquid crystal television 1 in the present embodiment.

Next, the operation will be described. The tuner 12 selects a designated channel according to the tuning control signal TC input from the controller 17 and
Is converted into an intermediate frequency signal and output to the receiving circuit 13. In the receiving circuit 13, the tuner 1
A color video signal is taken out from the intermediate frequency signal input from 2, R, G, and B color video signals are separated from the color video signal and output to the A / D converter 15.

In the synchronizing circuit 14, the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync are taken out of the color video signal and output to the controller 17, and the A / D converter 1
In step 5, analog signals of R, G, and B supplied from the receiving circuit 13 are converted into digital display data of R, G, and B and output to the gradation control circuit 16. Also, the gradation control circuit 16
Then, a gradation data signal based on the R, G, B digital display data input from the A / D converter 15 is generated and output to the signal side driving circuit 21.

In the controller 17, the horizontal synchronizing signal (H
sync) and the vertical synchronization signal (Vsync),
An image based on the received color image signal is displayed on the liquid crystal display panel 20. First, in the controller 17, based on the horizontal synchronization signal (Hsync), the pulse signal generation circuit 17a causes the reset signal RST, the scan start signal CDB,
It generates various scan-side drive control signals such as a shift clock signal CNB, a polar positive / inverted signal CFB, and enable signals EN1 and EN2, and among the generated various scan-side drive control signals, a reset signal RST, a scan start signal CDB, and The polarity inversion signal CFB is output to the scanning side drive circuit 22 via the interface circuit 18.

In the controller 17, of the various scan-side drive control signals generated by the pulse signal generation circuit 17a, the enable signal EN1 and the enable signal EN2 are output by the timing switching circuit 17b for each frame. , EN2, and changes the supply timing of one or more of the signals, and outputs the changed signal to the scanning-side drive circuit 22 via the interface circuit 18.

The interface circuit 18 generates three types of drive voltages V0, V2, and V4 based on a power supply voltage supplied from a power supply circuit (not shown), and
Feed to 2.

In the signal side driving circuit 21, the gradation control circuit 1
6, a display drive signal is generated based on the grayscale data signal supplied from the controller 6, and the display drive signal is simultaneously applied to each of the signal electrodes Y1 to Yn in accordance with a vertical synchronization signal input from the controller 17 via the interface circuit 18. Supply.

In the scanning side drive circuit 22, a reset signal RST, a scan start signal CDB, a shift clock signal CNB, a positive polarity inversion signal CFB, enable signals EN1 and EN2, etc., which are input from the controller 17 via the interface circuit 18, are provided. A scan drive signal is generated based on various scan-side drive control signals and three kinds of drive voltages V0, V2, and V4 supplied from the interface circuit 18, and is sequentially supplied to the scan electrodes X1 to Xm.

At this time, as shown in FIG.
Tristate circuits TS connected to 1 to Xm
, TS2, TS3,... Are connected to AND gates 1, 2, 3,... Respectively. Two input terminals of the AND gates 1, 2, 3,. , The sequentially shifted scanning start signal CDB from each of the corresponding flip-flops FF1, FF2, FF3,... Each AND
The enable signal EN1 is input to the gates 1, 3, 5,..., And the enable signal EN2 is input to the even-numbered AND gates 2, 4, 6,.

Therefore, the odd-numbered scan electrodes X1, X
, X5... Supplied to the corresponding flip-flops FF1, FF3,
Scanning start signal CDB sequentially shifted from FF5
The scan timing of each scan drive signal supplied to the scan electrodes X2, X4, X6,... Of the even-numbered rows is determined by the AND output of the flip-flops FF2, FF4, FF6,. Are determined by the AND output of the sequentially shifted scanning start signal CDB and the enable signal EN2.

FIGS. 4 and 5 are timing charts showing operation timings in the scanning line driving circuit 22. FIG. As shown in both figures, each scanning electrode X is controlled by the pulse width of the scanning start signal CDB supplied to the scanning line side driving circuit 22.
, X2, X3,... (One horizontal scanning period) are determined.

When the scan start signal CDB is supplied to the scan line driving circuit 22, the scan electrode X1 to be scanned first is an odd-numbered row.
The scan timing of the scan drive signal for selectively driving the scan electrode X1 is determined by the AND output of the scan start signal CDB shifted in synchronization with the next falling edge of the B waveform and the enable signal EN1. Then, a scan drive signal having the selected width is supplied to the scan electrode X1 at the determined scan timing.

Thereafter, the scanning electrodes X2, X4, X6 in the even-numbered rows are used.
The scanning timing of each scanning drive signal supplied to... Is determined by the AND output of the scanning start signal CDB sequentially shifted in synchronization with the falling edge of the shift clock signal CNB waveform and the enable signal EN2. X
, X4, X6,... Are sequentially supplied with the scanning drive signals having the selected width at the determined scanning timings.

The scanning electrodes X3, X5, X7 in the even-numbered rows are used.
The scanning timing of each scanning drive signal supplied to... Is determined by the AND output of the scanning start signal CDB and the enable signal EN1 sequentially shifted in synchronization with the falling edge of the shift clock signal CNB waveform, and the scanning electrode X
, X5, X7,... Are sequentially supplied with the scanning drive signals having the selected width at the determined scanning timings.

In the timing charts shown in FIGS. 4 and 5, the number of selected scanning electrodes in one horizontal scanning period is set to two, and video information for one scanning electrode is thinned out of six adjacent scanning electrodes. I have.

Specifically, FIG. 4 is a timing chart showing a part of the scanning state of each of the scanning electrodes X1, X2, X3... In a certain frame.
Then, the timing of thinning-out scanning is determined based on the shift clock signal CNB input from the controller 17 via the interface circuit 18 and the enable signals EN1 and EN2 obtained by changing the supply timing of one or more signals for each frame. When performing the control and performing the thinning-out scanning at a rate of 1/6, the scanning lines X3, X8,.
In s: s = 3 + 5n [n: zero and an integer]), image information for one scanning electrode is thinned out.

FIG. 5 is a timing chart showing a part of the scanning state of each of the scanning electrodes X1, X2, X3... In a frame different from that of FIG.
2, the timing control of the thinning-out scanning is performed based on the shift clock signal CNB and the enable signals EN1 and EN2 whose supply timings are different from those of the frame in FIG. 4, and the scanning lines X4, X9,. : S
= 4 + 5n [n: zero and an integer]), the video information for one scanning electrode is thinned out.

As described above, in the liquid crystal television 1,
In the controller 17, both enable signals EN1, EN1,
Scan-side drive circuit 22 for one or more signals of EN2
Supply timing is changed for each frame, and the scanning line side driving circuit 22 controls the timing of the thinning-out scanning based on the shift clock signal CNB and the enable signals EN1 and EN2, so that the thinning-out in the liquid crystal display panel 20 is performed. The position of each scanning electrode on which scanning is performed is changed for each frame.

The two enable signals EN1, EN
If 2 is always set to “Hi”, it is possible to perform the same display drive as in the related art. The above is the operation procedure of the liquid crystal television 1 in the present embodiment.

In the present embodiment, as the scan timing control signals, an enable signal EN1 for controlling the scan timing of each scan electrode in an odd row and an enable signal E for controlling the scan timing of each scan electrode in an even row.
The controller 17 changes the supply timing of one or more of the two enable signals EN1 and EN2 to the scan-side drive circuit 22 for each frame, and the scan line-side drive circuit 22 Although the thinning-out scan timing is controlled based on the signal CNB and the enable signals EN1 and EN2, the present invention is not limited to the above.

For example, scanning electrodes X1, X4, X7,...
(Xm: m = 1 + 3n [n: zero and integer]), scan electrodes X2, X5, X8 (Xm: m = 2 + 3n [n: zero and integer]), scan electrodes X3, X6, X9 (Xm) : M
= 3 + 3n [n: zero and integer]), three enable signals EN1, E for controlling the scanning timing of each scanning electrode
N2 and EN3 are provided, and the controller 17 changes the supply timing of any one or more of the enable signals EN1 to EN3 to the scanning-side driving circuit 22 for each frame. The shift clock signal CNB and the enable signals EN1-E
Needless to say, a configuration may be adopted in which the timing of the thinning-out scanning is controlled based on N3.

As described above, according to the liquid crystal television 1 of the present embodiment, the controller 17
(Control means) generates an enable signal for controlling the scan timing of each of the scan electrodes X1, X2, X3,... In the pulse signal generation circuit 17a, and in the timing switching circuit 17b, the scan-side drive circuit 22 ( The supply timing to the scan-side drive unit is changed for each frame, and the scan-side drive circuit 22 receives the scan start signal CDB and the shift clock signal CNB, and the enable signal supplied from the controller 17. The scanning timing of each of the scanning electrodes X1, X2, X3,... Is set. Therefore, it is possible to easily change the position of each scanning electrode on which thinning-out scanning is performed in the liquid crystal display panel 20 for each frame. Also, generation of flicker can be prevented.

According to the liquid crystal television 1 of the present embodiment, the controller 17 (control means) controls the scan signal X of the odd-numbered row in the pulse signal generation circuit 17a.
, X3, X5,..., And scan electrodes X2, X4, X
6 Enable signal EN for controlling the scanning timing
2 and the scanning switching circuit 22 (scanning-side driving means) of the timing switching circuit 17b for receiving at least one of the two enable signals EN1 and EN2.
The scan-side drive circuit 22 changes the supply timing for each frame, based on a scan start signal CDB and a shift clock signal CNB, and both enable signals EN1 and EN2 supplied from the controller 17. The scanning timing of each of the scanning electrodes X1, X2, X3,... Is set. Therefore, the position of each scanning line on which thinning-out scanning is performed can be easily changed for each frame by a combination pattern according to the supply timing of the two enable signals EN1 and EN2 for each of the odd-numbered rows and the even-numbered rows.

As described above, the present invention has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the gist of the present invention. Of course.

For example, in the above-described embodiment, the STN type liquid crystal is used for the liquid crystal display panel 20.
It may be a type liquid crystal.

In the above-described embodiment, the position of each scanning electrode on which the thinning-out scanning is performed is changed for each frame. Every time,
It may be every predetermined time.

[0066]

According to the first aspect of the present invention, the control means generates a scan timing control signal for controlling the scan timing of each scan electrode line, and sends the scan timing control signal to the scan side drive means. The supply timing is changed every predetermined period, and the scanning drive unit scans each of the scan electrode lines based on a scan start signal and a scan control signal, and the scan timing control signal supplied from the control unit. Set the timing. Therefore, it is possible to easily change the position of each scanning line on the liquid crystal display panel where the thinning scanning is performed, at predetermined intervals, and it is possible to use a low-cost circuit configuration without the need for a complicated control configuration and to reduce the deformation of display characters due to the thinning. And flicker can be prevented. As a result, the image quality of the liquid crystal display device can be improved.

According to the second aspect of the present invention, the control means includes: a first scanning timing control signal for controlling the scanning timing of each of the scanning electrode lines in an odd-numbered row; A second scan timing control signal for controlling timing is generated, and a supply timing of one or more of the first and second scan timing control signals to the scan side driving unit is changed every predetermined period. The scanning-side driving unit sets each scanning timing of the plurality of scanning electrode lines based on a scanning start signal and a scanning control signal, and the first and second scanning timing control signals. Therefore, it is possible to easily change the position of each scanning line on which the thinning-out scanning is performed according to the combination pattern according to the supply timing of the two scanning timing control signals for each of the odd-numbered rows and the even-numbered rows every predetermined period.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal television to which the present invention has been applied.

FIG. 2 is a block diagram showing an internal configuration of the controller of FIG.

FIG. 3 is a diagram showing a circuit configuration of a scanning line side driving circuit in FIG. 1;

FIG. 4 is a timing chart (part 1) illustrating operation timings in the scanning line side driving circuit of FIG. 1;

FIG. 5 is a timing chart (part 2) illustrating operation timings in the scanning line side driving circuit of FIG. 1;

FIG. 6 is a diagram showing a circuit configuration of a conventional scanning line driving circuit.

FIG. 7 is a timing chart (part 1) showing operation timing in a conventional scanning line side driving circuit.

FIG. 8 is a timing chart (part 2) showing operation timings in the conventional scanning line driving circuit.

[Explanation of symbols]

 Reference Signs List 1 liquid crystal television 11 antenna 12 tuner 13 reception circuit 14 synchronization circuit 15 A / D converter 16 gradation control circuit 17 controller 17a pulse signal generation circuit 17b timing switching circuit 18 interface circuit 19 liquid crystal module 20 liquid crystal display panel 21 signal side drive Circuit 22 Scanning-side drive circuit 23 AND circuit

Claims (2)

[Claims] 1. A liquid crystal display panel in which a plurality of scanning electrode lines and a plurality of signal electrode lines are arranged to face each other in a matrix, a scanning start signal for setting a scanning start timing of the plurality of scanning electrode lines and one horizontal scanning period. And a scan control signal for setting thinning scan at a ratio of one scan electrode line for each of a predetermined number of the scan electrode lines and a predetermined number of the scan electrode lines to be selectively driven in each one horizontal scan period. The scanning timing of each scanning electrode line is set, a plurality of adjacent scanning electrode lines set by the scanning control signal are sequentially selected and driven in each of the one horizontal scanning period, and the scanning timing is set by the scanning control signal. A liquid comprising: a scanning-side driving unit that sequentially performs thinning-out scanning at a ratio of one scanning electrode line for each of a predetermined number of adjacent scanning electrode lines; and a signal-side driving unit that drives the plurality of signal electrode lines. The display device, further comprising: a control unit that generates a scan timing control signal that controls a scan timing of each of the scan electrode lines, and that changes a supply timing of the scan timing control signal to the scan-side driving unit at predetermined intervals. The scanning-side drive unit sets each scan timing of the plurality of scan electrode lines based on the scan start signal and the scan control signal, and the scan timing control signal supplied from the control unit. Wherein the position of each scanning electrode line on which thinning-out scanning is performed at a rate of one scanning electrode line for each of the predetermined number of adjacent scanning electrode lines in the liquid crystal display panel is changed every predetermined period. apparatus. 2. A scanning timing control signal comprising: a first scanning timing control signal for controlling a scanning timing of each scanning electrode line in an odd row; and a second scanning timing control signal for controlling a scanning timing of each scanning electrode line in an even row. The control means changes the supply timing of any one or more of the first and second scan timing control signals to the scan-side drive means at predetermined intervals. The scanning-side driving unit sets each scanning timing of the plurality of scanning electrode lines based on the scanning start signal and the scanning control signal, and the first and second scanning timing control signals, 2. The liquid crystal display device according to claim 1, wherein the position of each scanning electrode line on which the thinning-out scanning is performed is changed every predetermined period.