JPH0973286A - Liquid crystal displaying device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device which has comparatively simple circuit constitution and can prevent degradation of picture quality caused by a spike noise generated in a scanning electrode. SOLUTION: A gradation data making circuit 6 generates gradation data in accordance with display data supplied from a signal source not illustrated and supplies it to a signal side driving circuit 4, while a timing signal generation circuit 7 generates various timing signals and a control signal based on the fundamental clock CK1 supplied from a fundamental signal generation circuit 8 and supplies it to a signal side driving circuit 4. The signal side driving circuit 4 generates a display driving signal having pulse width in accordance with supplied gradation data based on supplied various timing signals and a control signal and the same number of times of rise and fall in one horizontal scanning period, and supplies it to a signal electrode of a liquid crystal display panel 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device capable of reducing spike noise generated in scanning electrodes in a matrix type liquid crystal display panel.

[0002]

2. Description of the Related Art In a conventional simple matrix type liquid crystal display device, a plurality of scanning electrodes (common electrodes) and a plurality of signal electrodes (segment electrodes) are arranged to face each other in a direction orthogonal to each other with a liquid crystal layer interposed therebetween. And has a signal side driving circuit for driving the signal electrodes and a scanning side driving circuit for driving the scanning electrodes.

In the liquid crystal display device as described above, for example, a voltage averaging method has been conventionally used, and when displaying a halftone, a certain period within the selection period of one scanning electrode, that is, display data. The pulse width modulation method (PWM) is applied such that the scan drive signal of the ON voltage (selection voltage) is applied only for the period corresponding to the above, and the scan drive signal of the OFF voltage (non-selection voltage) is applied for the remaining period.

[0004]

However, when a liquid crystal display panel is driven by this conventional liquid crystal display device,
As shown in FIG. 7, the spike noise A is generated on the scan electrode Xm due to the differentiation of the display drive signal applied to the signal electrode Yn at the rising and falling edges.

As described above, the display driving signal for controlling the display of the liquid crystal display panel causes the spike noise to be generated in the scanning driving signal of the scanning electrodes, whereby the effective voltage between the display driving signal and the scanning driving signal is generated. On the display screen, so-called "stringing" is caused and the image quality is degraded.

Here, for example, 4 bits (“0” to “1”)
In a liquid crystal display device capable of reproducing gradations of 5 "gradations, as shown in FIG. 7, those having gradations of" 1 "to" 14 "have polarities during one horizontal scanning period (1H). There is a pair of spike noises different from each other, and these spike noises cancel each other out, which does not cause the above-mentioned "stringing".

However, in the "0" gradation (minimum gradation) and the "15" gradation (maximum gradation), the spike noises cannot be offset in one horizontal scanning period (1H), so the gradation If there are many signal lines of which the level is "0" or "15", spike noise occurs in the common voltage waveform, and there is a problem that the so-called "stringing" deteriorates the image quality on the display screen.

The present invention has been made in view of the above problems, and provides a liquid crystal display device capable of preventing deterioration of image quality due to spike noise generated in scan electrodes with a relatively simple circuit configuration. With the goal.

[0009]

According to another aspect of the present invention, there is provided a liquid crystal driving device, wherein liquid crystal is sealed between a pair of substrates, and a plurality of scanning electrodes formed on one substrate and signal electrodes formed on the other substrate. Is a liquid crystal display device in which a liquid crystal display panel arranged in a grid pattern is driven by a scanning side driving means and a signal side driving means, wherein the signal side driving means comprises grayscale data indicating a grayscale level and grayscale data. PWM signal generation means for generating a PWM signal having a pulse width corresponding to the gradation data based on the control pulse, and reset signal generation for generating a reset signal for resetting the PWM signal every horizontal scanning period. Means for resetting the PWM signal for each horizontal scanning period by the reset signal so that the rising edge and the falling edge within one horizontal scanning period in all gradations, respectively. And it generates a display drive signal having a first number of times, to solve the above problems by providing a display drive signal generating means allowed to apply to the signal electrodes.

That is, according to the liquid crystal display device of the first aspect, the liquid crystal is sealed between the pair of substrates, and the plurality of scanning electrodes formed on one substrate and the signal electrodes formed on the other substrate are provided. In a liquid crystal display device in which a liquid crystal display panel arranged in a grid pattern is driven by a scanning-side driving unit and a signal-side driving unit, the signal-side driving unit includes grayscale data indicating a grayscale level and grayscale control pulses. Generate a PWM signal having a pulse width corresponding to the gradation data,
The PWM signal is reset by a reset signal every horizontal scanning period to generate a display drive signal having the same number of rising edges and falling edges within one horizontal scanning period in all gradations, and applying the display driving signal to the signal electrode. .

Therefore, in all gradations, the scanning electrode has 1
Since it is possible to generate at least one pair of spike noises having the same magnitude and different polarities in the horizontal scanning period, it is possible to completely cancel the spike noises generated in the scan electrodes, and to suppress the display drive signal and the scan drive signal. It is possible to suppress the change in the effective voltage between and and prevent the deterioration of the image quality.

Further, in this case, as in the liquid crystal drive device according to the second aspect, the display drive signal has a pulse width that does not affect the transmittance of the liquid crystal at the lowest gradation and the highest gradation. You may decide to have it.

That is, according to the liquid crystal drive device of the second aspect, the display drive signal has a minimum gradation and a maximum gradation.
Each has a pulse width that does not affect the transmittance of the liquid crystal.

Therefore, it is possible to prevent deterioration of image quality due to "stringing" without affecting the gradation reproducibility.

Further, in this case, as in the liquid crystal display device according to the third aspect, the display drive signal generating means further inverts the voltage polarity of the display drive signal applied to each signal electrode alternately for each scanning electrode. It is also possible to include a polarity reversing means for driving.

That is, according to the liquid crystal display device of the fourth aspect, the voltage polarity of the display drive signal applied to each signal electrode is inverted for each scanning electrode.

Therefore, it is possible to disperse the positions where the spike noise is generated and prevent the deterioration of the image quality.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION A liquid crystal display device of the present invention will be described below based on embodiments.

(First Embodiment) FIG. 1 is a block diagram showing a structural example of a liquid crystal display device of the present invention.

FIG. 3 is a timing chart showing the operation timing of the signal side drive circuit 4 of FIG.

FIG. 4 is a waveform diagram showing an example of a signal voltage (segment voltage) waveform and a scanning voltage (common voltage) waveform of the liquid crystal display device 2.

In FIG. 1, the liquid crystal display device 1 includes a liquid crystal display panel 2, a scanning side drive circuit 3, and a signal side drive circuit 4.
A drive power supply generation circuit 5, a gradation data generation circuit 6,
It is composed of a timing signal generation circuit 7, a basic signal generation circuit 8 and the like.

The drive power supply generation circuit 5 includes a positive side display drive voltage V1C and a negative side display drive voltage V3 for the signal side control circuit 4.
And a positive side selection drive voltage V2 and a negative side selection voltage V4 to the scanning side drive circuit 3.

The basic signal generation circuit 8 generates basic clocks CK1 and CK2 based on, for example, a horizontal synchronizing signal (Hsync) and a vertical synchronizing signal (Vsync) included in a synchronizing signal supplied from a signal source (not shown). And a timing signal generation circuit 7 and a gradation data generation circuit 6 respectively.
To supply.

The timing signal generating circuit 7 is based on the basic clock CK1 supplied from the basic signal generating circuit 8 and outputs the data sampling signal C as shown in FIG. 3B.
KS, a data output signal CKN as shown in FIG.
Gradation creation signals P1 to P as shown in FIGS.
4, a reset signal CR as shown in FIG. 3 (H), and a frame alternating signal FCR as shown in FIG. 4 (A) for inverting the voltage polarity of the display drive signal applied to each signal electrode for each scanning electrode. , And various timing signals such as the zero bias control signal ECB and control signals are generated and supplied to the signal side drive circuit 4.

The timing signal generation circuit 7 also generates a scanning side drive control signal CCK based on the basic clock CK2 supplied from the basic signal generation circuit 8 and supplies it to the scanning side drive circuit 3.

The gradation data creating circuit 6 is based on the input display data of R, G, B (red, green, blue) and has a 4-bit gradation data as shown in FIG. The signals D1 to D4 are generated and supplied to the signal side drive circuit 4. When the input R, G, B signals are analog signals, a 4-bit A / D is provided in the data creating circuit 6.
A conversion circuit may be included.

In the liquid crystal display panel 2, TN liquid crystal is enclosed between two transparent substrates made of, for example, glass plates, and signal electrodes (segment electrodes) Y1 to Yn made of ITO and scanning electrodes are formed on the opposing surfaces of the substrates. A simple matrix type liquid crystal display panel in which (common electrodes) X1 to Xm are arranged in a grid pattern in orthogonal directions is used, and a scanning side drive circuit 3 and a signal side drive circuit 4 described later sequentially scan electrodes X1 to X1. Xm and the signal electrodes Y1 to Yn are selectively driven, and gradation display according to display data is performed.

The scanning side driving circuit 3 generates a display driving signal based on the scanning side driving control signal CCK supplied from the timing signal generating circuit 7 and sequentially supplies it to the plurality of scanning electrodes Xm of the liquid crystal display panel 2. Then, the selected state is set, and a predetermined voltage is applied to the liquid crystal at each pixel position intersecting the signal electrode Yn to drive the liquid crystal.

More specifically, the scanning side drive circuit 3,
It is arranged on the right side of the liquid crystal display panel 2, and the scan electrodes X1 to Xm of the liquid crystal display panel 2 are connected to it.

Then, the scanning side control signal CCK and the negative side selection voltage V4 and the positive side selection voltage V2 are input to the scanning side drive circuit 3, and the scanning side drive circuit 3 receives the scanning side control signal CCK.
The negative side selection voltage V4 or the positive side selection voltage V2 is selected based on the above, and sequentially output to the scan electrodes X1 to Xm as a scan drive signal, whereby the scan electrodes X1 to Xm are sequentially scan driven.

The signal side drive circuit 4 has the 4-bit grayscale data supplied from the grayscale data generation circuit 6 and the positive side display drive voltage V supplied from the drive power supply generation circuit 5.
Receiving 1C and the negative side display drive voltage V3, a liquid crystal drive pulse (display drive signal) having a voltage waveform suitable for AC driving the liquid crystal is generated to generate each signal electrode Y of the liquid crystal display panel 2.
By applying to n at a predetermined timing, gradation display of 16 steps is performed.

Specifically, the signal side drive circuit 4 is arranged above the liquid crystal display panel 2 and is connected to the signal electrodes Y1 to Yn of the liquid crystal display panel 2.

Various timing and control signals, a positive side display drive voltage V1C, and a negative side display drive voltage V3 are input to the signal side drive circuit 4, and the signal side drive circuit 4 receives various timing and control signals. Based on the control signal, the positive side display drive voltage V1C and the negative side display drive voltage V3 corresponding to the display data are selected and output to the respective signal electrodes Y1 to Yn as display drive signals.

That is, the signal side drive circuit 4 and the scanning side drive circuit 3 drive the liquid crystal display panel 2 with an alternating current, and in response to this alternating drive, the positive side display drive voltage V1C, the negative side display drive voltage V3 and the positive side. In addition to selecting the selection voltage V2 and the negative selection voltage V4, the correction non-selection voltage is appropriately selected and output to the signal electrodes Y1 to Yn and the scan electrodes X1 to Xm of the liquid crystal display panel 2.

FIG. 2 is a circuit configuration example of the signal side drive circuit 4.

In FIG. 2, the signal side drive circuit 4 includes a latch circuit (D type flip-flop) 41a1 to 41a4, 4a.
2a1 to 42a4, OR gates 43a1 to 43a4, AND
It comprises a gate 44, an RS flip-flop 46 (NOR gates 46a and 46b), an EXOR gate 47, a NOR gate 48, a level shifter 49, and a transfer gate circuit 50. The latch circuits (D-type flip-flops) 41a1 to 41a4, 42a1
To 42a4, OR gates 43a1 to 43a4, and AND
The gate 44 constitutes the PWM signal generation unit 40 that generates a PWM signal according to the grayscale data.

First, at each D terminal of the latch circuits (D type flip-flops) 41a1 to 41a4, each bit data D1 of 4-bit gradation data as shown in FIG.
(Least significant bit) to D4 (most significant bit) are input respectively, while the data sampling signals CKS as shown in FIG. 3 (B) are input to each CK terminal thereof, and the latch circuit (D type flip-flop) is input. 41a1 to 41a4 latch the logical values of the respective bit data D1 to D4 at the rising of the data sampling signal CKS, and latch the latched signals from the Q terminals to the next stage latch circuits (D type flip-flops) 42a1 to 42a4. To each D terminal of the.

Latch circuit (D type flip-flop) 42
a1 to 42a4 are supplied to the respective CK terminals.
A latch circuit (D-type flip-flop) 41 at the rising edge of the data output signal CKN as shown in (C)
The logic values of the latch signals supplied from a1 to 41a4 are respectively latched, and the latched signals are supplied from the respective Q terminals to the OR gates 43a1 to 43a4 of the next stage.

A latch circuit (D-type flip-flop) 41 is connected to one input terminal of each of the OR gates 43a1 to 43a4.
While the latch signal is supplied from a1 to 41a4, each of the other input terminals is supplied with a latch signal as shown in FIGS.
Each of the grayscale generation signals P1 to P has an "L" level at the start of one horizontal scanning period (1H) and an "H" level at the end.
4 is supplied, and the OR gates 43a1 to 43a4 respectively supply the OR outputs of the latch signal and the gradation creating signals P1 to P4 to the AND gate 44 of the next stage.

The AND gate 44 is the OR gate 43a1.
To 43a4, the AND output of the OR output, that is, the PWM signal corresponding to the gradation data, is applied to the S terminal of the RS flip-flop 46 at the next stage (the input end of the NOR gate 46b).
To supply.

At the S terminal of the RS flip-flop 46,
While the PWM signal is supplied from the AND gate 44, its R terminal (the input end of the NOR gate 46a) is supplied with the PWM signal shown in FIG.
As shown in (H), the reset signal CR that gives the pulse falling timing every 1H is supplied, and the RS flip-flop 46 resets the PWM signal from the Q terminal every 1H (at the start of 1H, "L" Signal) (to the "level") is supplied to the EXOR gate 47 of the next stage.

The EXOR gate 47 is for inverting the voltage polarity of the signal supplied from the RS flip-flop circuit 46 and the display drive signal applied to each signal electrode, as shown in FIG. 4A. The EXOR output with the frame alternating signal FCR signal whose polarity is switched in 1H units is supplied to the NOR gate 48 of the next stage.

The NOR gate circuit 48 outputs the output supplied from the EXOR gate 47 and the EXOR gate 47.
The NOR output with the zero bias control signal ECB for adjusting the output supplied from the reference level to the reference level is supplied to the level shifter circuit 49 of the next stage, and the level shifter circuit 49 is supplied.
Converts the supplied NOR output to a desired voltage level and then supplies it to the transfer gate 50 in the next stage.

The transfer gate 50 includes an inverter circuit 501, an N-type MOS 502a and a P-type MOS 50.
CMOS 502 formed by combining 2b and N
The source side of the CMOS 502 is supplied with the positive drive voltage V1C from the drive power supply circuit 5, and the source side of the NMOS 503 is supplied with the negative drive voltage V3 from the drive power supply circuit 5. To be done. Here, the NMOS is a PMOS 50 when the gate is High.
2P becomes conductive when the gate is low.

Therefore, the transfer gate 50 supplies the positive drive voltage V1C from the CMOS 502 and the "L" level signal from the level shift circuit 49 when the "H" level signal is supplied from the level shift circuit 49. In this case, the negative drive voltage V3 is applied from the NMOS 503 to the signal electrode Yn as a display drive signal. Here, for example, the gradation data is “0”, “1”, “14” and “1”.
When the gradation is 5 ", display drive signals having drive waveforms as shown in FIGS. 3I to 3L are supplied to the signal electrodes Yn, respectively.

As shown in one example in FIGS. 3I to 3L, the drive waveform of the display drive signal in one horizontal scanning period (1H) at all gradations (0 gradation to 15 gradations). Has a rising edge and a falling edge.
Specifically, the signal electrode Yn has “0” gradation, “1” gradation,
When "14" grayscale data and "15" grayscale data are applied, rising and falling (a0 and b0, a1 and b1, a14 and b14, and a) in one horizontal scanning period (1H), respectively.
It has both edges 15 and b15).

FIG. 4 shows the drive waveforms of the scan electrodes Xn when the display drive signals having the drive waveforms shown in FIGS. 3I to 3L are applied to the signal electrodes Yn.

As shown in FIGS. 4B to 4E, when the drive waveform of the display drive signal of each gradation applied to the signal electrode Ym rises and falls, differential waveforms as shown in the figure respectively occur. As a result, a pair of spike noises having opposite polarities are generated in the scan electrodes Xn during one horizontal scanning period (1H). Specifically, the rising and falling edges (a0 and b0, a1 and b1, a14) of the display drive signal at the "0" gradation, the "1" gradation, the "14" gradation, and the "15" gradation. b14 and a15 and b15), a pair of spike noises (c0 and d0, c1 and d1, c14) having different polarities are provided on the scan electrodes.
And d14, and c15 and d15) will occur.

Therefore, in all the gradation levels, the spike noise is canceled during one horizontal scanning period (1H), the effective voltage applied to the liquid crystal is not affected by the spike noise, and the deterioration of the image quality is prevented. Will be able to.

Therefore, as described above, in the conventional liquid crystal display device, the spike noise of the common voltage waveform cannot be completely canceled when the number of signal electrodes having the gradation level of "0" or "15" is large. There was a problem,
In the present embodiment, even when there are many signal electrodes of "0" gradation and "15" gradation, it is possible to completely cancel the spike noise of the scanning voltage waveform and obtain a good image quality. .

It should be noted that in the above-described embodiment, as shown in FIG.
The pulse widths t1 and t2 of the lowest gradation (“0” gradation) and the highest gradation (“16” gradation) of the display drive signal shown in (I) and (L) respectively indicate that the liquid crystal is on or off. That is, it is desirable to set the value so that it does not affect the transmittance. However, when the liquid crystal used for the liquid crystal display panel 2 is a TN liquid crystal, the luminance characteristic thereof does not have a completely linear characteristic as shown in FIG.
Since the slope of the curve is small in the vicinity of off and Von, the pulse intervals t1 and t2 do not have to be extremely small.

In the above embodiment, the pulse width of the display drive signal may have a linear characteristic with respect to the number of gradations, but the luminance characteristic of the liquid crystal used in the liquid crystal display panel 2 is as described above. In addition, since it does not have a completely linear characteristic, a characteristic corresponding to the luminance characteristic may be taken into consideration.

Next, the operation of the embodiment according to the present invention will be described.

When the main power source (not shown) of the liquid crystal display device 1 of the present embodiment is turned on, the power source voltage is supplied to each block shown in FIG. 1 to start the operation of each block and at the same time, not shown. The gradation data and the sync signal are supplied from the signal source to the drive power supply generation circuit 5 and the basic signal generation circuit 8, respectively.

In the drive power supply generation circuit 5, the negative side display drive voltage V3 and the positive side display drive voltage V1C are generated and supplied to the signal side drive circuit 4, and the negative side selection drive voltage V4 and the positive side selection voltage V2 are generated. Is generated and supplied to the scanning side drive circuit 3.

In the basic signal generation circuit 8, the horizontal sync signal (H) included in the sync signal supplied from a signal source (not shown) is used.
sync) and the vertical synchronization signal (Vsync), basic clocks CK1 and CK2 are generated and supplied to the timing signal generation circuit 7 and the gradation data generation circuit 6.

In the timing signal generating circuit 7, the data sampling signal C as shown in FIG. 3B is generated based on the basic clock CK1 supplied from the basic signal generating circuit 8.
KS, a data output signal CKN as shown in FIG.
Gradation creation signals P1 to P as shown in FIGS.
4, a reset signal CR as shown in FIG. 3 (H), a frame alternating signal FCR for inverting and driving the voltage applied to the signal electrode for each scanning electrode of the liquid crystal display panel 2, a zero bias control signal ECB, etc. Various timing signals and control signals are generated and supplied to the signal side drive circuit 4.

In the timing signal generating circuit 7, the scanning side drive control signal CCK is generated based on the basic clock supplied from the basic signal generating circuit 8 and is supplied to the scanning side driving circuit 3.

In the scanning side drive circuit 3, the scanning side drive control signal CCK supplied from the timing signal generating circuit 7 is supplied.
Based on the above, the scanning drive signal obtained by selecting the negative side selection voltage V4 or the positive side selection voltage V2 supplied from the drive power generation circuit 5 is sequentially output to the scanning electrodes X1 to Xm, thereby X1 to Xm are sequentially scanned and driven.

In the signal side drive circuit 4 (its specific configuration is shown in FIG. 2), the timing signal generation circuit 7 to FIG.
A data sampling signal CKS as shown in FIG. 3B, a data output signal CKN as shown in FIG.
Gradation creation signals P1 to P4 as shown in (D) to (G),
A reset signal CR as shown in FIG. 3H and a frame alternating signal FC for inverting and driving a display drive signal applied to each signal electrode Yn of the liquid crystal panel 2 for each scanning electrode Yn.
R, the zero bias control signal ECB, and the negative side display drive voltage V3 and the positive side display drive voltage V1C supplied from the drive power supply generation circuit 5 are latch circuits (D-type flip-flops) 41a1 to 41a4, 42a1 respectively. ~ 42a
4, OR gates 43a1 to 43a4, AND gate 44
And the RS flip-flop 46 (NOR gate 46a,
46b), EXOR gate 47, and NOR gate 4
8, the level shifter 49, and the transfer gate 50, and from the transfer gate 50, corresponding to the gradation data of the display data, for example, FIG.
All gradations (0 to 15
(Gradation), a rising edge and a falling edge are provided once in one horizontal scanning period (1H), and the display drive signals whose polarities are inverted for each scanning electrode are signal electrodes Y1 to Yn.
Is supplied to.

In the liquid crystal display panel 2, the scanning side drive circuit 3
And the scan side drive signal and the display drive signal supplied from the signal side drive circuit 4, the scan electrodes X1 to Xm and the signal electrodes Y1 to Yn are selectively driven to form a drive waveform as shown in FIG. The corresponding gradation display is performed.

In the above-mentioned embodiment, the drive waveform of the display drive signal for driving the signal electrode Yn of the liquid crystal display panel 2 is one horizontal scanning period (1H) for all the gradations (0 gradation to 15 gradations). In (), there is one rise and one fall.

Therefore, as shown in FIG. 4, at all gray levels, at least one set of spike noises having the same magnitude but different polarities can be generated in the scan electrodes within one horizontal scanning period. Spike noise generated in the scan electrodes can be completely canceled out, change in effective voltage between the display drive signal and the scan drive signal can be suppressed, and deterioration of image quality can be prevented.

Further, in the above-described embodiment, the display drive signal has a pulse width that does not affect the transmittance of the liquid crystal at the lowest gradation and the highest gradation. It is possible to prevent deterioration of image quality due to "stringing" or the like without affecting the above.

Furthermore, in the above-described embodiment, since the voltage polarity of the display drive signal applied to each signal electrode is inverted for each scanning electrode, the positions where spike noise is generated can be dispersed. It is possible to further prevent deterioration of image quality.

Although the TN type liquid crystal is used for the liquid crystal display panel in the above-mentioned embodiment, the STN type liquid crystal may be used.

(Second Embodiment) FIG. 6 shows a configuration of a liquid crystal television 11 as an example of a system suitable for applying the liquid crystal display device of the present invention.

The liquid crystal television 11 in FIG. 6 has an antenna 12, a tuner 13, a receiving circuit 14, a synchronizing circuit 15, and an A
/ D converter 16, gradation control circuit 17, controller 1
9, a display control system including an interface circuit 20 and the like, and a liquid crystal module 21 including a signal side driving circuit 4, a scanning side driving circuit 3, a liquid crystal display panel 2, and the like.

The gradation data creating circuit 6 in FIG.
6, and the drive power supply generation circuit 5, the timing signal generation circuit 7, and the basic signal generation circuit 8 in FIG. 1 correspond to the controller 19 or the interface circuit 20 in FIG.

The antenna 12 transmits the received radio wave to the tuner 13
The tuner 13 selects a designated channel in accordance with the tuning control signal TC input from the controller 19, converts the reception radio wave supplied from the antenna 12 into an intermediate frequency signal, and outputs the intermediate frequency signal to the reception circuit 14.

The receiving circuit 14 is composed of an intermediate frequency amplifying circuit, a video detecting circuit, a video amplifying circuit, a chroma circuit, and the like. The intermediate frequency signal input from the tuner 13 is subjected to video detection by the video detecting circuit to perform color detection. The video signal is taken out, the audio signal is taken out from this color video signal and output to an audio circuit (not shown), and the video amplifier circuit amplifies the color video signal and passes it to the chroma circuit. At the chroma circuit, the received color video signal is received. To R,
The G and B color image signals are separated and output to the A / D converter 16.

The synchronizing circuit 15 receives the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync from the received color video signals.
Is output to the controller 19.

The A / D converter 16 is composed of a sampling circuit, a comparator circuit, an encoder circuit and the like (not shown). Functionally, analog signals of R, G, and B are sampled and compared with a reference voltage by a comparator to perform A / D conversion (equal division in the range of RHH to RLL), and then, for example, R, G, and B Convert to digital display data of 3 bits each.

The controller 19 is a CPU (Central Pr
, which controls the operation of the liquid crystal television 11 as a whole. For example, a horizontal synchronizing signal (H
sync) and the vertical synchronization signal (Vsync) to display an image on the liquid crystal display panel 2, generate a sampling clock and supply the sampling clock to the A / D converter 16, and a basic circuit for the internal circuits such as the gradation control circuit 17. Clock CK1,
CK2 and control signals are formed and supplied.

The interface circuit 20 supplies the horizontal synchronizing signal and the vertical synchronizing signal input from the controller 19 to the signal side driving circuit 4 and the scanning side driving circuit 3 of the liquid crystal module 21, respectively, to scan the liquid crystal panel 2. The liquid crystal display panel 2 by driving the signal lines while sequentially scanning the electrodes
Display the image on.

Although the liquid crystal television has been described as an application example of the present invention in the above-described second embodiment, the present invention is not limited to this and is widely applied to other liquid crystal display devices. can do.

[0078]

As described above, in the liquid crystal display device according to the first aspect, the drive waveform of the display drive signal for driving the signal electrodes of the liquid crystal display panel is one horizontal scanning period (1H) at all gradations. In (), the rising and falling edges are provided once each.

Therefore, in all the gradations, at least one set of spike noises having the same magnitude but different polarities can be generated in the scan electrodes within one horizontal scanning period, so that the spike noises generated in the scan electrodes can be completely eliminated. Therefore, it is possible to suppress the change in the effective voltage between the display drive signal and the scan drive signal and prevent the deterioration of the image quality.

According to another aspect of the liquid crystal display device of the present invention, the display drive signal has a minimum gradation and a maximum gradation.
Since each has a pulse width that does not affect the transmittance of the liquid crystal, spike noise can be prevented from occurring in the scan electrodes without affecting the gradation reproducibility.

According to the liquid crystal display device of the third aspect, since the voltage polarity of the display data applied to each signal electrode is inverted for each scanning electrode, the positions where spike noise is generated can be dispersed. Therefore, it is possible to further prevent deterioration of image quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration example of a signal side drive circuit in FIG.

3 is a timing chart showing the operation timing of the signal side drive circuit of FIG.

4 is a waveform diagram showing an example of a signal voltage (segment voltage) waveform and a scanning voltage (common voltage) waveform of the liquid crystal display device of FIG.

FIG. 5 is a brightness characteristic diagram showing the relationship between the effective voltage applied to the TN liquid crystal and the brightness.

FIG. 6 is a block diagram showing a configuration example of a liquid crystal television according to a second embodiment of the present invention.

FIG. 7 is a waveform diagram showing a signal voltage (segment voltage) waveform and a scanning voltage (common voltage) waveform in a conventional liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 liquid crystal display device 2 liquid crystal display panel 3 scanning side drive circuit 4 signal side drive circuit 40 PWM signal generation part 41a1 to 41a4 latch circuit 42a1 to 41a4 latch circuit 43a1 to 43a4 OR gate 44 AND gate 46 RS flip flop 47 EXOR gate 48 NOR Gate 49 Level shifter 50 Transgate circuit 5 Driving power supply generation circuit 6 Grayscale data generation circuit 7 Timing signal generation circuit 8 Basic signal generation circuit 11 Liquid crystal television 12 Antenna 13 Tuner 14 Reception circuit 15 Synchronization circuit 16 A / D converter 17th floor Adjustment control circuit 19 Controller 20 Interface circuit 21 Liquid crystal module

Claims (3)

[Claims] 1. A liquid crystal display panel in which liquid crystal is sealed between a pair of substrates, and a plurality of scanning electrodes formed on one substrate and signal electrodes formed on the other substrate are arranged in a grid pattern to scan. A liquid crystal display device driven by a side driving unit and a signal side driving unit, wherein the signal side driving unit is based on gradation data indicating a gradation level of display data and a gradation control pulse. PWM signal generation means for generating a PWM signal having a pulse width corresponding to data, reset signal generation means for generating a reset signal for resetting the PWM signal every horizontal scanning period, and the PWM signal by the reset signal By resetting every horizontal scanning period, a display drive signal having the same number of rising edges and falling edges within one horizontal scanning period is generated for all gray levels, A liquid crystal display device, comprising: a display drive signal generating unit which is applied to the signal electrode. 2. The liquid crystal display device according to claim 1, wherein the display drive signal has a pulse width that does not affect the transmittance of the liquid crystal at the lowest gradation and the highest gradation. . 3. The signal side driving means further includes a polarity reversing means for reversing the voltage polarity of the display driving signal applied to each signal electrode alternately for each scanning electrode. Or the liquid crystal display device according to item 2.