JPH0414769B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a liquid crystal driving method capable of displaying a plurality of times.

[Prior Art] In recent years, small-sized liquid crystal televisions using liquid crystal display panels have been put into practical use. In the liquid crystal display panel used in this type of liquid crystal television, common electrodes and segment electrodes are arranged in a matrix, and the intersections of the matrix are used as pixels.A scanning signal is supplied to the common electrode, and gradation is applied to the segment electrodes. It is driven according to the effective value of the voltage applied between the common electrode and the segment electrode by supplying a signal. Here, the gradation signal is a signal obtained by pulse width modulating 4-bit digital display data obtained by A/D converting a television video signal, for example, according to gradations from 0 to 15. The technology for displaying multiple gradations on a liquid crystal display using gradation signals is disclosed in detail in, for example, Japanese Patent Application Laid-Open No. 179072/1982, but this will be briefly explained here with reference to FIGS. 1 and 2. Let me explain.

Figure 1 shows the drive waveform for a certain electrode, where φ _f is a frame signal, φ _oH is a timing signal outputted, for example, every four horizontal scanning periods, X ₁ is a common signal, and Y ₁ is a segment signal. , S ₁ is the composite waveform of common signal X ₁ and segment signal Y ₁ (X ₁ −
_Y1 ). Conventionally, the 16-gradation waveform of the segment signal is formed as shown in FIG. 2 with gradations 15 to 0.

In other words, the gradation waveform has a time width of 4H (H is one horizontal period) and its amplitude is changed at four levels of V ₀ , V ₂ , V ₃ , and V ₅ , and gradation 15 is |V It is assumed to be a rectangular wave with an amplitude of ₃ |. And gradation 14 ~
0 selects a pulse signal whose amplitude is |V ₅ | and whose time width gradually increases with respect to the waveform of gradation 15.
Therefore, at gradation 0, it is a rectangular wave with an amplitude of |V ₅ |. In Fig. 1, the liquid crystal display panel has a common signal _X1 and a segment signal
It is driven by the composite waveform S ₁ of Y ₁ , for example
The gradation is 0 at the timing of t ₁ and t ₁ ′, and the gradation is 0 at the timing of t ₂ and t ₂ ′.
15, t ₃ and t ₃ ', gradation 0 is displayed, t ₄ is 8, and t ₄ ' is gradation 15.

[Problems to be Solved by the Invention] The liquid crystal display panel is driven as described above, but in the conventional liquid crystal driving method, the gradation
The waveform of gradation 15 and gradation 0 does not change at all during the time width of 4H, so if gradation 15 and gradation 0 continue,
The low _level section (t ₁ ′,
As shown in the liquid crystal waveform at t ₂ ',...), the driving frequency becomes lower.

Since liquid crystals are highly frequency dependent, display quality deteriorates when the driving frequency changes from the optimum frequency.
For example, if you have set the optimal drive frequency assuming that the entire screen is displayed approximately half white and half black, if the drive frequency decreases due to continuous white or black as described above, the display Characteristics deteriorate. This deterioration in display characteristics appears in the form of trailing or color unevenness in the case of color.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a liquid crystal driving method that can keep the frequency of a liquid crystal driving signal constant, prevent color unevenness, and obtain high display quality.

[Means for Solving the Problems] In order to achieve the above object, the present invention arranges common electrodes and segment electrodes in a matrix, uses the intersections of the matrix as pixels, supplies a scanning signal to the common electrodes, and connects the segments to the common electrodes. A liquid crystal driving method in which a gradation signal in which display data is pulse width modulated according to the gradation is supplied to the electrodes, and the liquid crystal display panel is driven according to the effective value of the voltage applied between the common electrode and the segment electrode. When the time required to determine either of the minimum gradation and the maximum gradation is defined as one gradation interval, the gradation signals corresponding to the minimum gradation and the maximum gradation are defined as the one gradation interval. The present invention is characterized in that a means for inverting the polarity at least once is provided in the LCD panel, so that the number of inversions of the voltage applied to the pixels of the liquid crystal display panel during one frame period is constant regardless of the gradation.

[Function] In other words, when creating a gradation signal by pulse width modulating display data, the polarity of the gradation signal is always reversed once within one gradation interval, so even at the minimum gradation, the pulse of the gradation signal is Since the duty is not 0% and the duty of the pulse is not 100% even at the maximum gradation, the number of inversions within one frame period is constant no matter what gradation signals are combined, and the drive frequency is kept constant. It will be done.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. In FIG. 3, numeral 11 is a 4-bit latch circuit to which 4-bit display data D ₁ to _{D 4} are input. The latch circuit 11 outputs display data _D1 to _D4 .
is read in synchronization with the timing signal φ _oH and applied to the OR circuits 12 ₁ to 12 ₄ . Also, this OR circuit 12
Luminance modulation pulses P ₁ to _{P 4} are input to ₁ to 12 ₄ , respectively.

The outputs of the OR circuits 12 ₁ to 12 ₄ are inputted to the data input terminal D of the D-type flip-flop 15 via the NAND circuit 13 and the inverter 14. This flip-flop 15 has a clock terminal.
Reads the input data in synchronization with clock pulse ₂ input to CK, and outputs the Q side output to latch circuit 1.
Input to reset terminal R of 6. A timing signal φ _oH is input to the set terminal S of the latch circuit 16 and the reset terminal R of the flip-flop 15 .

The latch circuit 16 includes a pair of NOR circuits 17
a, 17b, and the NOR circuit 1
The output of 6a is sent to latch circuit 18. This latch circuit 18 latches input data in synchronization with clock pulse φ ₂ and outputs it to a decoder 19. Further, a frame signal φ _f is input to this decoder 19 . The decoder 19 performs different decoding operations depending on whether the frame signal φ _f is at a high level or a low level, and outputs a “1” signal to any of the output lines l ₁ to _{l 4} to output a “1” signal to the gate. Performs gate control of circuits _G1 to _G4 .

The gate circuits G ₁ to _{G 4} have liquid crystal drive voltages V ₅ ,
It selects and outputs V ₂ , V ₃ , and V ₀ , and the output is sent to a liquid crystal display panel (not shown) as a segment signal Y ₁ .

Next, the operation of the above embodiment will be explained. When 4-bit data D ₁ to _{D 4} specifying the gradation is sent, this data D ₁ to _{D 4} is latched by the latch circuit 11 in synchronization with the timing signal φ _oH shown in FIG. The data D ₁ -D ₄ latched by the latch circuit 11 are sent to the NAND circuit 13 via the OR circuits _{12 1} -12 ₄ together with the brightness modulation pulses P ₁ -P ₄ .

The luminance modulation pulses P ₁ to _{P 4} are obtained by sequentially frequency-dividing the pulse signal P ₁ by duty as shown in FIG _{. 5} . In this case, eight reference pulses P ₁ are generated for each period of the timing signal φ _oH , but when the eighth pulse rises, the timing signal φ oH is applied after a minute time and the timing signal φ _oH is reset. The frequency is set to . That is, the brightness modulation pulse P ₁ is the timing signal φ _oH
A thin pulse is generated just before the signal is applied.

However, now, the display data D ₁ to _{D 4} are the gradation
If "1111" specifying 15 is latched in the latch circuit 11, the output of the latch circuit 11 becomes all "1", and the output of the NAND circuit 13 becomes "0" and is inputted to the inverter 14. Therefore, the output Ui of the inverter 14 becomes "1" in synchronization with the rise of the timing signal φ _oH , as shown in FIG.
and is input to the flip-flop 15.

On the other hand, the latch circuit 16 receives the timing signal φ _oH
The output Ti becomes "1". The output Ti of the latch circuit 16 is latched by the latch circuit 18 in synchronization with the clock _φ2 , and sent to the decoder 19 as a gradation signal Si as shown in FIG.
sent to. Next, when the timing signal φ _oH becomes low level, the output Ui of the inverter 14 becomes
It is read into the flip-flop 15 in synchronization with the clock φ ₂ , and its Q-side output becomes "1" to provide a reset signal R to the latch circuit 16. As a result, both the output Ti of the latch circuit 16 and the output Si of the latch circuit 18 become "0". As a result, the gray scale signal
As shown in FIG. 4, Si becomes a pulse signal having the same time width as the timing signal φ _oH .

That is, when display data of 15 gradations is given, the gradation signal Si generates a thin pulse signal a at the beginning of one gradation section determined by the timing signal φ _oH , as shown in FIG. This gradation signal Si is
It is sent to the decoder 19 together with the frame signal φ _f and decoded. Then, the gate circuits G ₁ to _{G 4} are controlled by the output of this decoder 19, and V ₅ , V ₃ ,
The voltages V ₂ and V ₀ are selected and sent to the liquid crystal display panel as a segment signal Y ₁ .

Furthermore, if "0000" specifying gradation level 0 is latched in the latch circuit 11 as the display data D ₁ to _{D 4} , the output of the latch circuit 11 will be all "0", and only the brightness modulation pulses P ₁ to P ₄ will be output. The output of the NAND circuit 13 is determined by . That is, at the timing when all of the brightness modulation pulses P ₁ to _{P 4} become "1", the output of the NAND circuit 13 becomes "0" and the output of the inverter 14 becomes "1", which are read into the flip-flop 15. The above brightness modulation pulses P ₁ to _{P 4}
The timing when all the values become "1" is at the end of one gradation interval, as shown in FIG. Therefore, when the gray level is 0, the gray level signal Si rises in synchronization with the clock _φ2 when the timing signal φ _oH is applied.
A falling signal immediately before the next timing signal φ _oH is applied, that is, a pulse signal b having the opposite polarity to the pulse signal a of gray level 15 is generated at the end of one gray level section as shown in FIG.

Similarly, display data as shown in Figure 5.
_Gradation signals Si (15 _~
0) is obtained. That is, as shown in FIG. 6, the signal waveforms for gradations 15 to 0 fall once within the gradation interval and have the same frequency at each gradation.

FIG. 7 shows specific liquid crystal waveforms using the signal waveforms of gradations 15 to 0, that is, common signal X ₁ , segment signal Y ₁ , and composite waveform S ₁ (X ₁ −Y ₁ ). be. As is clear from Figure 7, the gradation
No matter how 15 to 0 are combined, a liquid crystal drive signal of the same frequency is always obtained.

In other words, when creating a gradation signal by pulse width modulating the display data, the polarity of the gradation signal is always inverted once within one gradation interval, so even at the minimum gradation, the duty of the pulse of the gradation signal is 0. % and the duty of the pulse is not 100% even at the maximum gradation, so no matter how the gradation signals are combined, the number of inversions within one frame period is constant, and the drive frequency is kept constant. It will be done.

[Effects of the Invention] As described above, according to the present invention, common electrodes and segment electrodes are arranged in a matrix,
The intersection of the matrix is used as a pixel, and a scanning signal is supplied to the common electrode, and a gradation signal obtained by pulse width modulating the display data according to the gradation is supplied to the segment electrode, and between the common electrode and the segment electrode. In a liquid crystal driving method that drives a liquid crystal display panel according to the effective value of an applied voltage, when the time required to determine one of the minimum to maximum gradations is defined as one gradation section, A means is provided for inverting the polarity of the grayscale signal corresponding to the minimum grayscale and the maximum grayscale at least once within the one grayscale interval, and the number of times the voltage applied to the pixels of the liquid crystal display panel is reversed during one frame period is increased. Since it is constant regardless of the gradation, the number of inversions within one frame period is constant no matter how any gradation signal is combined.
The driving frequency is kept constant. Therefore, even if a liquid crystal with high frequency dependence is used, it can always be driven at the optimum frequency, and deterioration of display characteristics due to a decrease in the driving frequency can be prevented.

[Brief explanation of drawings]

FIG. 1 is a timing chart showing a conventional liquid crystal driving method, FIG. 2 is a diagram showing a 16-gradation waveform of the liquid crystal driving signal in FIG. 1, and FIGS. 3 to 7 show an embodiment of the present invention. Fig. 3 is a circuit configuration diagram showing a segment signal generation circuit, Figs. 4 and 5 are timing charts for explaining the operation, Fig. 6 is a 16-gradation waveform diagram from gradation 15 to 0, FIG. 7 is a diagram showing specific liquid crystal driving waveforms. 11...Latch circuit, 15...Flip-flop, 16, 18...Latch circuit, 19...Decoder.

Claims (1)

[Claims] 1. Common electrodes and segment electrodes are arranged in a matrix, and the intersections of the matrices are used as pixels, and a scanning signal is supplied to the common electrode, and display data is pulsed to the segment electrodes according to the gradation. In a liquid crystal driving method in which a width-modulated gray scale signal is supplied to drive a liquid crystal display panel according to the effective value of the voltage applied between a common electrode and a segment electrode, any of the gray scales from the minimum gray scale to the maximum gray scale is When the time required to determine the
The gradation signal corresponding to the minimum gradation and maximum gradation is
A liquid crystal driving method characterized in that a means for inverting polarity at least once within a gradation interval is provided, and the number of inversions of a voltage applied to a pixel of a liquid crystal display panel during one frame period is constant regardless of the gradation. .