JPH0628864Y2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image display device using a liquid crystal display panel or the like as a display unit.

[Prior Art and its Problems] Conventionally, an image display device in a liquid crystal television or the like is configured as shown in FIG. In the figure, reference numeral 1 is an A / D controller, which is provided with an A / D converter 2 inside and which converts an image signal (analog signal) sent from a preceding amplification circuit (not shown) into, for example, 3-bit digital data D1. ~ D3
And outputs to the segment side driver 3. The segment-side driver 3 is provided with an n-stage decoder 4 and an exclusive OR circuit (hereinafter abbreviated as EX OR circuit) 5 ₁ , 5 ₂ , ... 5 _n . The decoder 4
Generates a pulse width modulation (PWM) signal according to the data D1 to D3 from the A / D controller 1 and outputs the output signal of each stage to one input end of the EX OR circuit 5 ₁ as will be described later in detail. input. Further, the EX OR circuits 5 _{1 to} 5 _n
The field signal φ _F is input to the other input terminal of the.
Then, the output signals of the EX OR circuits 5 _{1 to} 5 _n are sent to the liquid crystal display unit 6 as segment drive signals. The liquid crystal display unit 6 includes a segment side voltage selection circuit, a common side voltage selection circuit, and a liquid crystal display panel. The liquid crystal drive voltage is selected in accordance with the segment drive signal from the segment side driver 3 and the segment of the liquid crystal display panel is selected. Display drive the electrodes. Further, the liquid crystal display unit 6 selects the common drive voltage in the common side voltage selection circuit according to the common drive signal sent from the common side driver (not shown), and sequentially selects the common electrodes of the liquid crystal display panel. To drive.

FIG. 4 shows a detailed structure of one stage of the decoder 4. In the figure, 11 is a 3-bit register which reads the data sent from the A / D controller 1 in synchronization with a clock pulse φsi having the same frequency as the sampling frequency and inputs it to the 3-bit register 12. This register 12 stores the data given from the register 11 as 1
The pulse signals P1 and P for generating gradation signals are latched in synchronization with the latch timing signal φ _N output for each scanning period.
NAND circuit through OR circuits 13a to 13c together with 2, P3
Enter in 14. The pulse signals P1, P2 and P3 are 1
The pulse signal P1 that divides the scanning period into seven is sequentially divided to generate P2 and P3. NAND circuit 14 above
Is configured to open the output gate while the timing signal φc is applied, and the output signal is input to the reset terminal R of the flip-flop 15. The flip-flop 15 is composed of a pair of NAND circuits 15a and 15b, and a timing signal φ _N is sent to the inverter 16 at the set terminal S.
Input through the NAND circuit 14 to the reset terminal R.
Output signal is input. Then, the output of the flip-flop 15 is sent as an output signal of the decoder 4 to the EX OR circuit 5i together with the field signal φ _F. The output signal of the EX OR circuit 5i is sent to the liquid crystal display unit 6 as a segment drive signal, and the segment side voltage selection circuit
Entered in 17. The voltage selection circuit 17 selects the liquid crystal drive voltages V1 and V3 according to the segment drive signal output from the EX OR circuit 5i and supplies the liquid crystal drive voltages V1 and V3 to the segment electrodes.

In the above configuration, the common drive signal supplied to the liquid crystal display unit 6 is used to drive the liquid crystal display panel by alternating current.
As shown in FIG. 3A, the data is inverted and provided for each field. On the other hand, the image data D1 to D3 given from the A / D converter 2 to the decoder 4 are once written in the register 11 and then latched in the register 12 in synchronization with the timing signal φ _N. At this time, the flip-flop 15 is set by the timing signal φ _N. And this register
Timing signal P1 based on the data latched in 12
~ P3 determines the output timing of the NAND circuit 14, and the output signal of the NAND circuit 14 resets the flip-flop 15. That is, as shown in FIG. 5B, the time width of the output signal of the flip-flop 15 (gradation signal time width) is determined according to the latch data of the register 12. The output signal of this flip-flop 15 is E
In the X-OR circuit 5i, as shown in FIG. 5 (d), inversion control is performed in synchronization with the field signal φ _F (FIG. 5 (c)), and it is sent to the liquid crystal display unit 6 as a segment drive signal.

When AC driving the liquid crystal display panel as described above, conventionally, EX OR circuits 5 _{1 to} 5 _n are provided on the output side of the decoder 4 to invert the segment drive signal for each field. Therefore, a large number of EX OR circuits 5 _{1 to} 5n, that is, the same number as the number of segment electrodes of the liquid crystal display unit 6, are required, and the number of circuit elements in the segment side driver 3 becomes very large, resulting in a large chip area. There was a problem.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image display device capable of reducing the chip area by simplifying the circuit configuration of the segment side driver.

SUMMARY OF THE INVENTION The present invention is, in an image display device in which common electrodes and segment electrodes are arranged in a matrix, means for supplying N-bit digital data, and N-bit digital data supplied from this means. Each bit is input to one input terminal and the other input terminal is commonly input with an alternating signal that is inverted at a predetermined cycle. N exclusive OR circuits and the common electrode are inverted by the alternating signal. Grayscale of the segment electrodes based on a segment drive signal, which comprises a driving means and an ON waveform and an OFF waveform obtained by PWM-modulating the output of the exclusive OR circuit, and the grayscale is determined by the ratio of the ON waveform and the OFF waveform. Display driving means, and is ON when the PWM modulated segment drive signal is non-inverted and inverted.
The feature is that the order of the waveform and the OFF waveform is reversed.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 21 is an A / D controller, which has an A / D inside.
The converter 22 and the EX OR circuits 23a to 23c are provided, and the image signal (analog signal) sent from the amplifier circuit (not shown) at the previous stage is supplied from the A / D converter 22 to, for example, 3-bit digital data D1 to D3. EX or circuits 23a-23c
To enter. In addition, the EX OR circuits 23a to 23c include
The field signal φ _F is input and its output signal is sent to the segment side driver 24. The segment side driver 24 is provided with an n-stage decoder 25. The decoder 25 is an EX OR circuit 23a of the A / D controller 21.
23c, pulse width modulation signals are created according to the data D1 to D3 sent to the liquid crystal display unit 26 as segment drive signals. The liquid crystal display unit 26 includes a segment side voltage selection circuit, a common side voltage selection circuit, and a liquid crystal display panel. The liquid crystal drive voltage is selected according to the segment drive signal from the segment side driver 24 to drive the segment electrodes for display. You Further, the liquid crystal display unit 26 selects the common drive voltage in the common side voltage selection circuit according to the common drive signal sent from the common side driver (not shown), and sequentially selects the common electrodes of the liquid crystal display panel. To drive.

Next, the operation of the above embodiment will be described. The common drive signal supplied to the liquid crystal display unit 26 is inverted and provided for each field as shown in FIG. 2A in order to AC drive the liquid crystal display panel. On the other hand, the A / D controller 21 converts the image signal sent from the preceding amplifier into the A / D converter 22.
Are converted into 3-bit image data “000” to “111” and output to the segment side driver 24 via the EX OR circuits 23a to 23c. In this case, the EX OR circuit 23a-
23c is inverted and controlled for each field by the field signal φ _F shown in FIG. 2 (b). In this case, the first
In the field, if the field signal φ _F is low level, the image data D output from the A / D converter 22
1 to D3 are sent as they are to the segment side driver 24 via the EX OR circuits 23a to 23c. However, when the field signal φ _F becomes high level in the second field, A /
The image data D1 to D3 output from the D converter 22 are E
It is inverted by the X-OR circuits 23a to 23c and sent to the segment side driver 24. For example, if the image data D1 to D3 output from the A / D converter 22 is "101", it is inverted into "010" data by the EX OR circuits 23a to 23c. Thereafter, the image data D1 to D3 output from the A / D converter 22 in the same manner are inverted by the EX OR circuits 23a to 23c for each field and sent to the segment side driver 24, and the decoder 25 in FIG. Pulse width modulation is performed as shown in FIG. The waveform of the signal output from the decoder 25 has the same gradation as that of the segment drive signal waveform inverted for each field as in the conventional case, and is equivalent. Therefore, by outputting the signal output from the decoder 25 to the liquid crystal display unit 26 as a segment drive signal, the liquid crystal display panel in the liquid crystal display unit 26 can be AC-driven. However, as is clear from comparison between FIG. 5 (d) and FIG. 2 (c), in the past, the drive waveform of ON waveform → OFF waveform was used for both the first field and the second field. According to the first field, the ON waveform is changed to the OFF waveform, and the second field is changed to the OFF waveform →
A drive waveform called an ON waveform forms a pair. Actually, a whisker appears at the rising edge of the drive waveform, which causes the stringing of the display, but if the drive waveform is paired with non-inversion and inversion, the beard cancels each other out. It has the effect of reducing the string pulling out in the direction.

In the above embodiment, the television image signal is converted into an A / D converter.
Although the case where the image data is converted into 3-bit image data by 22 has been described, the conversion into image data having another number of bits, for example, 4-bit, can be performed in the same manner as the above embodiment.

[Advantage of Invention] As described in detail above, according to the present invention, the image signal is
Since the D-converted digital data is inverted by an alternating signal which is inverted at a predetermined cycle, and the common electrode is driven to be inverted by the alternating signal, the number of exclusive OR circuits for inversion is greatly reduced. You can Furthermore, since the order of the ON waveform and the OFF waveform is reversed between the non-inversion and the inversion of the PWM-modulated segment drive signal, threading can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an image display device according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of FIG. 1, and FIG. 3 is a conventional image display device. FIG. 4 is a block diagram showing a circuit configuration, FIG. 4 is a circuit configuration diagram showing details of the decoder in FIG. 3, and FIG. 5 is a signal waveform diagram for explaining the operation of FIG. 3 and FIG. 21 ... A / D controller, 22 ... A / D converter, 23a-23
c ... Exclusive OR circuit (EX OR circuit), 24 ...
Segment side driver, 25 ... Decoder, 26 ... Liquid crystal display section.

Claims (1)

[Scope of utility model registration request] 1. In an image display device in which common electrodes and segment electrodes are arranged in a matrix, a means for supplying N-bit digital data and each bit of the N-bit digital data supplied from this means are respectively provided. N exclusive OR circuits which are commonly input to one of the input terminals and to which the alternating signal which is inverted at a predetermined cycle is commonly input to the other input terminal, and means for inverting and driving the common electrode by the alternating signal. Decoding means for PWM-modulating the output of the exclusive OR circuit to output a segment drive signal having an ON waveform and an OFF waveform and having a gradation determined by the ratio of the ON waveform and the OFF waveform, and output from this decoding means. The segment electrodes are gradation-display-driven based on the PWM-modulated segment drive signal. Comprising the stage, the image display apparatus characterized by order of the ON waveform and OFF waveform in the PWM modulated segment drive signal and the time reversed and the non-inverting time was set to be opposite.