JPS63169691A - Liquid crystal driving - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a liquid crystal driving method that utilizes a liquid crystal as an electric shutter and is suitable for obtaining a gradation display image in combination with back illumination.

2. Description of the Related Art In general, if a DC voltage is applied to a liquid crystal for a long period of time, the liquid crystal will be destroyed due to electrochemical changes, so an AC voltage is usually applied to control the light transmittance. To display halftones using a liquid crystal (1> Control the voltage of the applied AC signal.

C) The voltage of the applied AC signal is held constant and the application time is controlled.

Three methods are being used.

(Method 11 is a method in which the polarity of the gradation control analog signal is reversed at a certain period, and the average DC component is set to zero to drive the liquid crystal.This method drives the liquid crystal with an analog signal, but currently Easy to digitize and convert to IC (2)
Since method (2) is commonly used, method (2) will be explained in detail.゛Figure 3 shows the driving voltage waveform of the electrode in the conventional liquid crystal driving method, and the period T,
It is driven by a square wave voltage with an inter-electrode voltage of ±V.

As shown in FIG. 4, 1.2.3 is a schematic diagram of a liquid crystal device, 1 and 3 are (liquid crystal driving) electrodes, and 2 is a liquid crystal sealed between electrodes 1 and 3. Further, in Fig. 3, 11 is a square wave (voltage) with a period T, a duty of -50%, and a voltage that oscillates between +V volts and O volts, and this voltage (a)
Suppose that is applied to the electrode 3. When applying a voltage exactly the same as the square wave 11, such as the square wave 12 in w), to the electrode 1 facing gold, the difference voltage (C) between the liquid crystal electrodes is 11-12.
= O, no driving voltage is applied to the liquid crystal, the light transmittance is small, and a black display is produced (the display is determined by the arrangement of the polarizing plates combined with the liquid crystal, but here the polarizing plates are arranged in this way). Next, when a voltage (d) such as a reverse phase square wave 13 whose phase is different from the square wave 11 by 180 degrees is applied to the electrode 1, the difference voltage (e) applied to the liquid crystal is 1l-13=(
±V), resulting in a white display.Only the phase of the 0 electrode 1 is a square wave 11 at a certain angle α (0° and α<180'). Compared to the case of No. 13, the liquid crystal 2 is not sufficiently driven, resulting in halftone display.

FIGS. 4 and 5 show circuit blocks and waveforms for driving as shown in FIG. 3. In FIG. 3, 21 is a gradation signal input, lla is a square wave generator that generates a square wave with a period T and a duty of 50, and 11 is a square wave as its output waveform. It corresponds to wave 11 and is applied to liquid crystal electrode 3.

22a is a pulse width modulator whose pulse width is changed by the tone signal input 21, with the rising and falling edges of the square wave 11 generated by the square wave generator 11a being the rising edges, and 22 is its modulation output. Reference numeral 23 denotes an exclusive OR circuit for performing an exclusive OR operation, which obtains an exclusive OR output 24 from the modulation output 22 and square wave 110 input, and the output 24 is applied to the liquid crystal electrode 1. As shown in FIG. 5 (the modulation output 22 of the pulse width modulator 22a is t□, t2. t4...
..., and its pulse width changes depending on the input gradation signal 21 (tl, t3... changes)
It is a pulse width modulated pulse, and its period is 1/2T. At this time, the exclusive OR output 24 of the modulation output 22 and the square wave 11 has the same period as the square wave 11, and the phase is the gradation signal 2
1, that is, a signal obtained by phase-modulating the square wave 11, which is the same signal as the phase-shifted square wave 14 in FIG.

In this way, voltage signals that differ only in phase depending on the gradation are transmitted to the liquid crystal display 2.
It is possible to drive the liquid crystal 2 to display gradation by applying it between the two electrodes 1 and 30.

Problems to be Solved by the Invention However, according to the conventional gradation display drive described above, there was a problem in that the operating frequency of the pulse width modulator 22a was extremely high. For clarity, a more detailed configuration of the pulse width modulator 22a is shown.

As another example, as shown in FIG. 6, the input gradation signal 21 is made into a 6-bit binary digital signal data string and is input into the memory 33a as a 6-bit parallel data string. The memory 33a stores one data (six pits) in the input data string, and the stored data is pulse width modulated and becomes a modulated output 22 during the period (''/2 T ) shown in FIGS. The operation of each block in this case is as follows.That is, the square wave 11 of the pulse generated by the square wave generator 11a resets and starts the counter 32a at the rising and falling edges, and at the same time, the frequency multiplier 11a resets and starts the counter 32a. 31a
to drive. When the gradation of the signal is 6 bits (64 gradations), the frequency multiplier 31a multiplies the frequency of the input square wave 11 by 128 so that the counter 32a counts 64 in 1/2T period. The output is set to 31. memory 3
3a also reads out data in synchronization with the counting operation of color/reader 32a, supplies data output 33 to comparator 34a, and compares it with counter output 32. Data output 3
If the value of 3 is dog, counter output 32 is data output 3
It takes a corresponding amount of time to reach the value of 3, and since the value of the modulated output 22 changes at the instant when the data output 33 = the counter output 32, it becomes a pulse width modulated signal.

The above is a case where one piece of data is stored in the memo 1, 133a and the pulse width is modulated during the bow T period.In this case, as explained above, the counter 32a, the memo! The operating frequency of J 33a is 128 times that of square wave 11. Actually the memory 33a
This frequency becomes even higher because it stores a large amount of data. Assuming a television signal, the number of stored data is 300.000 out of 480 x 640. T =
If it is 33.3m5ec (30Hz), the frequency of the multiplier output 310 is 30 x 128 x 300,0
00 = 1,152 (MHz), and it is quite difficult to realize the circuit, resulting in a complicated circuit configuration.

The present invention eliminates the drawbacks of the conventional example, and aims to provide a liquid crystal driving method that can significantly lower the memory operating frequency.

Means for Solving the Problems In order to achieve the above object, the present invention has a digital memory consisting of a plurality of bit planes that temporarily stores digital drive signals for driving a liquid crystal, reads signals from the digital memory, When driving the liquid crystal with the read signal, the signal is read from the digital memory for each bit plane, and a voltage controlled according to the weighting of the read bit plane is applied to the liquid crystal R by using the read signal. It is configured to drive a liquid crystal.

Effect: Therefore, according to the present invention, there is no need to use a high operating frequency as in the conventional case, and the circuit configuration can be simplified.

EXAMPLES Below, the liquid crystal driving method of the present invention will be explained with reference to FIGS. 1 and 2. To simplify the explanation, the following explanation will be given assuming that the display gradation is 6 bits (64 gradations) as an example.

In FIG. 1, 21 is a 6-bit gradation signal input, 42a is a memory that temporarily stores the signal, 43a is a voltage generator that generates a weighted voltage using a pit plane, and 11 is a pulse-shaped square wave (with period T). voltage) and is the same as in FIGS. 3 and 5. 41 is an output 41a which multiplies the pulse frequency of the square wave 11.

41b, 41C are obtained from the multiplier, 44a is the memory 42a
44 is a switch output 45a which switches and sequentially outputs the output signal 42 from the bit plane for each bit plane. 45 is a switch output 46 which switches the weighted voltage by the pit plane in synchronization with the switch 44a.
a is a switch for turning on and off the weighting voltage 43, 4
6 is a switch output, 47a and 48a are exclusive OR circuits, 47.48 is an exclusive OR output, and 49a is an inverter. The same reference numerals as in other FIGS. 1 to 3 represent the same names.

In FIG. 1, the 6-bit gradation signal 21 as an example is written to the memory 42a by writing pulses 408K to 42a-s (MSB) to 42a-0 for each bit plane, respectively.
(LSB). Further, the square wave 11 with period T is supplied to a frequency multiplier 41 to obtain pulse-like multiplier outputs 41a, 41b, 41C synchronized with period T. The cycle of the borrow output 41a differs depending on the number of data handled in the period T. The output 41b is connected to the switch 44a.

45a, and when the number of data handled in the period T is one, the switch output 44 and the switch output 44, which are signals in which respective bit plane signals are selected at intervals of 04 as shown in FIG. A stepped voltage 45 is obtained for weighting the pit plane in synchronization with the weighting voltage 45. The weighting voltage is generated by a voltage generator 43a, and the weight voltage v5 (MSB) to vO corresponding to each pit plane is obtained.
(LSB) Switch with switch 45a, (d
), a stepped voltage 45 is obtained. The wX value of the liquid crystal 2 is generally proportional to the effective value of the applied voltage.
' 2 'h, V4 = v'2 V3,...
It is convenient to determine the weighting voltages v5 to vO based on the relationship V1=&2Vo. The weighted voltages v5 to vO in the stepped voltage 45 are turned on and off by the switch 46a according to corresponding bit plane signals, respectively.
When a is ON, the phase between liquid crystal electrode 1 and electrode 3 is 180°.
Differently, in OFF, a high frequency wave is applied in which the voltage of period 14 of the same phase sequentially changes to weighted voltages v5 to Vo. 41
C is a pulse-like borrowing output with a period T/6 (for 6 bits) for operating the exclusive OR circuits 47a and 48a. Output ff of exclusive OR circuits 47a and 48a
), (g), (h) are step voltages of fdl, (el) where the voltage is applied to one input terminal 45°46
, and is controlled in an exclusive OR manner by the borrowed output 41G of the other input terminal signal, and outputs a 47°48 signal as an exclusive OR output. Since the drive voltage applied between the electrodes 1.3 of the liquid crystal 2 is the difference between the exclusive OR outputs 48.47, when the switch 46a is ON during all the periods of weighted voltages v5 to VO, the voltage on the liquid crystal 2 is ±. A pulse with a period T of v5°±v4 to ±Vo and 4 is applied for one cycle during the period T, and the OFF
Then the applied voltage becomes zero.

With this type of driving method, there is no need for pulse width modulation as in the conventional example, so when the number of data stored in the memory is one, the operating frequency of the Memo 'J42a is 1101 times the square wave, that is, 300,000 in 480 x 640. So, this is T=33
．． At 3m5ec (30Hz), the frequency is approximately 9MHz, which is '/128 of the conventional example. Furthermore, when comparing the number of data of the output signal, the modulation output 22 in Fig. 5 and the stepped voltage 4 in Fig.
6, the ratio of the number of data is 128:1.

As described in detail, according to the present invention, when obtaining a digital drive signal for a liquid crystal, it is temporarily recorded in a digital memory having a plurality of bit planes, and when read out, a predetermined weight is applied to each bit plane. garnish,
Since the obtained voltage is applied or not applied to the liquid crystal, it is possible to significantly reduce the operating frequency of the pulse width modulator, which has the advantage of greatly simplifying signal transmission circuits, signal processing circuits, etc. has.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a main part of a drive circuit applied to a liquid crystal driving method according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the same drive circuit, and FIG. 3 is a conventional liquid crystal drive method. Figure 4 is a block diagram showing the configuration of a conventional liquid crystal drive circuit, Figure 5 is a waveform diagram explaining the operation of the circuit, and Figure 6 shows the main points of the circuit. FIG. 1.3... Electrode, 2... Liquid crystal, 11... Square wave,
21... Gradation signal input, 41a... Frequency multiplier, 42a... Memory, 43a... Voltage generator, 4
4a +45a, 46a...Switch O Name of agent Patent attorney Toshi Nakao and 1 other person 1st
Figure 3 Figure 5-tJtt u t3f4

Claims (1)

[Claims] To drive the liquid crystal, digital drive signals are temporarily stored in a digital memory consisting of multiple bit planes,
By reading the digital drive signal from the digital memory for each bit plane, obtaining a drive voltage controlled according to the weighting of the read bit plane using the read signal, and applying or not applying the drive voltage to the liquid crystal. A liquid crystal driving method that drives a liquid crystal.