JPH0711746B2 - LCD driving method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving method which utilizes liquid crystal as an electric shutter and is suitable for obtaining a combination gradation display image with its back illumination.

2. Description of the Related Art In general, when a direct current voltage is applied to a liquid crystal for a long time, the liquid crystal is destroyed by an electrochemical change. Therefore, an alternating voltage is usually applied to control the light transmittance. To display halftones using liquid crystal (1) Control the voltage of the applied AC signal.

(2) The voltage of the applied AC signal is kept constant and the application time is controlled.

There are two methods.

The method (1) is a method of driving the liquid crystal by inverting the polarity of the gradation control analog signal at a certain cycle and setting the average DC component to zero. This method drives the liquid crystal with an analog signal, but at present, the method (2), which is easy to digitize and IC, is commonly used. Therefore, the method (2) will be described in detail.

FIG. 3 shows a drive voltage waveform of electrodes in a conventional liquid crystal drive method, which is driven by a square wave voltage having a period T and an inter-electrode voltage of ± V.

As shown in FIG. 4, 1, 2 and 3 are schematic views of the liquid crystal device,
Reference numerals 1 and 3 represent (liquid crystal driving) electrodes, and 2 represents liquid crystal enclosed between the electrodes 1 and 3. Further, in FIG. 3, reference numeral 11 denotes a period T, a duty of 50%, and a square wave (voltage) which oscillates + V volt and O volt, and this voltage (a) is applied to the electrode 3. The square wave of (b) is applied to the opposite electrode 1
When a voltage exactly the same as that of the square wave 11 is applied as in 12, the difference voltage (c) between the liquid crystal electrodes becomes 11-12 = 0, and no drive voltage is applied to the liquid crystal and the light transmittance is small and a black display is obtained. (Display is determined by the arrangement of the polarizing plate combined with the liquid crystal, but here the polarizing plate is arranged in this way). Next, when a voltage (d) such as a reverse-phase square wave 13 whose phase is different from that of the square wave 11 by 180 ° is applied to the electrode 1, the differential voltage (e) applied to the liquid crystal becomes 11-13 = {± V} and white display is performed. Becomes Electrode 1
At a certain angle α (0 ° <α <180
Applying a phase-shifting square wave 14 (f) that is different by only °), the difference voltage (g) applied to the liquid crystal becomes Therefore, unlike the case of 11-13, the period of O volt is generated, so that the liquid crystal 2 is not sufficiently driven as compared with the case of the anti-phase square wave 13 and half-tone display is performed.

FIGS. 4 and 5 show circuit blocks and waveforms for performing the drive shown in FIG. In FIG. 3, 21 is a gradation signal input, 11a is a square wave generator that generates a square wave with a period T and a duty of 50%, and 11 is a square wave as its output waveform. Corresponding to the wave 11, it is applied to the liquid crystal electrode 3. Reference numeral 22a is a pulse width modulator whose pulse width is changed by the gradation signal input 21 with the rising and falling edges of the square wave 11 generated by the square wave generator 11a as the rising edge, and 22 as its modulation output. An exclusive-OR circuit 23 executes an exclusive-OR operation, and an exclusive-OR output 24 is obtained from the modulation output 22 and the input of the square wave 11, and the output 24 is applied to the liquid crystal electrode 1. Fifth
As shown in the figure, the modulation output 22 of the pulse width modulator 22a is t ₀ , t ₂ , t
_The pulse width modulation pulse starts at ₄ ... And its pulse width changes according to the input gradation signal 21 (t ₁ , t ₃ ... Change), and its period is 1 / 2T. At this time, the modulation output
An exclusive OR output 24 of the square wave 11 and the square wave 11 is a signal in which the period of the square wave 11 is equal and the phase is changed by the gradation signal input 21, that is, a signal obtained by phase-modulating the square wave 11, and the phase shift square wave 14 of FIG.
Is the same signal as.

In this way, the liquid crystal 2 is supplied with voltage signals whose phases differ depending on the gradation.
It is possible to drive the gradation display of the liquid crystal 2 by applying the voltage between the two electrodes 1 and 3.

Problems to be Solved by the Invention However, according to the above-described conventional gradation display driving, there is a problem that the operating frequency of the pulse width modulator 22a becomes extremely high. In order to clarify the above problems, FIG.
9 shows a more detailed configuration of the pulse width modulator 22a.

As another example, as shown in FIG. 6, input gradation signal input
21 is a 6-bit binary digital signal data string,
It enters the memory 33a as a 6-bit parallel data string. Memory 3
3a stores 1 data (6 bits) in the input data string,
Stored data during the period of (1 / 2T) shown in Figs.
The pulse width is modulated to become the modulated output 22. The operation of each block in this case is as follows. That is, the square wave generator 11a
The square wave 11 of the pulse generated in 1 resets and starts the counter 32a at the rising and falling edges thereof, and at the same time drives the frequency multiplier 31a. The signal gradation is 6
In the case of bits (64 gradations), the frequency multiplier 31a multiplies the frequency of the input square wave 11 by 128 so that the counter 32a counts 64 in the 1 / 2T period, and outputs the result as the multiplier output 31. The memory 33a also reads data in synchronization with the counting operation of the counter 32a, supplies the data output 33 to the comparator 34a, and compares it with the counter output 32. If the value of the data output 33 is large, it takes a corresponding time for the counter output 32 to reach the value of the data output 33, and the value of the modulation output 22 moves at the moment of the data output 33 = the counter output 32. It becomes a pulse width modulated signal.

The above is the case where one data is stored in the memory 33a and the pulse width is modulated in the 1 / 2T period. In this case, the operating frequency of the counter 32a and the memory 33a is 128 of the square wave 11 as described above.
Doubled. Since the memory 33a actually stores a large amount of data, this frequency becomes higher. Assuming that the number of stored data is a television signal, 480 × 640 ≈ 300,
If 000 and T = 33.3msec (30Hz), the multiplier output 31
Frequency of 30 × 128 × 300,000 = 1,152 (MHz),
Realization of the circuit involves considerable difficulty and a complicated circuit configuration.

The present invention eliminates the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a liquid crystal driving method capable of greatly reducing the memory operating frequency.

Means for Solving the Problems In order to achieve the above object, the present invention has a digital memory composed of a plurality of bit planes for temporarily storing a digital drive signal for driving a liquid crystal, and reading a signal from the digital memory, When the liquid crystal is driven by the read signal, the signal is read from the digital memory for each bit plane, and the voltage controlled by the read signal according to the weighting of the read bit plane is “applied” or “not applied” to the liquid crystal. It is configured to drive the.

Operation Therefore, according to the present invention, it is not necessary to use a high operating frequency as in the prior art, and the circuit configuration can be simplified.

Example A liquid crystal driving method according to the present invention will be described below with reference to FIGS. 1 and 2. In order to simplify the explanation, the display gradation will be 6 bits (64 gradations) as an example in the following description.

In FIG. 1, 21 is a 6-bit gradation signal input, 42a is a memory for temporarily storing the signal, 43a is a voltage generator for generating a weighting voltage by the bit plane, 11 is a pulse-shaped square wave of period T ( Voltage), which is the same as in FIGS. 3 and 5. 41 is a multiplier that doubles the pulse frequency of the square wave 11 to obtain doubled outputs 41a, 41b, 41c, 44a is a switch that sequentially extracts the output signal 42 from the memory 42a for each bit plane, and 44 is a switch The output 45a is a switch for extracting and switching the weighted voltage by the bit plane in synchronization with the switch 44a, and 45 is a switch output 46a is a weighting voltage 43.
Is a switch output, 46a is a switch output, 47a and 48a are exclusive OR circuits, 47 and 48 are exclusive OR outputs, and 49a is an inverter. The same reference numerals as those in the other FIGS. 1 to 3 represent the same names.

In FIG. 1, the 6-bit gradation signal input 21 as an example is stored in the memory 42a at 42a-5 (MSB) to 42a-0 (LSB) for each bit plane by the write pulse 40a.
Further, the square wave 11 having the period T is supplied to the frequency multiplier 41 to obtain pulsed multiplication outputs 41a, 41b and 41c synchronized with the period T. The cycle of the double output 41a differs depending on the number of data handled in the period T. The double output 41b switches the switches 44a and 45a. When the number of data handled in the period T is one, each bit plane signal is selected at T / 6 intervals as shown in (c) of FIG. Then, the switch output 44 and the stepped voltage 45 for weighting the bit plane synchronized with the switch output 44 are obtained. The weighted voltage is the voltage generator 43
The weighting voltage V ₅ (MSB) to V ₀ (LSB) generated at a and corresponding to each bit plane is switched by the switch 45a to obtain the stepwise voltage 45 as shown in (d) of FIG.
Since the driving of the liquid crystal 2 is generally proportional to the effective value of the applied voltage,
_{V 5 = √2V 4, V 4} = √2V 3 it is convenient to determine the weighting voltage V ₅ ~V ₀ to relationship ...... V ₁ = √2V _0. The weighted voltages V _{5 to} V _{0 in the} stepwise voltage 45 are turned ON / OFF by the switch 46a by the corresponding bit plane signals, respectively.
When ON, the phase of liquid crystal electrode 1 differs from that of electrode 3 by 180 °,
In FF, a high frequency is applied in which the voltage of the period T / 6 of the same phase changes sequentially to the weighted voltages V _{5 to} V ₀ . 41c is an exclusive OR circuit 4
Period T / 6 for operating 7a and 48a (because of 6 bits)
This is a pulse-shaped double output. Exclusive OR circuit 47a, 48
The outputs (f), (g), and (h) of a correspond to the stepwise voltages 45 and 46 of (d) and (e) in which the voltage is applied to one input terminal, and the output of the other input terminal is doubled. The exclusive OR control is performed by 41c, and the exclusive OR output 47, 48 signals are output.
In all periods switch 46a is ON weighting voltage V ₅ ~V ₀ because the difference of the driving voltage applied between the electrodes 1 and 3 of the liquid crystal 2 exclusive output 48, 47, the liquid crystal 2 Voltage Is ± V ₅ ,
A pulse having a period T / 6 of ± V ₄ to ± V ₀ is applied for one cycle in the period T, and the applied voltage becomes zero when the pulse is OFF.

With such a driving method, there is no need for pulse width modulation as in the conventional example, so that the operating frequency of the memory 42a when the number of data stored in the memory is 1, is 1 × the square wave 11, that is, 480 ×
640≈300,000, which is about 9M at T = 33.3msec (30Hz)
It becomes Hz and becomes 1/128 of the conventional example. Further, even if the data numbers of the output signals are compared, the ratio of the data numbers is 128: 1 for the stepped voltage 46 of FIG. 2 of the modulation output 22 of FIG.

As described above, according to the present invention, when a digital drive signal of liquid crystal is obtained, it is temporarily recorded in a digital memory having a plurality of bit planes, and a predetermined weight is set for each bit plane at the time of reading. The operating frequency of the pulse width modulator can be significantly reduced because the obtained voltage is applied or not applied to the liquid crystal, and the signal transmission circuit, signal processing circuit, etc. can be significantly reduced. It has the advantage that it can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a drive circuit applied to a liquid crystal drive method according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the drive circuit, and FIG. 3 is a conventional liquid crystal drive. Waveform diagram for explaining the method, FIG. 4 is a block diagram showing a configuration of a conventional liquid crystal drive circuit, FIG. 5 is a waveform diagram for explaining the operation of the circuit, and FIG. 6 is a main part of the circuit. It is a block diagram. 1,3 ... Electrodes, 2 ... Liquid crystal, 11 ... Square wave, 21 ... Gradation signal input, 41a ... Frequency multiplier, 42a ... Memory, 43
a …… Voltage generator, 44a, 45a, 46a …… Switch.

Claims (1)

[Claims] 1. A digital drive signal for driving a liquid crystal is temporarily stored in a digital memory including a plurality of bit planes, the digital drive signal is read from the digital memory for each bit plane, and the read signal is read. A liquid crystal driving method for driving a liquid crystal by obtaining a driving voltage controlled according to the weighting of a bit plane and applying or not applying the driving voltage to the liquid crystal.