JPS6282885A - Method for driving liquid crystal - Google Patents

Abstract

PURPOSE:To display an image of high quality even if the number of electrodes is restricted by regularly differentiating the driving times of respective scanning electrodes in accordance with the scanning electrodes and setting up the total driving time of respective scanning electrodes equally every scanning of plural frames. CONSTITUTION:Although a scanning data shift clock phiS2 from a signal generating circuit 11 is formed in synchronizing with a horizontally synchronizing signal phiH, the 3rd output after the preceding 2 outputs is cut out. On the other hand, the cut clock timing is set up so as to be delayed by 1H between the 1st and 2nd fields. When a driving signal with 2H width e.g. is applied to a scanning electrode Xi, a driving signal with 1H width is applied to a scanning electrode Xi+1. When a driving signal with 2H width in the 1st frame is applied to the electrode Xi, a scanning signal with 1H width is applied in the 2nd frame. In this case, the total driving time of respective scanning electrodes X1-X160 is made equal every scanning of two frames. Since the driving time for all the scanning electrodes is set up equally in every two fields, picture quality can be prevented from reduction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a liquid crystal driving method used, for example, when driving a simple matrix liquid crystal display device.

[Prior art and its problems] In recent years, small portable television receivers have become popular.
Liquid crystal display panels with low power consumption are widely used. Since the number of electrodes in the above-mentioned liquid crystal display panel is limited if it is small, the number of scanning lines corresponding to the effective number of scanning lines in one field of a television signal (for example, 240 in the case of NTSC) is set. However, in reality, it is often constructed with two-thirds of the number of scanning lines (160). Here, as shown in FIG. 3, the scanning period for each scanning electrode X1 to Xn of the liquid crystal display panel is as follows:
Conventionally, T1 to Tn are all set equal, so the actual 1
The scanning period per scanning line is the scanning period IH (65.7 μs) of the television receiver equipped with the above 240 scanning lines.
) is 240/160-1.5H.

However, as mentioned above, the scanning period per scanning line is 1.
5H, there will be a case where the shift clock Φs2 of the scan 7u pole is located at the center of the video signal, as shown in FIG. In this case, the video signal corresponding to that position will not be shifted and latched by the signal electrode drive circuit, and as a result, many video signals will not appear on the screen. It is assumed that one field of the above-mentioned television signal corresponds to one frame of the liquid crystal display panel.

[Purpose of the Invention This invention was made in view of the above-mentioned problems.
For example, an object of the present invention is to provide a liquid crystal driving method that makes it possible to display images of sufficiently high quality even when the number of scanning electrodes is limited in a small liquid crystal display device.

``The main point of the invention, that is, the liquid crystal driving method according to the present invention is to regularly vary the driving time of each scanning electrode depending on the scanning electrode, and to make the total driving time of each scanning electrode equal for every multiple frame scan. This is what you set.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of a display drive part in a liquid crystal television receiver. In the figure, 11 is a signal generation circuit, and this circuit 11 has a horizontal synchronization signal ΦH processed and outputted by a synchronization processing circuit 12. and vertical synchronization signal ΦV
is input. This signal generation circuit 11 generates various signals based on the -F input signal ΦH2ΦV, and outputs, for example, a 4 MH2 basic clock ΦT to the scan electrode drive circuit 13 and the signal electrode drive circuit 14, and generates the scan data S.
outputs T and scanning data shift clock Φs2 to the shift register 15, outputs the video data shift clock Φs1 to the shift register 16, outputs the data latch clock Φ to the latch circuit 17, and further outputs the clock pulse ΦC
is output to the signal electrode drive circuit 14. Then, the scanning electrode drive circuit 13 and the signal electrode drive circuit 14 drive a simple matrix liquid crystal display panel 18 of, for example, 160×200 dots. Here, the video signal (Vi
deo) is supplied to the synchronization processing circuit 12, and
The signal is supplied to the shift register 16 as video data (Data) via the A/D converter 19. Note that one field in the television video signal corresponds to one frame on the liquid crystal display panel 18.

Next, the shift register 15 reads and sequentially shifts the scan data ST supplied from the signal generation circuit 11 in synchronization with the scan data shift clock Φs2. Then, the output signal of the shift register 15 is transferred to the scan electrode drive circuit 13 as scan data ST, and the data transferred from the scan electrode drive circuit 13 is shifted in synchronization with the scan data shift clock Φs2, and the data is transferred to the scan electrode X1. ~X1
60 drive signals are created.

Further, the shift register 16 reads and sequentially shifts the video data supplied via the A/D converter 19 in synchronization with the video data shift clock Φs1, and outputs the output signal to the latch circuit 17. This latch circuit 17 latches the output signal of the shift register 17 in synchronization with the data latch clock Φ, and uses the luminance modulation signal Y1 to Y2O0 generated by the signal electrode drive circuit 14 according to the latched video data. to drive.

Next, the operation of the above embodiment will be explained with reference to the timing chart shown in FIG.

Here, the scanning data clock Φs2 outputted by the signal generating circuit 11 is generated in synchronization with the horizontal synchronizing signal ΦH, and when two pulses are output, the next one is cut. That is, for every three horizontal synchronizing signals ΦH, all but one are used as the scanning data shift clock Φs2. In FIG. 3, one out of 13 video data latch clocks generated corresponding to the horizontal retrace period of the video signal is shown. In addition, this scanning data shift clock Φs2 has a clock timing of IH that is cut in the first field and the second field.
It is set so that it deviates by a certain amount.

In other words, scanning electrodes X1 to X16Q (Xi.

Xi+1. ), a drive signal with a time width of IH and 2H is applied to every other signal at the timing shown in FIG. 3 above. For example, when a 2H width drive signal is applied to the scan electrode Xi, an IH width drive signal is applied to the next scan electrode Xi+1. Furthermore, the scanning type tiX1 to
160 drive signals are used for the first field and the second field of the video signal.
field, that is, the first field on this liquid crystal display panel 18.
The time width is set to be opposite between the frame scanning time and the second frame scanning time. For example, if a 2H width drive signal is applied to the scanning electrode Xi in the first frame, an IH width scanning signal is applied in the second frame. In this case, each scan electrode X1 to X
The total drive time for 160 hours is the same.

As described above, the scanning electrodes X1 to X160 are driven every other time with a time width of 2H, and the corresponding signal electrode Y
1 to Y2O0 display 2H worth of video data. As a result, all video data is sampled and displayed in the effective scanning section. In this case, as mentioned above, the scanning electrodes on which 2H worth of display is performed are not limited, and the driving time for all scanning electrodes is made equal in units of 2 fields, so that the deterioration in image quality is prevented. I won't invite you.

In the above embodiment, since the number of scanning electrodes is 160, the scanning electrode drive signal is doubled in signal width for every other electrode, and 1
The settings were made so that all the video data of the field could be sampled in one frame, but for example, if the number of scanning electrodes was 18.
If there are 0 lines, it is sufficient to double the signal width of every second line. Also, for example, the number of scanning electrodes is 12.
If there are 0 lines, it is sufficient to triple the signal width for every other line. That is, the signal width multiple and generation timing of the scanning electrode drive signal are set according to the number of scanning electrodes of the liquid crystal display panel 18 used.

[Effects of the Invention] As described above, according to the present invention, the drive time of each scan electrode is made to vary regularly depending on the scan electrode, and the total drive time of each scan electrode is made equal for each scan of a plurality of frames. With this setting, it is possible to provide a liquid crystal driving method that can display images of sufficiently high quality even when the number of scanning electrodes is limited, for example in a small liquid crystal display device.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram (11S diagram) showing a liquid crystal display device whose display is controlled by the liquid crystal driving method according to an embodiment of the present invention, FIG. 2 is a timing chart showing the driving operation by the liquid crystal driving method described above, and FIG. 4 is a timing chart showing the driving waveform of the scanning electrode according to the conventional liquid crystal driving method, and FIG. 4 is a timing chart showing the operation of the liquid crystal display device according to the conventional liquid crystal driving method shown in FIG. 3. 11...Signal generation Circuit, 12...Synchronization processing circuit, 1
3... Scanning electrode drive circuit, 14... Signal electrode drive circuit, 15.16... Shift register, 17... Latch circuit, 18... Liquid crystal display panel, 19... A/D
Converter, ΦT: basic clock, Φs1: video data shift clock, Φs2: scanning data shift clock, Φ): video data latch clock. Applicant's agent Patent attorney Takehiko Suzue Figure 1 φT 6th chapter No. 9 Kofu Kapuku n-3n-2n-+
n n+1 n+2 2Figure 2

Claims (1)

[Claims] In a liquid crystal driving method for driving a liquid crystal display panel in which a large number of scanning electrodes and signal electrodes are arranged in a matrix, the driving time for driving the scanning electrodes is regularly varied depending on the scanning electrode, and the driving time for driving the scanning electrodes is regularly varied depending on the scanning electrode. A liquid crystal driving method characterized by equalizing the total driving time of electrodes.