JPH07181921A - Synchronous timing circuit - Google Patents

Abstract

PURPOSE:To display composite video signals of plural standards on one liquid crystal display panels in a center-aligned state by a relatively small scale circuit by providing a 1st delay means which gives a predetermined 1st delay time to a 2nd vertical synchronizing signal of a 2nd composite signal by, and a 2nd delay means which gives a predetermined 2nd delay time to a 2nd horizontal synchronizing signal. CONSTITUTION:This circuit is equipped with a delay circuit 61 which delays a vertical synchronizing signal V2 by a specific time to generate a vertical synchronizing signal V2D, a delay circuit 62 which delays a horizontal synchronizing signal H2 by a specific time to generate a horizontal synchronizing signal H2D, a switch circuit 63 which selects and outputs one of the vertical synchronizing signals V1 and V2D with a mode selects signal, and a switch circuit 64 which selects and outputs one of the horizontal synchronizing signal H1 and H2D with the mode select signal M. Therefore, the composite video signals of the 1st and 2nd standards can be displayed on the liquid crystal panel while having their center aligned with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous timing circuit, and more particularly to a synchronous timing circuit for a liquid crystal display device which displays a plurality of standard composite video signals.

[0002]

2. Description of the Related Art A dot matrix type display device using a liquid crystal or the like has features such as space saving and low power consumption since it has a low voltage drivability and a small planar structure, and is used as a display for a computer or the like. Is increasing rapidly.

This type of dot matrix type display device is
The number of dots in the horizontal direction is equal to the number of effective clocks in one horizontal scanning period of the video signal to be displayed, and the number of dots in the vertical direction is equal to the number of effective horizontal scanning lines in one vertical scanning period of the video signal. Therefore, in order to display the effective display data portion of the composite video signal including the horizontal and vertical synchronization signals on the entire display unit without omission, the pulse width of each of the horizontal and vertical synchronization signals and the pulse trailing edge of these synchronization signals are used. It is necessary to strictly define the back porch period up to the leading edge of the valid display data period.

A first example (hereinafter referred to as a first standard) of a standard of a composite video signal for a display of a personal computer, which is composed of pixels of 640 dots in the horizontal direction and 480 dots in the vertical direction, is shown in each time chart of vertical scanning and horizontal scanning. Figure 4,
Referring to FIG. 5, one scanning period of the vertical synchronizing signal V, that is, one vertical scanning period (hereinafter, 1V) LN1 is a horizontal synchronizing signal H.
525 scanning periods, that is, one horizontal scanning period is set to 1H, it is 525H, and the effective display data period LD1 in 1V corresponds to 480H. The pulse width VS1 of the vertical synchronizing signal V corresponds to 2H, and the vertical back porch period VB1 from the trailing edge of the vertical synchronizing signal V to the leading edge of the effective display data period LD1 of the data signal D corresponds to 32H.

Further referring to FIG. 5, one horizontal scanning period (1H) CL1 corresponds to 800 cycles of the clock signal CP, that is, 800 clocks, and a valid data period CD1 during 1H.
The pulse width HS1 of the horizontal synchronizing signal H at 640 clocks.
Corresponds to 96 clocks, and the horizontal back porch period HB1 from the trailing edge of the horizontal synchronizing signal H to the leading edge of the valid data period CD1 of the data signal D corresponds to 48 clocks.

Referring to FIG. 6 which is a block diagram showing an example of a liquid crystal display device capable of displaying a composite video signal of the above-mentioned first standard, this liquid crystal display device has a horizontal dot number M1 of six.
40, the number N1 of dots in the vertical direction is 480, that is, 480 lines 6
A liquid crystal panel 5 including a thin film transistor and a liquid crystal forming each pixel group arranged in a matrix of 80 columns.
And horizontal and vertical synchronizing signals H and V and clock signal CP
And a data signal D to generate a vertical start signal SV, a vertical clock signal CV, a horizontal start signal SH, a horizontal clock signal CH, and a latch pulse LP, respectively.
A synchronous timing circuit 1 for supplying, a vertical driver circuit 3 which has a shift register corresponding to a pixel row and which is supplied with a vertical start signal SV and a vertical clock signal CV to scan the liquid crystal panel 5 in the vertical direction, and a pixel column respectively. An upper and lower horizontal driver circuit 3, which has a corresponding shift register, receives the horizontal start signal SH, the horizontal clock signal CH, and the latch pulse LP and scans the liquid crystal panel 5 in the horizontal direction.
4 and.

Describing the operation, the synchronization timing circuit 1 includes horizontal and vertical synchronization signals H and V and a clock signal CP having the timings shown in FIGS. 4 and 5, respectively.
And the data signal D, the vertical driver circuit 2 receives the vertical start signal SV and the vertical clock signal CV, and the horizontal driver circuits 3 and 4 receive the horizontal start signal SH, the horizontal clock signal CH, and the latch pulse LP. Are generated and supplied respectively. In the vertical driver circuit 2, the internal shift register operates in response to the supply of the vertical start signal SV and the vertical clock signal CV to sequentially scan 480 pixel rows. The timing of the vertical start signal SV and the vertical clock signal CV is the pulse width S of the vertical synchronization signal V.
V1 and the back porch period VB1 correspond to the time relationship between the horizontal sync signal H and the effective display data period LD1 of the data signal D, respectively, so that the images are displayed on the liquid crystal panel 5 so as to coincide with each other without being vertically displaced. Is decided.

On the other hand, each of the horizontal driver circuits 3 and 4 has
The internal shift register operates in response to the supply of the horizontal start signal SH, the horizontal clock signal CH, and the latch pulse LP, and 1H corresponding to the sequential scanning of the vertical driver circuit 2.
The corresponding 640 pixel columns are sequentially scanned. The timing of these horizontal start signal SH, horizontal clock signal CH, and latch pulse LP is the pulse width SH1 of the horizontal synchronizing signal H.
And corresponding to the time relationship between the back porch period HB1 and the effective display data period CD1 of the clock signal CP and the data signal D, respectively, and it is determined so that the images are displayed on the liquid crystal panel 5 so as to be aligned with each other without shifting in the horizontal direction. To be done.

Next, as an example of the second standard for a display of a personal computer, 640 dots horizontally and 4 pixels vertically
There is a standard for composite video signals consisting of 00 dot pixels,
In this second standard, one vertical scanning period (1V) LN2 is 4
The effective display data period LD2 in 1V corresponds to 400H. Also, the pulse width VS2 of the vertical synchronizing signal V is 8H, and the back porch period VB2 is 2H.
Each corresponds to 6H. In addition, one horizontal scanning period (1
H) CL2 is 848 clocks, valid data period CDH in 1H is 640 clocks, pulse width HS2 of horizontal synchronizing signal H is 64 clocks, and back porch period H
B2 corresponds to 80 clocks, respectively.

When the composite video signal of the second standard is displayed as it is on the liquid crystal display device compatible with the first standard, the entire display screen is biased above the liquid crystal panel display surface, and
The upper part of the screen corresponding to the next vertical scanning after the vertical blanking period is displayed below, which is very unsightly.

As an example of the third standard, there is a standard for a composite video signal composed of pixels of 720 dots in the horizontal direction and 480 dots in the vertical direction. Regarding the horizontal scanning related to the third standard,
1 horizontal scanning period (1H) CL3 is 900 clocks and 1
The valid data period CD3 in H corresponds to 720 clocks, the pulse width HS3 of the horizontal synchronizing signal H corresponds to 20 clocks, and the back porch period HB3 corresponds to 30 clocks.

When the composite video signal of the first or second standard is displayed as it is on the liquid crystal display device compliant with the third standard, the entire display screen is biased to the left of the liquid crystal panel display surface. .

In order to display the above-mentioned composite video signals of the first and second or third standards centered on the same liquid crystal panel, the composite video signal of the second standard having the smaller number of vertical pixels is displayed. In the case of a signal, the vertical scanning period start time, that is, the timing of the vertical synchronizing signal is delayed, and at the same time, the difference between the horizontal and vertical effective periods and the difference between the horizontal and vertical back porch periods between the first and second standards of the display data are set. Need to be adjusted. Therefore, these first and second
The conventional liquid crystal display device capable of displaying the composite video signal of the standard has a function of delaying the timing of the vertical synchronizing signal and a function of adjusting the difference between the horizontal and vertical back porch periods and the difference between the effective display periods, A synchronous timing circuit having an enable circuit for validating the display data at correct timing is provided.

Referring to FIG. 7 which is a block diagram showing a conventional synchronous timing circuit having the enable circuit, the conventional synchronous timing circuit 100 includes an enable circuit 10 for generating a data enable signal ED in the synchronous timing circuit 1 of FIG. It is equipped with.

The enable circuit 10 delays the vertical synchronizing signal V in synchronization with the horizontal synchronizing signal H and delays the vertical synchronizing signal VD.
A vertical delay circuit 11 that outputs a clock, a back porch correction circuit 121 that adjusts a horizontal back porch period HB by receiving a clock CP and a horizontal synchronizing signal H, and a horizontal data setting circuit 122 that sets a horizontal effective data period CD. The horizontal enable circuit 12 for generating the included horizontal data enable signal EH, the back porch correction circuit 131 for adjusting the vertical back porch period VB by receiving the horizontal synchronizing signal H and the vertical synchronizing signal V, and the vertical effective data period LD are set. A vertical data setting circuit 132 for generating a vertical data enable signal EV, and an AND circuit 14 for generating a data enable signal ED which is a logical product of the horizontal and vertical enable signals EA and EV,
An enable gate circuit 15 for outputting the data D as the effective display data DE in response to the supply of the data enable signal ED or the mode selection signal M.

Next, referring to FIG. 8 which is an operation time chart, the operation of the conventional synchronous timing circuit will be described. First, when displaying a composite video signal of the first standard, mode selection is performed. By setting the signal M to the high level, the enable gate circuit 15 is always turned on, and the same operation as that of the synchronous timing circuit 1 of FIG. 6 described above is performed.

Next, when the composite video signal of the second standard is displayed, the mode selection signal M is set to the low level so that the enable gate circuit 15 enables the data D only during the high level period of the data enable signal ED. Output as display data DE.

First, the vertical delay circuit 11 is constituted by using a well-known binary counter, which is connected in cascade, which operates using the horizontal synchronizing signal H as a clock, a D flip-flop, and a monostable multivibrator. In response to the supply, a predetermined time, that is, (LD1-LD
2) / 2 = 40H This vertical synchronizing signal V is delayed to generate a delayed synchronizing signal VD. Back porch correction circuit 131
Corrects VB1-VB2 = 6H and sets the start time TV2 of the vertical data enable signal EV. The vertical data setting circuit 132 starts LD2 =
A vertical data enable signal EV having a width of 400H is generated. Next, the back porch correction circuit 121 sets HB1-
The correction is made by HB2 = 16 clocks, and the start time TH2 of the horizontal data enable signal EH is set. The horizontal data setting circuit 122 starts CD2 = 64 starting from the start time TH2.
A horizontal data enable signal EH having a width of 0 clock is generated. The AND circuit 14 performs a logical product operation of these vertical and horizontal data enable signals EV and EH to generate a data enable signal ED.

Here, both the fall of the vertical synchronizing signal V of the first and second standards to the start time TV are 34H.
Since the horizontal synchronizing signal H falls from the falling edge to the start time TH in 144 clocks, the composite video signals of the first and second standards are displayed in alignment with the center of the liquid crystal panel. be able to.

[0020]

The conventional sync timing circuit described above adjusts the timings of the vertical and horizontal sync signals in order to display the video aligned with the center of the liquid crystal panel corresponding to a plurality of standard composite video signals. The data enable signal that controls the valid display period of data is generated, and the data enable signal requires the data enable circuit that passes the input display data only for the required display period to generate the valid display data. There was a drawback that

[0021]

According to the synchronization timing circuit of the present invention, a liquid crystal display panel in which display cells are arranged in a matrix having a predetermined first row number and first column number is provided.
A first scan line which is the same as the number of the first columns and which is the scan line corresponding to the display; and a first number which is the number of the display columns which are the display corresponding pixels per scan line. The first image corresponding to the composite video signal and at least one of the number of rows and the number of columns is less than the number of effective scanning lines of the first number of rows and the number of effective scanning lines of the second number of rows and / or the first number of columns. In a synchronization timing circuit of a liquid crystal display panel drive device for respectively displaying a second image corresponding to a second composite video signal, which comprises a smaller number of effective display pixels in a second column, the first timing of the first composite video signal First delay means for generating a second delayed vertical synchronizing signal by giving a predetermined first delay time to the second vertical synchronizing signal of the second composite video signal with reference to the timing of the first vertical synchronizing signal. And the first The second of the timing of the first horizontal synchronizing signal of the multiplexer video signal as a reference the second composite video signal
Second horizontal delay signal to the horizontal synchronization signal of
Second delay means for generating the delayed horizontal synchronization signal, and first switching means for switching to output either one of the first vertical synchronization signal and the second delayed vertical synchronization signal, It comprises a second switch means for switching to output either one of the first horizontal synchronizing signal and the second delayed horizontal synchronizing signal.

[0022]

1 is a block diagram showing an embodiment of the present invention.
6, the synchronization timing circuit 1A of the present embodiment shown in this figure generates a vertical synchronization signal V2D by delaying and delaying the vertical synchronization signal V2 by a predetermined time in addition to the various components of the synchronization timing circuit 1 of FIG. A delay circuit 61 for delaying the horizontal synchronization signal H2 by a predetermined time to generate a delayed horizontal synchronization signal H2D, and a mode selection signal M to select and output one of the vertical synchronization signals V1 and V2D. And a switch circuit 64 that selects and outputs one of the horizontal synchronizing signals H1 and H2D by the mode selection signal M.

Referring to FIG. 2 showing the configuration of the delay circuit 61, the delay circuit 61 includes a 9-bit counter circuit 611 that counts the horizontal synchronizing signal H as a clock, an inverter 612 that inverts the vertical synchronizing signal V1. D-type flip-flop 6 that latches the output of the inverter 612
13 and a monostable multivibrator 614 which is triggered by the output of the counter circuit 611 and outputs a vertical synchronization signal V2D having a predetermined width.

The delay circuit 62 has the same configuration as the delay circuit 61 except that the clock signal CP is supplied instead of the horizontal synchronizing signal H, and the horizontal synchronizing signal H is supplied instead of the vertical synchronizing signal V. Omit it.

For convenience of explanation, the liquid crystal display device provided with the synchronization timing circuit of this embodiment has the above-described first and second liquid crystal display devices.
It shall be possible to display the composite video signal of the standard.

Next, the operation of the present embodiment will be described with reference to FIGS. 1 and 2 and FIG. 3 showing a time chart of vertical scanning. First, in the case of displaying a composite video signal of the first standard, By setting the mode selection signal M to a high level, the switch circuits 63 and 64 respectively select and directly output the vertical synchronization signal V1 and the horizontal synchronization signal H1 of the first standard, and the synchronization timing circuit 1 of FIG. Performs the same operation as.

Next, when the composite video signal of the second standard is displayed, the mode selection signal M is set to a low level, so that the switch circuits 63 and 64 respectively delay the vertical synchronization signal corresponding to the second standard. V2D, horizontal sync signal H2
Select D to perform the display operation corresponding to the second standard.

The vertical and horizontal synchronizing signals V2 and H2 of the second standard, which are input to the liquid crystal display device conforming to the first standard, are delayed for a predetermined time respectively and the composite video signal of the second standard is centered on the liquid crystal display panel. The delay times DL and DC required to generate the vertical and horizontal synchronizing signals V2D and H2D for displaying the same are respectively expressed by equations (1) and (2).
It is shown by the formula.

DL = LN2- (LD1-LD2) / 2-{(VS1 + VB1)-(VS2 + VB2)} ………………………………………………………… (1) DC = CL2- (CD1-CD2) / 2-{(HS1 + HB1)-(HS2 + HB2)} …………………………………………………… (2) Description of the conventional technology By substituting the numerical values of these parameters corresponding to the first and second standards, the delay times DL and DC for the vertical and horizontal synchronizing signals V2 and H2 are 400H and 0 clocks, respectively. Therefore, the horizontal synchronizing signal H2 is used as H2D without delay.

The operation of the delay circuit 61 will be described below.
First, the inverter 612 receives the supplied vertical synchronizing signal V
Is inverted and supplied to the input CL of the flip-flop 613. The flip-flop 613 latches the signal level 1 supplied to D at the rising edge of the signal supplied to CLK and outputs it from Q. The RST resets the output Q to level 0 in response to the supply of signal level 1. Flip-flop 61
3 supplies the output of Q to the input E of the counter circuit 611. The counter circuit 611 responds to the supply of the level 1 to the terminal E and performs the counting operation of the rising of the horizontal synchronizing signal H supplied to the input CLK, and a predetermined count value, that is, 4 in this embodiment.
When it reaches 00, Q outputs level 1. The counter circuit 611 is reset in response to the supply of the level 1 to the reset terminal RST, and the output Q also becomes the level 0. The multivibrator 614 operates in response to the supply of the level 1 of the output Q of the counter circuit 611, and the capacitor C61,
A delayed vertical synchronizing signal VD having a pulse width corresponding to the time constant determined by the resistor R61 is output from the terminal Q. At the same time, this output Q
The counter circuit 611 itself and the flip-flop 613 are reset in response to the supply of the level 1 of.

Referring to FIG. 3, the liquid crystal display device having the synchronization timing circuit according to the present embodiment has a delayed vertical synchronization signal V.
The display is started after the total time of the vertical synchronizing signal pulse width VS2 and the back porch period VB2, that is, 34H has elapsed from the falling time of D2. Therefore, the blanking periods B1 and 400H for 40H before the data signal D of FIG.
Minute effective data display period DD and the subsequent 40H blanking period B2 are display target periods, but the data signals corresponding to the blanking periods B1 and B2 are at level 0, and black display is performed. Effective data display period DD
Only the corresponding data is displayed in the center of the display panel.

The required delay time DC1 with respect to the horizontal synchronizing signal H1 when displaying the first composite video signal on the liquid crystal display device conforming to the third standard is 754 clocks.
The delay circuit 62 generates this delay time DC1, and
Except that the display direction is adjusted in the left-right direction, it is the same as the case of displaying the composite signal of the second standard on the display device compatible with the first standard, and thus the description thereof is omitted.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made. For example, it is needless to say that a shift register or a RAM may be used as the delay circuit instead of the counter without departing from the spirit of the present invention.

[0034]

As described above, the synchronization timing circuit of the present invention comprises the first delay means for giving a predetermined first delay time to the second vertical synchronization signal of the second composite video signal, Since the second horizontal synchronizing signal is provided with a second delaying means for giving a predetermined second delay time, a composite video signal of a plurality of standards is centered on one liquid crystal display panel by a relatively small circuit. The effect is that they can be displayed side by side.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronization timing circuit of the present invention.

FIG. 2 is a block diagram showing an example of a configuration of a delay circuit according to the present exemplary embodiment.

FIG. 3 is a flowchart showing an example of an operation in the synchronization timing circuit of this embodiment.

FIG. 4 is a time chart of vertical scanning of a composite video signal.

FIG. 5 is a time chart of horizontal scanning of a composite video signal.

FIG. 6 is a block diagram showing an example of a general liquid crystal display device.

FIG. 7 is a block diagram showing an example of a conventional synchronization timing circuit.

FIG. 8 is an operation time chart of a conventional synchronization timing circuit.

[Explanation of symbols]

 1, 1A, 100 Synchronous timing circuit 2 Vertical driver circuit 3, 4 Horizontal driver circuit 5 Liquid crystal panel 10 Enable circuit 11 Vertical delay circuit 12 Horizontal enable circuit 13 Vertical enable circuit 14 AND circuit 15 Enable gate circuit 61, 62 Delay circuit 63, 64 switch circuit 121,131 back porch correction circuit 122 horizontal data setting circuit 133 vertical data setting circuit 611 counter 612 inverter 613 flip-flop 614 multivibrator

Claims (3)

[Claims] 1. A liquid crystal display panel in which display cells are arranged in a matrix having a first number of rows and a first number of columns determined in advance has scan lines corresponding to the same number as the first columns. A first image corresponding to a first composite video signal, which includes a certain effective scanning line and an effective display pixel which is the same number of pixels corresponding to the display per one scanning line as the first column, and at least the number of rows Either one of the number of rows is the first
A second image corresponding to the second composite video signal, which comprises a second number of effective scan lines less than the number of effective scanning lines and / or a second number of effective display pixels less than the first number of columns; In a synchronization timing circuit of a liquid crystal display panel driving device for displaying each of the above, the second vertical synchronization signal of the second composite video signal is previously set to the second vertical synchronization signal of the second composite video signal with reference to the timing of the first vertical synchronization signal of the first composite video signal. First delay means for generating a second delayed vertical synchronizing signal by giving a determined first delay time; and the second composite based on the timing of the first horizontal synchronizing signal of the first composite video signal. Second delay means for applying a predetermined second delay time to the second horizontal synchronizing signal of the video signal to generate a second delayed horizontal synchronizing signal; the first vertical synchronizing signal and the second delay Any with vertical sync signal A first switch means for switching to output one of the two; and a second switch means for switching to output one of the first horizontal synchronizing signal and the second delayed horizontal synchronizing signal. A synchronous timing circuit characterized by. 2. The effective period represented by the number of horizontal scanning lines in one vertical scanning period of the first composite video signal, the vertical synchronizing signal pulse width, and the vertical back porch period are each LD.
1, VS1, and VB1, and the valid period, the horizontal synchronizing signal pulse width, and the horizontal back porch period, which are represented by the number of pixel clocks in one horizontal scanning period of the first composite video signal, are CD1, HS1, and HB1, respectively. The vertical scanning period, the effective period, the vertical synchronizing signal pulse width, and the vertical back porch period, which are represented by the number of horizontal scanning lines in one vertical scanning period of the second composite video signal, are LN2 and LN2, respectively.
Let LD2, VS2, and VB2 be 1 represented by the number of pixel clocks in one horizontal scanning period of the second composite video signal.
The horizontal scanning period, effective period, horizontal synchronizing signal pulse width, and horizontal back porch period are CL2, CD2, H, respectively.
When S2 and HB2, the first and second delay times DL and DC are (1) and (2), respectively.
The synchronous timing circuit of claim 1 having a value of an expression. DL = LN2- (LD1-LD2) / 2-{(VS1 + VB1)-(VS2 + VB2)} ………………………………………………………… (1) DC = CL2- (CD1-CD2) / 2-{(HS1 + HB1)-(HS2 + HB2)} ………………………………………………………… (2) 3. A first counter circuit, wherein the first delay means counts the second horizontal synchronizing signal as a clock from the leading edge of the second vertical signal, and an output of the first counter circuit. A first monostable multivibrator which is triggered and outputs the second delayed vertical synchronizing signal of a predetermined width, wherein the second delay means uses the pixel clock signal as a clock from the leading edge of the second horizontal signal. Second counting
2. The counter circuit according to claim 1, and a second monostable multivibrator which is triggered by the output of the second counter circuit and outputs the second delayed horizontal synchronizing signal of a predetermined width. Synchronous timing circuit.