JP2699846B2 - Synchronous timing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous timing circuit, and more particularly to a synchronous timing circuit for a liquid crystal display device which displays a composite video signal of a plurality of standards.

[0002]

2. Description of the Related Art A dot matrix type display device using a liquid crystal or the like has features such as space saving and low power consumption due to its low voltage drivability and a small flat structure, and is used as a display for a computer or the like. Is growing rapidly.

[0003] This type of dot matrix display device is
The number of dots in the horizontal direction is equal to the number of effective clocks in one horizontal scanning period of the video signal to be displayed, and the number of dots in the vertical direction is equal to the number of effective horizontal scanning lines in one vertical scanning period of the video signal. Therefore, in order to display the effective display data portion of the composite video signal including the horizontal and vertical synchronizing signals on the entire display unit without omission, the pulse width of each of the horizontal and vertical synchronizing signals and the pulse trailing edge of these synchronizing signals are used. It is necessary to strictly define the back porch period up to the leading edge of the effective display data period. It should be noted that the normal liquid crystal display device vertical
The drive circuit moves to the start position of the video signal by the vertical synchronization signal.
"Line-sequential scanning" that sends sequential pulses to the line
Display, and the horizontal drive circuit is sent sequentially serially
Rearrange one horizontal period of the incoming video signal into a parallel signal
it's shown.

A first example (hereinafter referred to as a first standard) of a standard of a composite video signal for a display of a personal computer comprising pixels of 640 horizontal dots and 480 vertical dots is shown in a time chart of each of vertical scanning and horizontal scanning. FIG.
Referring to FIG. 5, one scanning period of the vertical synchronizing signal V, that is, one vertical scanning period (hereinafter, 1V) LN1 is the horizontal synchronizing signal H.
If the 525 scanning period, ie, one horizontal scanning period, is 1H, the effective display data period LD1 in 1V corresponds to 480H. The pulse width VS1 of the vertical synchronization signal V corresponds to 2H, and the vertical back porch period VB1 from the trailing edge of the vertical synchronization signal V to the leading edge of the effective display data period LD1 of the data signal D corresponds to 32H.

Referring to FIG. 5, one horizontal scanning period (1H) CL1 is equivalent to 800 cycles of the clock signal CP, that is, 800 clocks, and a valid data period CD1 during 1H.
Is 640 clocks, and the pulse width HS1 of the horizontal synchronization signal H is
Corresponds to 96 clocks, and the horizontal back porch period HB1 from the trailing edge of the horizontal synchronization signal H to the leading edge of the valid data period CD1 of the data signal D corresponds to 48 clocks.

Referring to FIG. 6, which is a block diagram showing an example of a liquid crystal display device capable of displaying a composite video signal of the above-mentioned first standard, this liquid crystal display device has a horizontal dot number M1 of six.
40, the number of dots N1 in the vertical direction is 480, that is, 480 rows 6
A liquid crystal panel 5 composed of thin film transistors and liquid crystal constituting each pixel group arranged in a matrix of 80 columns
Horizontal and vertical synchronizing signals H and V and a clock signal CP
And a data signal D to generate a vertical start signal SV, a vertical clock signal CV, a horizontal start signal SH, a horizontal clock signal CH, and a latch pulse LP, respectively.
A synchronization timing circuit 1 for supplying a pixel signal, a vertical driver circuit 3 having a shift register corresponding to a pixel row, receiving the supply of the vertical start signal SV and the vertical clock signal CV, and scanning the liquid crystal panel 5 in the vertical direction. Upper and lower horizontal driver circuits 3 having corresponding shift registers and receiving the supply of the horizontal start signal SH, the horizontal clock signal CH, and the latch pulse LP to scan the liquid crystal panel 5 in the horizontal direction.
4 is provided.

The operation of the synchronous timing circuit 1 will now be described. The synchronous timing circuit 1 comprises horizontal and vertical synchronous signals H and V and a clock signal CP having the timings shown in FIGS.
And a data signal D, and supplies a vertical start signal SV and a vertical clock signal CV to the vertical driver circuit 2 and a horizontal start signal SH, a horizontal clock signal CH and a latch pulse LP to each of the horizontal driver circuits 3 and 4. Is generated and supplied. In the vertical driver circuit 2, the internal shift register operates in response to the supply of the vertical start signal SV and the vertical clock signal CV, and sequentially scans 480 pixel rows. The timing of the vertical start signal SV and the vertical clock signal CV corresponds to the pulse width S of the vertical synchronization signal V.
V1 and the back porch period VB1 correspond to the time relationship between the horizontal synchronizing signal H and the effective display data period LD1 of the data signal D, respectively, so that the images are displayed on the liquid crystal panel 5 so as to match without being shifted in the vertical direction. Is determined.

On the other hand, each of the horizontal driver circuits 3 and 4
The internal shift register operates in response to the supply of the horizontal start signal SH, the horizontal clock signal CH, and the latch pulse LP, and 1H corresponds to the sequential scanning of the vertical driver circuit 2.
The corresponding 640 pixel columns are sequentially scanned. The timing of the horizontal start signal SH, the horizontal clock signal CH, and the latch pulse LP is determined by the pulse width SH1 of the horizontal synchronization signal H.
Corresponding to the time relationship between the back porch period HB1 and the effective display data period CD1 of the clock signal CP and the data signal D, respectively, and are determined so that the images are displayed on the liquid crystal panel 5 so as to match without shifting in the left-right direction. Is done.

Next, as an example of a second standard for a display of a personal computer, 640 dots in width and 4 dots in height
There is a standard for composite video signals consisting of 00 dot pixels,
The second standard is that one vertical scanning period (1 V) LN2 is 4
The effective display data period LD2 in 1V corresponds to 400H. The pulse width VS2 of the vertical synchronization signal V is 8H, and the back porch period VB2 is 2H.
6H respectively. Also, one horizontal scanning period (1
H) CL2 is 848 clocks, effective data period CD2 in 1H is 640 clocks, pulse width HS2 of horizontal synchronizing signal H is 64 clocks, and back porch period H
B2 corresponds to 80 clocks, respectively.

When the composite video signal of the second standard is displayed as it is on a liquid crystal display device compliant with the first standard, the entire display screen is biased above the liquid crystal panel display surface,
The upper part of the screen corresponding to the next vertical scanning after the vertical blanking period is displayed below, which is extremely unsightly.

Further, as an example of the third standard, there is a standard of a composite video signal composed of 720 horizontal pixels and 480 vertical pixels.
One horizontal scanning period (1H) CL3 corresponds to 900 clocks.
The effective data period CD3 in H corresponds to 720 clocks, the pulse width HS3 of the horizontal synchronization signal H corresponds to 20 clocks, and the back porch period HB3 corresponds to 30 clocks.

When a composite video signal of the first or second standard is displayed as it is on a liquid crystal display device compliant with the third standard, the entire display screen is displaced to the left of the liquid crystal panel display surface. .

In order to display the above-mentioned composite video signals of the first and second or third standards on the same liquid crystal panel in a centered manner, the composite video of the second standard having a smaller number of vertical pixels is required. In the case of a signal, the start time of the vertical scanning period, that is, the timing of the vertical synchronizing signal is delayed, and at the same time, the difference between the horizontal and vertical effective periods and the difference between the horizontal and vertical back porch periods between the first and second standards of display data. Need to adjust. For this reason, these first and second
The conventional liquid crystal display device capable of displaying the composite video signal of the standard has a function of delaying the timing of the vertical synchronization signal and a function of adjusting the difference between the horizontal and vertical back porch periods and the difference between the effective display periods, A synchronous timing circuit having an enable circuit for validating the display data at a correct timing is provided.

Referring to FIG. 7 which shows a block diagram of a conventional synchronous timing circuit having this enable circuit, the conventional synchronous timing circuit 100 is different from the synchronous circuit 1 shown in FIG. It is provided with.

The enable circuit 10 delays the vertical synchronizing signal V in synchronization with the horizontal synchronizing signal H to delay the vertical synchronizing signal VD.
, A back porch correction circuit 121 that receives the clock CP and the horizontal synchronization signal H to adjust the horizontal back porch period HB, and a horizontal data setting circuit 122 that sets a horizontal effective data period CD. A horizontal enable circuit 12 for generating an included horizontal data enable signal EH, a back porch correction circuit 131 for receiving a horizontal synchronization signal H and a vertical synchronization signal V and adjusting a vertical back porch period VB, and a vertical valid data period LD are set. A vertical data setting circuit 132 for generating a vertical data enable signal EV, and an AND circuit 14 for generating a data enable signal ED which is a logical product of the horizontal and vertical enable signals EA and EV.
An enable gate circuit 15 that outputs data D as valid display data DE in response to supply of a data enable signal ED or a mode selection signal M.

Next, the operation of the conventional synchronous timing circuit will be described with reference to FIG. 8 which is an operation time chart. First, when a composite video signal of the first standard is displayed, a mode selection is performed. When the signal M is set to the high level, the enable gate circuit 15 is always turned on, and the same operation as the above-described synchronous timing circuit 1 of FIG. 6 is performed.

Next, when the composite video signal of the second standard is displayed, the mode selection signal M is set to low level, so that the enable gate circuit 15 enables the data D only during the high level period of the data enable signal ED. Output as display data DE.

First, the vertical delay circuit 11 is configured using a cascade-connected well-known binary counter, a D flip-flop, and a monostable multivibrator that operate using the horizontal synchronization signal H as a clock. A predetermined time in response to the supply, i.e. (LD1-LD
2) The vertical synchronization signal V is delayed by / 2 = 40H to generate a delayed synchronization signal VD. Back porch correction circuit 131
Corrects VB1−VB2 = 6H and sets the start time TV2 of the vertical data enable signal EV. The vertical data setting circuit 132 determines that LD2 =
A vertical data enable signal EV having a width of 400H is generated. Next, the back porch correction circuit 121 performs HB1-
The start time TH2 of the horizontal data enable signal EH is set by correcting HB2 = 16 clocks. The horizontal data setting circuit 122 determines that CD2 = 64 starting from the start time TH2
A horizontal data enable signal EH having a width of 0 clock is generated. The AND circuit 14 performs a logical product operation of the vertical and horizontal data enable signals EV and EH to generate a data enable signal ED.

Here, from the fall of the vertical synchronizing signal V of the first and second standards to the start time TV, both are 34H.
Since the horizontal synchronization signal H falls from the falling edge of the horizontal synchronization signal H to the start time TH is 144 clocks, the composite video signals of the first and second standards are displayed in accordance with the center of the liquid crystal panel. be able to.

[0020]

The above-mentioned conventional synchronous timing circuit adjusts the timing of the vertical and horizontal synchronous signals in order to display a composite video signal of a plurality of standards in accordance with the center of the liquid crystal panel. A data enable signal for controlling the effective display period of the data to generate valid display data by passing the input display data only for a required display period by the data enable signal. There was a disadvantage of becoming.

[0021]

Configuration of the synchronization timing circuit of the present invention According to an aspect of the liquid crystal composed of the first number of rows and the first columns
The number of scanning lines of the standard corresponding to this display screen on the display screen
And a first composite video signal having an effective display pixel number is displayed.
In the liquid crystal display panel , at least one of the number of rows and the number of columns is smaller than the first number of effective scan lines and the second number of effective scan lines is smaller than the first number of effective scan lines. in synchronization timing circuit of a liquid crystal display panel driving device for displaying the second composite video signal and driven by line-sequential scanning of having an effective display pixels of the second number of columns, pre-Symbol said display screen a second composite video signal To be displayed in the center of
In a first delay means for generating a first delayed vertical synchronizing signals providing a first delay time to the vertical synchronizing signal of said second composite video signal, horizontal synchronization before Symbol second composite video signal characterized in that it comprises a second delay means for generating a second delayed horizontal synchronizing signal given second delay time signal.

[0022]

FIG. 1 is a block diagram showing an embodiment of the present invention.
6, the synchronization timing circuit 1A of this embodiment shown in FIG. 6 generates a vertical synchronization signal V2D obtained by delaying the vertical synchronization signal V2 by a predetermined time in addition to the various components of the synchronization timing circuit 1 of FIG. Delay circuit 61, a horizontal synchronization signal H2 is delayed by a predetermined time to generate a horizontal synchronization signal H2D, and a mode selection signal M selects and outputs one of the vertical synchronization signals V1 and V2D. And a switch circuit 64 for selecting and outputting one of the horizontal synchronization signals H1 and H2D according to the mode selection signal M.

Referring to FIG. 2 showing the configuration of the delay circuit 61, the delay circuit 61 includes a 9-bit counter circuit 611 for counting the horizontal synchronization signal H as a clock, an inverter 612 for inverting the vertical synchronization signal V1, and D-type flip-flop 6 for latching the output of inverter 612
13 and a monostable multivibrator 614 that is triggered by the output of the counter circuit 611 and outputs a vertical synchronization signal V2D of a predetermined width.

The delay circuit 62 has the same configuration as that of the delay circuit 61 except that the clock signal CP is supplied instead of the horizontal synchronization signal H and the horizontal synchronization signal H is supplied instead of the vertical synchronization signal V. Omitted.

For convenience of explanation, the liquid crystal display device provided with the synchronization timing circuit of the present embodiment employs the above-described first and second liquid crystal display devices.
It is possible to display a composite video signal conforming to the standard.

Next, the operation of this embodiment will be described with reference to FIGS. 1 and 2 and FIG. 3 showing a time chart of vertical scanning. First, in the case of displaying a composite video signal of the first standard, When the mode selection signal M is set to the high level, the switch circuits 63 and 64 select the vertical synchronization signal V1 and the horizontal synchronization signal H1 of the first standard, respectively, and directly output the signals. The same operation as is performed.

Next, when a composite video signal of the second standard is displayed, the mode selection signal M is set to a low level so that the switch circuits 63 and 64 respectively delay the vertical synchronization signal corresponding to the second standard. V2D, horizontal synchronization signal H2
D is selected to perform a display operation conforming to the second standard.

The vertical and horizontal synchronizing signals V2 and H2 of the second standard input to the liquid crystal display device conforming to the first standard are each delayed for a predetermined time, and the composite video signal of the second standard is centered on the liquid crystal display panel. The required delay times DL and DC for generating the vertical and horizontal synchronizing signals V2D and H2D for aligning and displaying are represented by the equations (1) and (2), respectively.
It is shown by the formula.

DL = LN2− (LD1−LD2) / 2 − {(VS1 + VB1) − (VS2 + VB2)}... ……………………………… (1) DC = CL2− (CD1−CD2) / 2 − {(HS1 + HB1) − (HS2 + HB2)}........... When the values of these parameters corresponding to the first and second standards are substituted, the delay times DL and DC for the vertical and horizontal synchronization signals V2 and H2 are 400H and 0 clocks, respectively. Therefore, the horizontal synchronization signal H2 is used as H2D without delay.

The operation of the delay circuit 61 will be described.
First, the inverter 612 receives the supplied vertical synchronizing signal V
Is supplied to the input CL of the flip-flop 613. The flip-flop 613 latches the signal level 1 supplied to D at the rising edge of the signal supplied to CLK and outputs it from Q. RST resets output Q to level 0 in response to supplying signal level 1. Flip-flop 61
3 supplies the output of Q to the input E of the counter circuit 611. The counter circuit 611 counts the rising of the horizontal synchronizing signal H supplied to the input CLK in response to the supply of the level 1 to the terminal E, and counts a predetermined count value, that is, 4 in the present embodiment.
When the number reaches 00, level 1 is output from Q. The counter circuit 611 is reset in response to the supply of the level 1 to the reset terminal RST, and the output Q also becomes the level 0. The multivibrator 614 operates in response to the supply of the level Q of the output Q of the counter circuit 611, and the capacitor C61,
A delayed vertical synchronization signal VD having a pulse width corresponding to the time constant determined by the resistor R61 is output from the terminal Q. At the same time, this output Q
, The counter circuit 611 itself and the flip-flop 613 are reset.

Referring to FIG. 3, the liquid crystal display device provided with the synchronization timing circuit according to the present embodiment employs a delayed vertical synchronization signal V.
The display is started after a lapse of the total time of the vertical synchronization signal pulse width VS2 and the back porch period VB2, that is, 34H, from the falling time of D2. Therefore, blanking periods B1 and 400H for 40H before the data signal D in FIG.
The effective data display period DD and the subsequent blanking period B2 for 40H are display target periods. However, since the data signals corresponding to the blanking periods B1 and B2 are at level 0 and black display is performed, Valid data display period DD
Only the corresponding data is displayed at the center of the display panel.

The required delay time DC1 for the horizontal synchronizing signal H1 for displaying the first composite video signal on the liquid crystal display device conforming to the third standard is 754 clocks.
That the delay circuit 62 generates the delay time DC1;
Except that the adjustment of the display direction is performed in the left-right direction, it is the same as the case where the composite signal of the second standard is displayed on the display device compliant with the first standard, and therefore the description is omitted.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, a shift register or a RAM may be used instead of the counter as the delay circuit, as a matter of course, without departing from the spirit of the present invention.

[0034]

As described above, the synchronization timing circuit of the present invention comprises: a first delay means for providing a predetermined first delay time to a second vertical synchronization signal of a second composite video signal; A second delay means for providing a predetermined second delay time to the second horizontal synchronizing signal, so that a plurality of standard composite video signals can be centered on one liquid crystal display panel by a relatively small-scale circuit. There is an effect that they can be aligned and displayed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a synchronization timing circuit of the present invention.

FIG. 2 is a block diagram illustrating an example of a configuration of a delay circuit according to the embodiment.

FIG. 3 is a flowchart illustrating an example of an operation in the synchronization timing circuit according to the embodiment.

FIG. 4 is a time chart of vertical scanning of a composite video signal.

FIG. 5 is a time chart of horizontal scanning of a composite video signal.

FIG. 6 is a block diagram illustrating an example of a general liquid crystal display device.

FIG. 7 is a block diagram showing an example of a conventional synchronous timing circuit.

FIG. 8 is an operation time chart of a conventional synchronous timing circuit.

[Explanation of symbols]

 1, 1A, 100 Synchronous timing circuit 2 Vertical driver circuit 3, 4 Horizontal driver circuit 5 Liquid crystal panel 10 Enable circuit 11 Vertical delay circuit 12 Horizontal enable circuit 13 Vertical enable circuit 14 AND circuit 15 Enable gate circuit 61, 62 Delay circuit 63, 64 switch circuit 121, 131 back porch correction circuit 122 horizontal data setting circuit 133 vertical data setting circuit 611 counter 612 inverter 613 flip-flop 614 multivibrator

Claims (3)

(57) [Claims] 1. A first number of rows and a liquid crystal comprising a first number of columns
The number of scanning lines of the standard corresponding to this display screen on the display screen
And a first composite video signal having an effective display pixel number is displayed.
Liquid crystal display panel, less than least number of rows and any one of the effective scanning lines and or first row number of the first second number of lines smaller than the number of effective scanning lines row and column number of liquid crystal in synchronization timing circuit of a display panel drive device, before Symbol second composite video signal said display screen for displaying the second composite video signal having an effective display pixels of the second number of columns driven by line-sequential scanning To be displayed in the upper center
In a first delay means for generating a first delayed vertical synchronizing signals providing a first delay time to the vertical synchronizing signal of said second composite video signal, horizontal synchronization before Symbol second composite video signal synchronization timing circuit; and a second delay means for generating a second delayed horizontal synchronizing signal given second delay time signal. 2. The method according to claim 1, wherein an effective period, a vertical synchronizing signal pulse width, and a vertical back porch period represented by the number of horizontal scanning lines within one vertical scanning period of the first composite video signal are respectively represented by LD.
1, VS1, and VB1, and the effective period, the horizontal synchronizing signal pulse width, and the horizontal back porch period represented by the number of pixel clocks within one horizontal scanning period of the first composite video signal are CD1, HS1, and HB1, respectively. And a vertical scanning period, an effective period, a vertical synchronizing signal pulse width, and a vertical back porch period represented by the number of horizontal scanning lines within one vertical scanning period of the second composite video signal are LN2 and LN2, respectively.
LD2, VS2, and VB2, and 1 represented by the number of pixel clocks in one horizontal scanning period of the second composite video signal
The horizontal scanning period, effective period, horizontal synchronizing signal pulse width, and horizontal back porch period are designated CL2, CD2, and H, respectively.
S2 and HB2, the first and second delay times DL and DC are (1) and (2), respectively.
Synchronization timing circuit 請 Motomeko 1 wherein that having a value of the expression. DL = LN2- (LD1-LD2) / 2-{(VS1 + VB1)-(VS2 + VB2)}............ CD1−CD2) / 2 − {(HS1 + HB1) − (HS2 + HB2)}........... Wherein said first delay means includes a first counter circuit for counting the second horizontal synchronizing signal as a clock from the leading edge of the second vertical signal, the output of the first counter circuit A first monostable multivibrator for outputting the second delayed vertical synchronizing signal having a predetermined width triggered by the second clock signal, wherein the second delay means clocks a pixel clock signal from a leading edge of the second horizontal signal. 請 a second counter circuit for counting, for Ru and a second monostable multivibrator for outputting the second delayed horizontal synchronizing signal triggered predetermined width by the output of said second counter circuit as <br / The synchronous timing circuit according to claim 1.