JPH0718988B2 - Liquid crystal display circuit - Google Patents

Description

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display having a structure suitable for driving an active matrix liquid crystal display device using a switching element for each pixel. Regarding the circuit.

[Conventional technology]

A large liquid crystal display device using Twisted Nematic liquid crystal (TN liquid crystal, hereafter abbreviated as TN liquid crystal) displays data sent to the LCD X driver in synchronization with the data shift clock for one line of the screen. At the same position, the data signal is latched by the X driver by the clock and is scanned by the scanning circuit Y drive to display the pixels.

At this time, the liquid crystal scanning and pixel display timings are latched by the fall of the data signal latch clock for one line of display data, and the Y driver scanning is also shifted by the trailing edge of the data signal latch clock.

As a conventional example of this type, for example, LCD dot matrix common driver data sheet (MSM5298G
S) can be mentioned.

[Problems to be solved by the invention]

The structure and operation of this type of liquid crystal display device will be outlined with reference to FIG.

FIG. 9 is an explanatory diagram of a liquid crystal display device, in which (a) is a configuration diagram, (b) is an explanatory diagram of wiring resistance of a gate line, and (c) is a timing for explaining a shift in on / off timing of a gate. It is a figure.

As shown in FIG. 3A, in an active matrix liquid crystal (hereinafter abbreviated as TFT active matrix liquid crystal) using an insulated gate thin film transistor (TFT) 7 as a switching element in each pixel, as shown in FIG. The wiring resistance of the gate line 6 (wiring resistance value per pixel r
d), there is a pixel (X
The wiring resistance value of the gate line 6 in the direction X _n ) becomes maximum as (rd · n), and this wiring resistance value causes the gate line drive signal voltage of Y _m of the Y driver output as shown in FIG. waveform rounding as Y _m ', the gate-on / off timing of the TFT7 is turned on at t _a, it will be delayed by t _b off.

FIG. 10 is a driving timing chart of the TN type liquid crystal display device according to the prior art. Due to the delay, as in the driving method by the conventional TN type liquid crystal driver IC and liquid crystal controller, the fall of the data signal latch clock CL1 is caused. As shown in FIG. 10, when the scanning signal timing (Y ₁ , Y ₁ , ... ...... Y _m ) of the Y driver is generated only by the timing of, the TFT switching timing shift due to the wiring resistance of the liquid crystal panel, each pixel There was a problem that data could not be displayed normally and could not be displayed.

It is an object of the present invention to provide a liquid crystal display circuit adapted to generate and supply a drive signal timing most suitable for drive display of a TFT active matrix liquid crystal.

[Means for solving problems]

The above-mentioned purpose has heretofore been the fall of the data signal latch lock CL1 and the latch of 1-line data in the X driver
The driver scanning signal was turned on instead of the timing control of the Y driver scanning signal being turned on only by the falling edge of the data signal latch clock CL1, but at the timing different from this clock CL1 by one horizontal scanning. This is achieved by providing a circuit that adjusts the TFT gate voltage on period during the period.

[Action]

In the TFT active matrix liquid crystal, as shown in FIG. 9, the insulated gate thin film transistor (TFT) 7 of the liquid crystal 8 of each pixel is arranged, and the drain line 5 is formed by the X driver 3.
The gate line 6 is driven by the Y driver 4.

11 and 12 are driving timing charts of the X driver and the Y driver. The display data sent to the X driver 3 in synchronization with the data shift clock 10 (CL2) is the data signal latch clock 1 ( CL1) latches as display data for one line in the X direction, and drain line 5
It is output to (X ₁ , X ₂ , ……… X _n ). During the period t _L during which the display data for one line is latch-outputted, the gate lines 6Y ₁ , Y ₂ , ...
... Y _m ) is turned on, but this gate line 6 drive period t
_{The g} is set so that the timing and the length can be arbitrarily set so that the charge corresponding to the display data is sufficiently accumulated in the liquid crystal 8 after the latched display data for one line is determined.

As a result, the TFT active matrix liquid crystal can display the display data normally, and the gate line 6
Since the drive time t _g of can be set variably, it can also drive TFT active matrix liquid crystals with different liquid crystal charge capacities.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a principle diagram of a TFT active matrix liquid crystal display circuit. 1 is a data signal latch, 3 is an X driver, 4 is a Y driver, 10 is a TFT liquid crystal module, 11
Is a TFT active matrix liquid crystal panel, 12 is a liquid crystal controller (LCDC), 13 is a timing adjustment circuit, and 14 is a gate line reset clock.

In the figure, the TFT liquid crystal module 10 includes a TFT active matrix liquid crystal panel 11 and an X for driving in the horizontal direction.
It comprises a drive 3 and a Y driver 4 for vertical drive. It is a conventional TN type liquid crystal controller (LCDC) 12 that generates data and various timing signals in the TFT liquid crystal module 10, and a data signal latch clock 1 (CL1) for synchronizing and latching display data for one line.
Therefore, it is composed of a timing adjusting circuit 13 for generating a gate line reset clock 14 (CL1 ') for adjusting the ON period of the Y driver 4. The signal CL2 in the figure is a data shift clock synchronized with the data, and FLM is 1
It is a clock for screen synchronization (vertical synchronization).

Figure 2 is filed in the timing diagram of the data signal Ratsuchikurotsuku 1 (CL1) and a gate line reset black stick 14 (CL1 '), although latch period of the display data for one line is t _L, the t _L period indicating that utilizes fall of CL1 'to generate an on-time t _g of Y driver gate lines (Y ₁ to Y _m in.

FIG. 3 is an explanatory view of the main parts of FIG. 1, where (a) is a block diagram of the Y driver and (b) is a block diagram of the timing adjustment circuit.

In the figure (a), 15 is a level driver, 16 is a shift register, each line (horizontal direction) on timing of the liquid crystal panel is sequentially shifted by the shift register 16 at the trailing edge of CL1, and the level driver 15 causes the TFT It is driven to a voltage for driving the gate lines (Y _{1 to} Y _m ) of the active matrix liquid crystal panel 11. However, this gate line ON voltage is CL
It is reset by the rising edge of 1 '.

In FIG. 2B, 18 is a selector and 19 is a shift register. The data signal latch clock 1 (CL1) is shifted by the shift register 19 and the shift amount, that is, the gate line reset clock 14 (delayed by the time t _g ). It comprises a selector 18 for selecting CL1 ') and a t _g adjustment signal 17 for selection.

As described above, it is possible to drive various TFT active matrix liquid crystals by using the liquid crystal controller 12 for the conventional TN type liquid crystal, adding the timing adjustment circuit to this, and utilizing the t _g adjustment signal 17. There is.

FIG. 4 illustrates an embodiment of the TFT active matrix liquid crystal display circuit according to the present invention.

FIG. 4 is a block diagram showing another embodiment of the TFT active matrix liquid crystal display circuit according to the present invention, in which 21 is a timing adjusting circuit and the same reference numerals as those in FIG. 1 correspond to the same portions.

In the figure, a TFT liquid crystal module 10 comprises a TFT active matrix liquid crystal panel 11, an X driver 3 for horizontal drive and a Y driver 4 for vertical drive.
It is the same TN type LCD controller (LCDC) 12 that generates data and various timing signals for driving the LCD in the TFT LCD module 10, and is data for synchronizing and latching the display data for one line. From the signal latch clock 1 (CL1), the data signal latch timing component,
Data signal latch clock 20 which is a combination of gate line reset timing components for adjusting the ON period of the Y driver 4
It is composed of a timing adjustment circuit 21 for generating (CL1 ″).

FIG. 5 is a drive timing chart of FIG. 4, in which the data signal latch clock 20 and the gate line (Y ₁
~ Y _m ) shows the drive timing to turn on.

FIG. 6 is an explanatory diagram of the timing adjustment circuit of FIG.
(A) is a block diagram thereof, and (b) is a timing diagram.

As shown in FIG. 5, the data signal latch clock 20 of FIG. 5 shifts the data latch clock 1 (CL1), which used to latch the data for one line only by the falling component, in the shift register 19 by the shift delay. And t _g adjustment signal 17
The shift amount is selected by the selector 18, and the generated gate line reset clock (CL1 ') and the data latch clock (CL1) are combined and generated. The falling component of the data signal latch clock 20 (CL1 ″) produces the latch timing (cycle time t _L ) of the one-line data signal, and the rising component produces the reset timing of the gate line (gate line on-time t _g ).

FIG. 7 is a block diagram of the Y driver when the data signal latch clock (CL1 ″) is used.

In the figure, the ON timing of each horizontal line of the liquid crystal panel is the same as the above-mentioned data signal latch clock 20 (CL1 ″).
The shift register 16 sequentially shifts at the trailing edge of, and the level driver 15 causes the TFT active matrix liquid crystal panel 1
It is driven to the voltage for driving ₁ gate line (Y _{1 to} Y _m ). However, the voltage of the gate line ON is reset by the rise of CL1 ″.

According to the above embodiment, the timing adjustment circuit 21 causes the TN
The type liquid crystal controller 12 is a conventional one, and the number of signal lines between the liquid crystal controller 12 and the TFT liquid crystal module 10 is reduced, so that the TFT active matrix liquid crystal can be driven.

Further, by incorporating the timing adjustment circuit 21 into the TFT liquid crystal module 10, a TFT liquid crystal module compatible with the conventional TN type liquid crystal display circuit can be obtained. As a result, the TFT active matrix liquid crystal can be displayed by the conventional drive signal for the TN type liquid crystal.

FIG. 8 is a block diagram showing another embodiment of the present invention, which is the timing adjustment circuit 21 shown in the embodiment of FIG.
By incorporating in the liquid crystal controller (LCDC) 22,
The control signal lines for the TFT liquid crystal module 10 are integrated so that the configuration can be simplified.

〔The invention's effect〕

As described above, according to the present invention, the timing signal for driving the TFT active matrix liquid crystal can be generated from that for the conventional TN type liquid crystal, and the number of signal lines can be reduced to reduce the number of parts. It is possible to reduce and simplify the assembly work. Moreover, since the gate on time t _g is variable,
Optimum drive signal timing can be generated with the same liquid crystal drive circuit for various TFT active matrix liquid crystals with different liquid crystal charge capacities, and a liquid crystal display circuit with excellent functions can be provided excluding the drawbacks of the conventional technology. it can.

[Brief description of drawings]

1 is a principle diagram of the present invention, FIG. 2 is a drive timing diagram of FIG. 1, FIG. 3 is an explanatory diagram of main parts of FIG. 1, (a) is a block diagram of a Y driver, and (b) is timing adjustment. FIG. 4 is a block diagram of the circuit, FIG. 4 is a block diagram showing an embodiment of the present invention, FIG. 5 is a drive timing diagram of FIG. 4, and FIG. 6 is an explanatory diagram of the timing adjustment circuit of FIG. Is a block diagram (b)
Is a timing diagram, FIG. 7 is a block diagram of the Y driver, FIG. 8 is a block diagram showing another embodiment of the present invention, and FIG. 9 is an explanatory diagram of the structure and operation of the liquid crystal display device. The configuration diagram (b) is an explanatory diagram of the wiring resistance of the gate line, (c) is a gate on / off timing diagram, FIG. 10 is a drive timing diagram of a liquid crystal display device according to the prior art, and FIGS. It is a drive timing diagram of a driver and a Y driver. 3 ... X driver, 4 ... Y driver, 10 ... TFT liquid crystal module, 11 ... TFT active matrix liquid crystal panel, 12 ... Liquid crystal controller (LCDC), 13 ... Timing adjustment circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Satoshi Onuma Satoshi Onuma 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Nikkei Video Engineering Co., Ltd. (72) Tokoru Karasawa 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Tachi Video Engineering Co., Ltd. (72) Inventor Tsujiharu Tateuchi, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Ltd. Microelectronics Equipment Development Laboratory, Hitachi, Ltd. (72) Inventor Masaaki Kitajima 4026, Kuji-machi, Hitachi, Ibaraki Address: Hitachi Research Laboratory, Hiritsu Seisakusho Co., Ltd. (72) Inventor Shinji Tanaka 1479, Kamimizuhonmachi, Kodaira-shi, Tokyo In-house Hitachi Micro Computer Engineering Co., Ltd. (56) Reference: JP-A-63-118128 (JP, A)

Claims (4)

[Claims] 1. An active matrix liquid crystal panel using an insulated gate thin film transistor as a switching element, a drain drive circuit for driving a drain of the insulated gate thin film transistor, and a gate drive circuit for driving a gate of the insulated gate thin film transistor. A liquid crystal module, and a liquid crystal controller that generates display data and a clock synchronized with the display data,
In a liquid crystal display circuit in which the cycle of the clock is equal to the period of one line of the display data, the level is inverted at the start timing of each cycle of the clock to obtain a latch timing edge, and from the latch timing to one cycle of the clock or more. A timing adjustment circuit is provided for inverting the level after a short period of time to generate a data signal latch clock as an off timing edge, and the drain drive circuit latches the display data by one line for each latch timing edge of the data signal latch clock. Then, the drain of the insulated gate thin film transistor is driven, and the gate drive circuit forms a gate drive signal in the period from the latch timing edge of the data signal latch to the off timing edge, and the insulated gate is driven by the gate drive signal. Thin film tiger The liquid crystal display circuit and drives the gate of the register. 2. The liquid crystal display circuit according to claim 1, wherein the timing adjustment circuit has means for varying a time interval of an off timing edge in the data signal latch clock from the latch timing edge. Liquid crystal display circuit characterized by. 3. A liquid crystal display circuit according to claim 1, wherein the timing adjusting circuit is built in the liquid crystal controller, and the liquid crystal controller is integrated into a circuit. circuit. 4. The liquid crystal display circuit according to claim 1 or 2, wherein the timing adjustment circuit is built in the liquid crystal module.