TWI413969B - Liquid crystal display device and control method thereof - Google Patents

Abstract

The present invention provides a liquid crystal display device and a control method thereof. The liquid crystal display device comprises a plurality of scan lines, a plurality of data lines, a plurality of pixel circuits, a scan driving unit, a data driver, and a timing controller. The data driver outputs a plurality of data signals representing reset frame and image frame alternately to the data lines respectively. The timing controller outputs a start signal, an odd clock signal, and an even clock signal. The scan driving unit outputs a plurality of scan signals to the scan lines respectively, controls the time when pulses of the scan signals start to appear sequentially according to the start signal, controls pulse width of the scan signals corresponding to the odd-numbered scan lines according to the odd clock signal, and controls pulse width of the scan signals corresponding to the even-numbered scan lines according to the even clock signal.

Description

Liquid crystal display device and control method thereof

The present invention relates to a liquid crystal display device and a control method thereof, and more particularly to a liquid crystal display device using an impulse type driving method and a control method thereof.

Liquid crystal display devices are widely used in various modern electronic devices because of their advantages of thin profile, light weight, low power consumption, low radiation, and compatibility with semiconductor process technology. However, the liquid crystal is a viscous substance, which causes the reaction time of the liquid crystal display device to be generally long, and the liquid crystal display device usually adopts a hold type driving mode, and therefore, when the liquid crystal display device is used for dynamic image display. At the time, it is easy to cause the smear phenomenon due to the fast reaction speed, which affects the dynamic image quality.

In order to solve the smear phenomenon of the liquid crystal display device during the dynamic image display, most of the current researches adopt the pulse type driving method, that is, insert a black picture between two adjacent image frames, so that the image picture and the black picture are alternately displayed. , for example, as disclosed in U.S. Patent Nos. 6,693,618 and 6,074,034. This technology can make the gray scale change between screens more obvious, thereby shortening the reaction time of the liquid crystal display device to improve its dynamic image quality.

Accordingly, it is an object of the present invention to provide a liquid crystal display device using a pulsed driving method.

Therefore, the liquid crystal display device of the present invention comprises a plurality of scanning lines arranged in parallel, a plurality of data lines vertically arranged with the scanning lines, a plurality of pixel circuits defined by the scanning lines and the data lines, and arranged in a matrix. A scan driving unit electrically connected to the trace lines, a data driver electrically connected to the data lines, and a timing controller electrically connected to the scan driving unit.

The data driver outputs a plurality of data signals to the data lines, wherein the data signals alternately represent a reset picture and an image picture; the timing controller outputs a start signal, an odd clock signal, and an even clock signal to the a scan driving unit; the scan driving unit respectively outputs a plurality of scan signals to the scan lines, and controls, according to the start signal, a time at which the scan signals start to sequentially pulse, and the odd clock signal control is output to the scan signals according to the start signal a pulse width of the scan signals of the odd scan lines in the scan line, and a pulse width of the scan signals output to the even scan lines of the scan lines according to the even clock signals, so that the data signals are written Into these pixel circuits.

The liquid crystal display device of the present invention controls the scan signals according to the start signal, the odd clock signal and the even clock signal, and can alternately display the reset screen and the image screen to improve the dynamic image quality.

Another object of the present invention is to provide a control method for a liquid crystal display device which can achieve a pulse driving method.

Therefore, the control method of the liquid crystal display device of the present invention is applied to a scan line including a plurality of parallelly arranged scan lines, a plurality of data lines vertically disposed with the scan lines, and a plurality of lines defined by the scan lines and the data lines and arranged in a matrix A liquid crystal display device of a distributed pixel circuit. The control method of the liquid crystal display device includes the following steps:

(A) providing a start signal, an odd clock signal, and an even clock signal;

(B) generating, according to the start signal, the odd clock signal and the even clock signal, a plurality of scan signals suitable for being respectively output to the scan lines, wherein the scanning signals are controlled according to the start signal a timing at which a pulse occurs, controlling a pulse width of the scan signals output to the odd scan lines of the scan lines according to the odd clock signal, and controlling an even scan line outputted to the scan lines according to the even clock signal The pulse width of the scan signals; and

(C) providing complex data signals suitable for being output to the data lines, respectively, wherein the data signals alternately represent a reset picture and an image picture.

The control method of the liquid crystal display device of the present invention can control the scan signals according to the start signal, the odd clock signal and the even clock signal, so that the liquid crystal display device can alternately display the reset screen and the image screen to improve Its dynamic image quality.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments.

Referring to FIG. 1, a first preferred embodiment of the liquid crystal display device 1 of the present invention includes a plurality of parallel-arranged scan lines 11, a plurality of data lines 12 disposed perpendicularly to the scan lines 11, and a plurality of scan lines 11 and data lines 12 defined by A matrix-distributed pixel circuit 13, a scan driving unit 14 electrically connected to the scan line 11, a data driver 15 electrically connected to the data line 12, and a timing control electrically connected to the scan driving unit 14 and the data driver 15. 16.

The pixel circuits 13 located in the same column are electrically connected to the same scanning line 11, and the pixel circuits 13 located in the same row are electrically connected to the same data line 12. Each of the pixel circuits 13 includes a thin film transistor 131 and a liquid crystal capacitor 132. The thin film transistor 131 has a gate electrically connected to the corresponding scan line 11 and an electrical connection to the corresponding data line 12. a source, and a drain; the liquid crystal capacitor 132 has a first end electrically connected to the drain of the thin film transistor 131, and a second end receiving a common voltage. Each pixel circuit 13 is controlled by a signal on the corresponding scan line 11 to transfer the signal on the corresponding data line 12 to the liquid crystal capacitor 132 when the thin film transistor 131 is turned on.

The timing controller 16 outputs a display data DATA which alternately represents the reset picture and the video picture to the data driver 15, and outputs a start signal STV, an odd clock signal CKVO and an even clock signal CKVE to the scan driving unit 14. The data driver 15 converts the display data DATA into a plurality of analog data signals D1 to Dq, and outputs the data signals D1 to Dq to the data lines 12, respectively. The scan driving unit 14 outputs the complex scan signals G1 G Gp to the scan line 11 respectively, and controls the timings at which the scan signals G1 G Gp start to sequentially pulse according to the start signal STV, and is controlled to be output to the odd scan lines according to the odd clock signal CKVO control. The pulse widths of the scanning signals (for example, G1, G3, G5, ...) and the pulse widths of the scanning signals (for example, G2, G4, G6, ...) output to the even scanning lines are controlled according to the even clock signal CKVE.

In the present embodiment, the scan driving unit 14 includes a scan driver 141. The scan driver 141 receives the start signal STV, the odd clock signal CKVO, and the even clock signal CKVE, and generates scan signals G1 to Gp accordingly. It should be noted that the scan driver 141 may be formed on the same glass substrate (not shown) together with the thin film transistor 131 of the pixel circuit 13, but may also be a separate integrated circuit.

Referring to FIG. 1 and FIG. 2, in a picture period T, the start signal STV has a first start pulse 21 and a second start pulse 22; the odd clock signal CKVO has a plurality of first clock pulses 23 and a plurality of second clocks. The pulse 24, and the rising edge of one of the first clock pulses 23 occurs during the occurrence of the first start pulse 21 of the start signal STV, wherein the rising edge of a second clock pulse 24 appears in the second of the start signal STV The period in which the start pulse 22 occurs; the even clock signal CKVE has a plurality of third clock pulses 25 and a plurality of fourth clock pulses 26; the first to fourth clock pulses 23 to 26 are sequentially cycled; each of the scan signals G1 to Gp has one The first scan pulse 27 and a second scan pulse 28.

The scan driver 141 controls the timing at which the first scan pulse 27 of the scan signals G1 G Gp starts to sequentially start according to the first start pulse 21 of the start signal STV, and controls the scan signal G1 according to the second start pulse 22 of the start signal STV. The second scan pulse 28 of Gp starts to appear sequentially, and the width of the first scan pulse 27 of the scan signal output to the odd scan lines is controlled according to the width of the first clock pulse 23 of the odd clock signal CKVO, according to the odd clock signal The width of the second clock pulse 24 of the CKVO controls the width of the second scan pulse 28 of the scan signal outputted to the odd scan lines, and the scan output to the even scan line according to the width of the third clock pulse 25 of the even clock signal CKVE. The width of the first scan pulse 27 of the signal, and the width of the second scan pulse 28 of the scan signal output to the even scan line according to the width of the fourth clock pulse 26 of the even clock signal CKVE, so that the scan signals G1 G Gp The first scan pulse 27 and the second scan pulse 28 alternately appear, for example, the order of occurrence is the first scan pulse 27 of the scan signal Gm, the scan signal G a second scan pulse 28 of 1 , a first scan pulse 27 of the scan signal Gm+1, a second scan pulse 28 of the scan signal G2, a first scan pulse 27 of the scan signal Gm+2, and a second scan pulse of the scan signal G3 28...

Referring to FIG. 3, the display data DATA represents a reset picture (as indicated by a hatched portion) during the occurrence of the first clock pulse 23 of the odd clock signal CKVO and the occurrence of the third clock pulse 25 of the even clock signal CKVE, and is in an odd number. The period during which the second clock pulse 24 of the clock signal CKVO occurs and the period during which the fourth clock pulse 26 of the even clock signal CKVE occurs represent a picture picture (as indicated by a blank portion), whereby the first scan pulse 27 of the scan signals G1 G Gp is generated. The reset screen can be written to the pixel circuit 13, and the second scan pulse 28 of the scan signals G1 to Gp can cause the image frame to be written to the pixel circuit 13. Therefore, the liquid crystal display device 1 of the present embodiment can alternately display the weight. Set the screen (for example: black or gray) and image to improve its dynamic image quality.

It should be noted that the widths of the first scan pulse 27 and the second scan pulse 28 of the scan signals G1 G Gp are not necessarily equal, that is, the widths of the first clock pulse 23 and the second clock pulse 24 of the odd clock signal CKVO are not necessarily equal. To be equal, the widths of the third clock pulse 25 and the fourth clock pulse 26 of the even clock signal CKVE are not necessarily equal, and the time required for the reset picture to be written to the pixel circuit 13 and the image picture are written to the pixel circuit. 13 depending on the time required.

Referring to FIG. 4, a second preferred embodiment of the liquid crystal display device 3 of the present invention includes a plurality of scanning lines 31 arranged in parallel, a plurality of data lines 32 disposed perpendicularly to the scanning lines 31, and a plurality of dividing lines defined by the scanning lines 31 and the data lines 32. A matrix-distributed pixel circuit 33, a scan driving unit 34 electrically connected to the scan line 31, a data driver 35 electrically connected to the data line 32, and a timing control electrically connected to the scan driving unit 34 and the data driver 35 36.

The pixel circuits 33 located in the same column are electrically connected to the same scanning line 31, and the pixel circuits 33 located in the same row are electrically connected to the same data line 32. Each of the pixel circuits 33 includes a thin film transistor 331 and a liquid crystal capacitor 332. The thin film transistor 331 has a gate electrically connected to the corresponding scan line 31 and an electrical connection to the corresponding data line 32. a source, and a drain; the liquid crystal capacitor 331 has a first end electrically connected to the drain of the thin film transistor 331 and a second end receiving a common voltage. Each pixel circuit 33 is controlled by a signal on the corresponding scan line 31 to transfer the signal on the corresponding data line 32 to the liquid crystal capacitor 332 when the thin film transistor 331 is turned on.

The timing controller 36 outputs a display data DATA alternately representing the reset picture and the image picture to the data driver 35, and outputs a start signal, an odd clock signal and an even clock signal to the scan driving unit 34, wherein the start signal A first start sub-signal STV1 and a second start sub-signal STV2 are included. The odd-numbered clock signal includes a first odd-numbered clock sub-signal CKVO1 and a second odd-numbered sub-signal CKVO2, and the even-numbered clock signal includes a first even-numbered clock sub- Signal CKVE1 and a second even clock sub-signal CKVE2. The data driver 35 converts the display data DATA into a plurality of analog data signals D1 to Dq, and outputs the data signals D1 to Dq to the data lines 32, respectively. The scan driving unit 34 outputs the complex scan signals G1 G Gp to the scan line 31, and controls the scan signals G1 G Gp to start the pulse sequentially according to the start signal, and controls the scan signals output to the odd scan lines according to the odd clock signals. The pulse width of (for example, G1, G3, G5, ...) and the pulse width of the scanning signals (for example, G2, G4, G6, ...) output to the even-numbered scanning lines in accordance with the even-numbered clock signals.

In the embodiment, the scan driving unit 34 includes a first scan driver 341 and a second scan driver 342. The first scan driver 341 receives the first start sub-signal STV1, the first odd-numbered clock sub-signal CKVO1 and the first even-numbered clock sub-signal CKVE1, and the second scan driver 342 receives the second start sub-signal STV2 and the second odd-numbered sub-signal CKVO2 And the second even clock sub-signal CKVE2, the first scan driver 341 and the second scan driver 342 generate the scan signals G1 G Gp according to the respective received signals. It should be noted that the first scan driver 341 and the second scan driver 342 may be formed on the same glass substrate (not shown) together with the thin film transistor 331 of the pixel circuit 33, but may also be an independent integrated circuit. .

Referring to FIG. 4 and FIG. 5, in a picture period T, the first start sub-signal STV1 has a first start pulse 41; the second start sub-signal STV2 has a second start pulse 42; the first odd-numbered clock sub-signal CKVO1 has a plurality of first clock pulses 43, and a rising edge of one of the first clock pulses 43 occurs during the occurrence of the first start pulse 41 of the first start sub-signal STV1; the second odd-numbered clock sub-signal CKVO2 has a complex second clock a pulse 44, and a rising edge of a second clock pulse 44 occurs during a second start pulse 42 of the second start sub-signal STV2; the first even clock sub-signal CKVE1 has a complex third clock pulse 45; The second even clock sub-signal CKVE2 has a plurality of fourth clock pulses 46; the first to fourth clock pulses 43-46 are sequentially cycled; each of the scan signals G1 G Gp has a first scan pulse 47 and a second scan pulse 48. .

The first scan driver 341 controls the time when the first scan pulse 47 of the scan signals G1 G Gp starts to appear according to the first start pulse 41 of the first start sub-signal STV1, according to the first clock pulse of the first odd-numbered clock sub-signal CKVO1 The width of 43 controls the width of the first scan pulse 47 of the scan signal outputted to the odd scan lines, and controls the scan signal output to the even scan lines according to the width of the third clock pulse 45 of the first even clock sub-signal CKVE1. The width of the first scan pulse 47; the second scan driver 342 controls the second scan pulse 48 of the scan signals G1 G Gp to start sequentially according to the second start pulse 42 of the second start sub-signal STV2, according to the second The width of the second clock pulse 44 of the odd clock sub-signal CKVO2 controls the width of the second scan pulse 48 of the scan signal outputted to the odd scan lines, and is controlled according to the width of the fourth clock pulse 46 of the second even clock sub-signal CKVE2. The width of the second scan pulse 48 of the scan signal outputted to the even scan lines; the two cooperate with each other such that the first scan pulse 47 and the scan signal G1 G Gp The scan pulse 48 alternately appears, for example, the order of appearance is the first scan pulse 47 of the scan signal Gm, the second scan pulse 48 of the scan signal G1, the first scan pulse 47 of the scan signal Gm+1, and the scan signal G2. The second scan pulse 48, the first scan pulse 47 of the scan signal Gm+2, and the second scan pulse 48 of the scan signal G3.

Referring to FIG. 6, in the case where the first scan pulse 47 of the scan signals G1 G Gp and the second scan pulse 48 do not overlap, that is, the first clock pulse 43 of the first odd clock sub-signal CKVO1 and the second odd clock sub-signal CKVO2 The second clock pulse 44 does not overlap, the third clock pulse 45 of the first even clock sub-signal CKVE1 does not overlap with the fourth clock pulse 46 of the second even clock sub-signal CKVE2, and the display data DATA is in the first odd-numbered clock sub-signal CKVO1. The period during which the first clock pulse 43 occurs and the third clock pulse 45 of the first even clock sub-signal CKVE1 occur represent a reset picture (as indicated by the hatched portion), and the second of the second odd-numbered clock sub-signal CKVO2 The period during which the clock pulse 44 occurs and the period in which the fourth clock pulse 46 of the second even clock sub-signal CKVE2 occurs are representative of the picture picture (as indicated by the blank portion), whereby the first scan pulse 47 of the scan signals G1 G Gp can be made heavy The screen is written to the pixel circuit 33, and the second scan pulse 48 of the scan signals G1 to Gp can cause the image frame to be written into the pixel circuit 33. Therefore, the liquid crystal display device 3 of the present embodiment can alternately Shows RESET screen (e.g.: gray or black picture screen) and a video screen, in order to improve the dynamic image quality.

Referring to FIG. 6 and FIG. 7, as shown in FIGS. 7(a) to 7(c), when the first scan pulse 47 and the second scan pulse 48 of the scan signals G1 to Gp do not overlap, the scan signal G1~ The widths of the first scan pulse 47 and the second scan pulse 48 of Gp are not necessarily equal, that is, the width of the first clock pulse 43 of the first odd clock sub-signal CKVO1 and the second clock pulse 44 of the second odd clock sub-signal CKVO2 It is not necessarily equal, the widths of the third clock pulse 45 of the first even clock sub-signal CKVE1 and the fourth clock pulse 46 of the second even clock sub-signal CKVE2 are not necessarily equal, and the reset picture is written to the pixel circuit 33. The time required and the video picture are determined by the time required to write to the pixel circuit 33.

In addition, as shown in FIG. 7(d), the first scan pulse 47 and the second scan pulse 48 of the scan signals G1 G Gp may be partially overlapped, that is, the first clock pulse 43 and the second of the first odd clock sub-signal CKVO1. The second clock pulse 44 of the odd clock sub-signal CKVO2 partially overlaps, and the third clock pulse 45 of the first even clock sub-signal CKVE1 partially overlaps the fourth clock pulse 46 of the second even-numbered clock sub-signal CKVE2, in this case, The display data DATA is during the period in which the first scan pulse 47 of the scan signals G1 G Gp occurs (ie, the first clock pulse 43 of the first odd clock sub-signal CKVO1 occurs, and the third clock pulse of the first even clock sub-signal CKVE1) The period 45 occurs represents a reset screen, and the second clock pulse 44 of the second odd clock sub-signal CKVO2 does not overlap with the second scan pulse 48 of the scan signals G1 G Gp not overlapping with the first scan pulse 47. a period during which the first clock pulse 43 of the first odd clock sub-signal CKVO1 overlaps, and a period during which the fourth clock pulse 46 of the second even clock sub-signal CKVE2 does not overlap with the third clock pulse 45 of the first even-numbered clock sub-signal CKVE1 It represents a video picture, whereby the pixel circuit 43 to be written into the video picture can be precharged during the partial overlap to further shorten the reaction time of the liquid crystal display device 3 of the present embodiment.

Referring to FIG. 8, a preferred embodiment of the method for controlling a liquid crystal display device of the present invention is applied to a scan line including a plurality of parallel arranged scan lines, a plurality of data lines vertically arranged with the scan lines, and a plurality of scan lines and data lines separated and defined. A liquid crystal display device of a matrix-distributed pixel circuit. The control method of the liquid crystal display device of this embodiment includes the following steps:

Step 51 is to provide a start signal, an odd clock signal and an even clock signal.

Step 52 is to generate a plurality of scan signals according to the start signal, the odd clock signal and the even clock signal, and respectively output the scan signal to the scan line, wherein the scan signal starts to sequentially start the pulse according to the start signal, according to the odd number The clock signal controls the pulse width of the scan signal output to the odd scan lines, and controls the pulse width of the scan signal output to the even scan lines in accordance with the even clock signal.

Step 53 is to provide a plurality of data signals, and respectively output the data signals to the data lines, wherein the data signals alternately represent the reset picture and the image picture.

For a detailed relationship between the start signal, the odd clock signal, the even clock signal, the scan signal and the data signal, reference may be made to the first preferred embodiment and the second preferred embodiment of the above liquid crystal display device, and will not be further described herein.

In summary, in the above embodiment, the scan signal is controlled by the start signal, the odd clock signal, and the even clock signal, so that the liquid crystal display device can alternately display the reset screen and the image screen (ie, the pulse driving method) to improve With its dynamic image quality, it is indeed possible to achieve the object of the present invention.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

1. . . Timing controller

11. . . Scanning line

12. . . Data line

13. . . Pixel circuit

131. . . Thin film transistor

132. . . Liquid crystal capacitor

14. . . Scan drive unit

141. . . Scan drive

15. . . Data driver

16. . . Timing controller

twenty one. . . First start pulse

twenty two. . . Second start pulse

twenty three. . . First clock pulse

twenty four. . . Second clock pulse

25. . . Third clock pulse

26. . . Fourth clock pulse

27. . . First scan pulse

28. . . Second scan pulse

3. . . Timing controller

31. . . Scanning line

32. . . Data line

33. . . Pixel circuit

331. . . Thin film transistor

332. . . Liquid crystal capacitor

34. . . Scan drive unit

341. . . First scan driver

342. . . Second scan driver

35. . . Data driver

36. . . Timing controller

41. . . First start pulse

42. . . Second start pulse

43. . . First clock pulse

44. . . Second clock pulse

45. . . Third clock pulse

47. . . First scan pulse

46. . . Fourth clock pulse

48. . . Second scan pulse

51~53. . . step

1 is a circuit diagram showing a first preferred embodiment of a liquid crystal display device of the present invention;

2 is a waveform diagram illustrating a start signal, an odd clock signal, an even clock signal, and a complex scan signal of the first preferred embodiment, and the relationship between the signals;

3 is a waveform diagram illustrating a display material of the first preferred embodiment, and a relationship between display data, an odd clock signal, an even clock signal, and a scan signal;

Figure 4 is a circuit diagram showing a second preferred embodiment of the liquid crystal display device of the present invention;

FIG. 5 is a waveform diagram illustrating a first start sub-signal, a second start sub-signal, a first odd-numbered clock sub-signal, a second odd-numbered clock sub-signal, and a first even number in the second preferred embodiment. a clock sub-signal, a second even clock sub-signal, and a complex scan signal, and a relationship between the signals;

6 is a waveform diagram illustrating a display material of the second preferred embodiment, and display data, a first odd clock sub-signal, a second odd clock sub-signal, a first even-numbered clock sub-signal, and a second even-numbered clock sub-signal. Relationship with the scan signal;

Figure 7 is a waveform diagram showing the relationship between the display material and the scan signal of the second preferred embodiment;

Figure 8 is a flow chart showing a preferred embodiment of the control method of the liquid crystal display device of the present invention.

twenty one. . . First start pulse

twenty two. . . Second start pulse

twenty three. . . First clock pulse

twenty four. . . Second clock pulse

25. . . Third clock pulse

26. . . Fourth clock pulse

27. . . First scan pulse

28. . . Second scan pulse

Claims (30)

A liquid crystal display device comprising: a plurality of scan lines arranged in parallel; a plurality of data lines arranged perpendicularly to the scan lines; and a plurality of pixel circuits defined by the scan lines and the data lines and arranged in a matrix; a scan driving unit connected to the trace lines; a data driver electrically connected to the data lines; and a timing controller electrically connected to the scan driving unit; wherein the data driver outputs a plurality of data signals to the The data lines alternately represent a reset picture and an image picture; the timing controller outputs a start signal, an odd clock signal, and an even clock signal to the scan driving unit; the scan driving unit respectively outputs a complex scan Transmitting a signal to the scan lines, and controlling, according to the start signal, a time at which the scan signals start to sequentially pulse, and controlling the scan signals output to the odd scan lines in the scan lines according to the odd clock signals. a pulse width, and controlling the scans that are output to the even scan lines of the scan lines according to the even clock signal a pulse width of the number such that the data signals are written to the pixel circuits; wherein, in a picture period, the start signal has a first start pulse and a second start pulse, the odd clock signal The plurality of first clock pulses and the plurality of second clock pulses, the even clock signal having a plurality of third clock pulses and a plurality of fourth clock pulses, each of the scan signals having a first scan pulse and a second scan pulse. The liquid crystal display device of claim 1, wherein the scan driving unit comprises a scan driver, the scan driver receiving the start signal, the odd clock signal and the even clock signal, and generating the same according to the scan driver Scan the signal. The liquid crystal display device of claim 2, wherein, in the picture period, a rising edge of one of the first clock pulses of the odd clock signal appears at a first start pulse of the start signal During which a rising edge of one of the second clock pulses of the odd clock signal occurs in the second of the start signal The period in which the start pulse occurs. The liquid crystal display device of claim 2, wherein the first clock pulse, the second clock pulse, and the third clock pulse and the fourth clock pulse of the odd clock signal are sequentially cycled. The liquid crystal display device of claim 4, wherein the scan driver controls, according to the first start pulse of the start signal, a time at which the first scan pulse of the scan signals starts to appear sequentially, according to the start a second start pulse of the signal controls a time at which the second scan pulse of the scan signal begins to appear sequentially, and the scan signals output to the odd scan lines are controlled according to a width of the first clock pulse of the odd clock signal a width of the first scan pulse, controlling a width of the second scan pulse of the scan signals output to the odd scan lines according to a width of the second clock pulse of the odd clock signal, according to the third of the even clock signals The width of the clock pulse controls the width of the first scan pulse of the scan signals outputted to the even scan lines, and controls the output to the even scan lines according to the width of the fourth clock pulse of the even clock signal The width of the second scan pulse of the scan signal. The liquid crystal display device of claim 5, wherein the data signals represent a reset screen during a period in which the first clock pulse of the odd clock signal occurs and a third clock pulse of the even clock signal And representing the image frame during the occurrence of the second clock pulse of the odd clock signal and the occurrence of the fourth clock pulse of the even clock signal. The liquid crystal display device of claim 1, wherein the start signal comprises a first start sub-signal and a second start sub-signal, wherein the odd-numbered clock signal comprises a first odd-numbered clock sub-signal and a And a second odd clock sub-signal, the even clock signal comprising a first even clock sub-signal and a second even clock sub-signal. The liquid crystal display device of claim 7, wherein the scan driving unit comprises a first scan driver and a second scan driver, the first scan driver receiving the first start sub-signal, the first odd number a clock sub-signal and the first even clock sub-signal, the second scan driver receiving the second start sub-letter The second odd-numbered clock sub-signal and the second even-numbered clock sub-signal, the first scan driver and the second scan driver generate the scan signals according to the respective received signals. The liquid crystal display device of claim 8, wherein the first start sub-signal has the first start pulse and the second start sub-signal has the second start pulse in a picture period, The first odd clock sub-signal has the first clock pulse, the second odd clock sub-signal has the second clock pulse, the first even clock sub-signal has the third clock pulse, the second even clock The sub-signals have the fourth clock pulses. The liquid crystal display device of claim 9, wherein a rising edge of one of the first clock pulses of the first odd clock sub-signal appears in the first start sub-signal during the picture period During the occurrence of a start pulse, a rising edge of one of the second clock pulses of the second odd clock sub-signal occurs during the occurrence of the second start pulse of the second start sub-signal. The liquid crystal display device of claim 9, wherein the first clock pulse of the first odd clock sub-signal, the second clock pulse of the second odd clock sub-signal, and the first even-numbered clock sub-signal The third clock pulse and the fourth clock pulse of the second even clock sub-signal are sequentially cycled. The liquid crystal display device of claim 11, wherein the first scan driver controls, according to the first start pulse of the first start sub-signal, a time when the first scan pulse of the scan signals starts to appear sequentially, Controlling a width of a first scan pulse of the scan signals output to the odd scan lines according to a width of a first clock pulse of the first odd clock sub-signal, and a third clock according to the first even clock sub-signal The width of the pulse controls the width of the first scan pulse of the scan signals outputted to the even scan lines, and the second scan driver controls the scan signals according to the second start pulse of the second start sub-signal a second scan pulse begins to sequentially appear, controlling a width of the second scan pulse of the scan signals output to the odd scan lines according to a width of the second clock pulse of the second odd clock sub-signal, and according to the The width of the fourth clock pulse of the second even clock sub-signal controls the scans that are output to the even scan lines The width of the second scan pulse of the signal. The liquid crystal display device of claim 12, wherein the first clock pulse of the first odd clock sub-signal does not overlap with the second clock pulse of the second odd clock sub-signal, the first even clock sub- The third clock pulse of the signal does not overlap with the fourth clock pulse of the second even clock sub-signal. The liquid crystal display device of claim 13, wherein the data signals appear during a first clock pulse of the first odd clock sub-signal and a third clock pulse of the first even clock sub-signal The period represents a reset picture, and represents an image picture during the occurrence of the second clock pulse of the second odd clock sub-signal and the occurrence of the fourth clock pulse of the second even clock sub-signal. The liquid crystal display device of claim 12, wherein the first clock pulse of the first odd clock sub-signal partially overlaps the second clock pulse of the second odd clock sub-signal, the first even clock sub- The third clock pulse of the signal partially overlaps the fourth clock pulse of the second even clock sub-signal. The liquid crystal display device of claim 15, wherein the data signals appear during a first clock pulse of the first odd clock sub-signal and a third clock pulse of the first even clock sub-signal The period represents a reset picture, and the second clock pulse of the second odd clock sub-signal does not overlap with the first clock pulse of the first odd-numbered sub-signal, and the fourth even-numbered clock sub-signal A period in which the clock pulse does not overlap with the third clock pulse of the first even clock sub-signal represents an image picture. A control method for a liquid crystal display device is applied to a scan line including a plurality of parallel sets, a plurality of data lines vertically disposed with the scan lines, and a plurality of scan lines defined by the scan lines and the data lines and arranged in a matrix A liquid crystal display device for a pixel circuit, the method for controlling the liquid crystal display device comprising the steps of: (A) providing a start signal, an odd clock signal, and an even clock signal; (B) according to the start signal, the odd clock signal And the even clock signal, generating a plurality of scan signals suitable for being respectively output to the scan lines, wherein the scan signals are sequentially controlled to start the pulse according to the start signal, Controlling, according to the odd clock signal, a pulse width of the scan signals output to the odd scan lines of the scan lines, and controlling the scan signals output to the even scan lines of the scan lines according to the even clock signals a pulse width, wherein, in a picture period, the start signal has a first start pulse and a second start pulse, the odd clock signal having a plurality of first clock pulses and a plurality of second clock pulses, the even clock signal Having a plurality of third clock pulses and a plurality of fourth clock pulses, each of the scan signals having a first scan pulse and a second scan pulse; and (C) providing a plurality of data signals suitable for being respectively output to the data lines, Among them, the data signals alternately represent a reset screen and an image screen. The control method of a liquid crystal display device according to claim 17, wherein, in the picture period, a rising edge of one of the first clock pulses of the odd clock signal appears at a first start of the start signal During the occurrence of the pulse, a rising edge of one of the second clock pulses of the odd clock signal occurs during the occurrence of the second start pulse of the start signal. The control method of the liquid crystal display device of claim 17, wherein the first clock pulse of the odd clock signal, the second clock pulse, and the third clock pulse and the fourth clock pulse of the even clock signal are sequentially The loop appears. The control method of the liquid crystal display device according to claim 19, wherein in the step (B), the first scan pulse of the scan signal is controlled to start according to the first start pulse of the start signal. And a time when the second start pulse of the scan signal starts to sequentially start according to the second start pulse of the start signal, and the width control of the first clock pulse according to the odd clock signal is output to the time Widths of the first scan pulses of the scan signals of the odd scan lines, and widths of the second scan pulses of the scan signals output to the odd scan lines according to the width of the second clock pulses of the odd clock signals, Controlling, according to a width of the third clock pulse of the even clock signal, a width of a first scan pulse of the scan signals output to the even scan lines, and controlling a width of the fourth clock pulse according to the even clock signal to be output The width of the second scan pulse of the scan signals to the even scan lines. The method of controlling a liquid crystal display device according to claim 20, wherein the data signals are represented during a period in which the first clock pulse of the odd clock signal occurs and a third clock pulse of the even clock signal The picture is reset and represents an image picture during the occurrence of the second clock pulse of the odd clock signal and during the occurrence of the fourth clock pulse of the even clock signal. The control method of the liquid crystal display device of claim 17, wherein the start signal comprises a first start sub-signal and a second start sub-signal, wherein the odd-numbered clock signal comprises a first odd clock The signal and a second odd clock sub-signal, the even clock signal comprising a first even clock sub-signal and a second even clock sub-signal. The control method of the liquid crystal display device of claim 22, wherein the first start sub-signal has the first start pulse and the second start sub-signal has the second start in a picture period a first pulse, the first odd clock sub-signal having the first clock pulse, the second odd clock sub-signal having the second clock pulse, the first even-numbered clock sub-signal having the third clock pulse, the first The two even clock sub-signals have the fourth clock pulses. The control method of a liquid crystal display device according to claim 23, wherein, in the picture period, a rising edge of one of the first clock pulses of the first odd clock sub-signal appears in the first starter During the occurrence of the first start pulse of the signal, a rising edge of one of the second clock pulses of the second odd clock sub-signal occurs during the occurrence of the second start pulse of the second start sub-signal. The control method of the liquid crystal display device of claim 23, wherein the first clock pulse of the first odd clock sub-signal, the second clock pulse of the second odd clock sub-signal, the first even-numbered clock The third clock pulse of the sub-signal and the fourth clock pulse of the second even clock sub-signal are sequentially cycled. The control method of the liquid crystal display device of claim 25, wherein in the step (B), the first scan pulse of the first start sub-signal is controlled to start the first scan pulse of the scan signals. In the sequentially occurring time, controlling the width of the first scan pulse of the scan signals output to the odd scan lines according to the width of the first clock pulse of the first odd clock sub-signal, according to the The width of the third clock pulse of an even clock sub-signal controls the width of the first scan pulse of the scan signals outputted to the even scan lines, and the second start pulse of the second start sub-signal controls the And a second scan pulse of the scan signals output to the odd scan lines is controlled according to a width of the second clock pulse of the second odd clock sub-signal, when the second scan pulse of the scan signal begins to appear sequentially Width, and controlling a width of a second scan pulse of the scan signals output to the even scan lines according to a width of a fourth clock pulse of the second even clock sub-signal. The control method of the liquid crystal display device of claim 26, wherein the first clock pulse of the first odd clock sub-signal does not overlap with the second clock pulse of the second odd clock sub-signal, the first The third clock pulse of the even clock sub-signal does not overlap with the fourth clock pulse of the second even clock sub-signal. The control method of the liquid crystal display device of claim 27, wherein the data signals are during a first clock pulse of the first odd clock sub-signal and a third time of the first even clock sub-signal The period in which the clock pulse occurs represents a reset picture, and represents an image picture during the occurrence of the second clock pulse of the second odd clock sub-signal and the occurrence of the fourth clock pulse of the second even clock sub-signal. The control method of the liquid crystal display device of claim 26, wherein the first clock pulse of the first odd clock sub-signal partially overlaps the second clock pulse of the second odd clock sub-signal, the first The third clock pulse of the even clock sub-signal partially overlaps the fourth clock pulse of the second even clock sub-signal. The control method of the liquid crystal display device of claim 29, wherein the data signals are during a first clock pulse of the first odd clock sub-signal and a third time of the first even clock sub-signal The period in which the clock pulse occurs represents a reset picture, and while the second clock pulse of the second odd clock sub-signal does not overlap with the first clock pulse of the first odd-numbered sub-signal, and the second even-numbered sub-signal The fourth clock pulse is not associated with the first even clock sub-signal The period in which the third clock pulse overlaps represents an image screen.