JPS63236010A - Liquid crystal display circuit - Google Patents

Abstract

PURPOSE:To generate an optimum driving signal timing for a driving display of a TFT active matrix liquid crystal, by providing a circuit for adjusting an insulating gate thin film transistor (TFT) gate voltage ON period in one horizontal scanning period. CONSTITUTION:Display data which has been sent to an X driver 3 by synchronizing with a data shift clock 10 (CL2) is latched as the display data of a one-line portion in the X direction by a data signal latch clock 1 (CL1), and outputted to drain lines 5X1-Xn. During this period tl, gate lines 6Y1-Ym are brought to ON-driving by a Y driver 4, as a scan in the Y direction. This driving period tg is provided so that the timing and the length can be set arbitrarily, after the display data of an on-line portion, which has been latched has been decided definitely, and also, so that a charge corresponding to the display data is accumulated enough in a liquid crystal 8. In such a way, in various TFT active matrix liquid crystals in which the charge capacity of the liquid crystal is different, an optimum driving signal timing can be generated by the same liquid crystal driving circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a liquid crystal display device, and particularly to a liquid crystal display device having a configuration suitable for driving an active matrix type liquid crystal display device using a switching element in each pixel. Regarding circuits.

[Conventional technology]

Twisted nematic liquid crystal (TwistedN
A large liquid crystal display device using emattc liquid crystal (hereinafter abbreviated as TN liquid crystal) is synchronized with the data shift clock.
When the data sent to the X driver of the liquid crystal is collected for 11 lines of the picture, it is latched by the X driver using the data signal latch clock, scanned by the scanning circuit Y drive, and displayed in pixels.

Regarding the timing of liquid crystal scanning and pixel display at this time, one line of display data is latched at the falling edge of the data signal latch clock, and the scanning of the X driver is also shifted at the falling edge of the data signal latch clock.

As a conventional example of this type, for example, Oki Electric's LCD dot matrix common driver data sheet (MSM
5298GS).

[Problem that the invention seeks to solve]

The structure and operation of this type of liquid crystal display device will be outlined with reference to FIG.

FIG. 9 is an explanatory diagram of a liquid crystal display device, in which (a) is a configuration diagram, (b) is an explanatory diagram of the wiring resistance of the gate line, and (C) is a timing diagram explaining the shift in gate on/off timing. It is a diagram.

As shown in Figure (a), in the Actep matrix liquid crystal (hereinafter abbreviated as TPT active matrix liquid crystal) using an insulated gate thin film transistor (TPT) 7 as a switching element in each pixel, as shown in Figure (b), Since there is wiring resistance of the gate line 6 (wiring resistance value rd per pixel), pixels located far from the X driver 4 (
The wiring resistance value of the gate line 6 in the X direction (X, ) is (rd・n)
Due to this wiring resistance value, the gate line drive signal voltage waveform of Y, , l of the X driver output becomes y, J as shown in the same figure (C), and TPT
7's gate on/offta, iminoji will be delayed by ta when it is on and L when it is off.

FIG. 10 is a drive timing diagram of a TN type liquid crystal display device according to the prior art.
As in the driving method using a type liquid crystal driver IC and a liquid crystal controller, the timing of the scanning signal of the X driver (Yl, Y2) can be adjusted only by the falling timing of the data signal latch clock CI, as shown in FIG. ,...
.

An object of the present invention is to provide a liquid crystal display circuit that generates and supplies optimal drive signal timing for driving and displaying a TPT active matrix liquid crystal.

[Means for solving problems]

” The second purpose is to conventionally use data signal latch clock CLI
At the falling edge of
The timing of turning on the scanning signal of the driver is not only controlled by the falling edge of the data signal latch clock CLI, but also by controlling the timing of turning on the scanning signal of the driver at a timing different from this clock CL1.
This is achieved by providing a circuit that adjusts the TPT gate voltage on period during the horizontal scanning period.

[Effect]

In the TPT active matrix liquid crystal, as shown in FIG. 9, an insulated gate thin film transistor (TPT) 7 is arranged in the liquid crystal 8 of each pixel, and the X driver 3 drives the drain line 5 and the X driver 4 drives the gate line 6. do.

11 and 12 are drive timing diagrams of the X driver and the data shift clock 10 (Cl
The display data sent to the X driver 3 in synchronization with 3) is latched as display data for one line in the X direction by the data signal latch clock l (CLI), and is transferred to the drain line 5 (x, ).

X2. ......XI,). The period t during which this one line of display data is latched and output
.

During scanning in the Y direction, the gate line 6 (Yl, Yz, ......YITh) is connected by the X driver 4.
The driving period 1g of the gate line 6 is set at a timing such that the latched display data for one line is determined and the liquid crystal 8 is sufficiently charged with charge corresponding to the display data. and length can be set arbitrarily.

As a result, the TPT active matrix liquid crystal
Display data can be displayed normally, and since the driving time t,1 of the gate line 6 can be variably set, it is possible to drive TPT active matrix liquid crystals having different charge capacities.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a TPT active matrix liquid crystal display circuit, in which 1 is a data signal latch clock, 3 is an X driver, 4 is an X driver, 10
is a TPT liquid crystal module, 11 is a TPT active matrix liquid crystal panel, and 12 is a liquid crystal controller (LCDC).
), 13 is a timing adjustment circuit, and 14 is a gate line reset clock.

In the figure, a TPT liquid crystal module 10 includes a TPT active matrix liquid crystal panel 11, an X drive 3 for driving in the horizontal direction, and a Y driver 4 for driving in the vertical direction. A conventional TN liquid crystal controller (LCDC) 12 generates data and various timing signals for the TPT liquid crystal module 10, and a data signal latch clock 1 (CLI) is used to synchronize and latch one line of display data. ), the gate line reset clock 14 (CL
It consists of a timing adjustment circuit 13 that generates I'). Note that the signal CL2 in the figure is a data shift clock synchronized with data, and FLM is a one-screen synchronization (vertical synchronization) clock.

Figure 2 shows data signal latch clock 1 (CLl)
and gate line reset clock 14 (CLI'), the latch period of 1547 minutes of display data is t, and during this tL period, the gate line ('Y l'' Y - ) shows that the falling edge of CLI' is used to generate the on period t9.

FIG. 3 is an explanatory diagram of the main part of FIG. 1, in which (a) is a block diagram of the Y driver, and (b) is a block diagram of the timing adjustment circuit.

In the same figure (a), 15 is a level driver, 16 is a shift register, and each line (horizontal direction) turn-on timing of the liquid crystal panel is at the falling edge of CLI.
6, and by the level driver 15, the TP
Gate line of T active matrix liquid crystal panel 11 (Y
, ~Yffl) is driven by a driving voltage. However, this gate line on voltage is reset by the rise of CLI'.

In the same figure (b), 18 is a selector, 19 is a shift register, and data signal latch clock 1 (CL
I) by shift register 19, and this shift 1
-it, that is, a selector 1 day for selecting the gate line reset clock 14 (CLI') delayed by time t9;
It consists of a tg adjustment signal 17 for selection.

According to the above embodiment, various TPT active matrix liquid crystals can be driven by using the liquid crystal controller 12 for conventional TN type liquid crystals, adding a timing adjustment circuit thereto, and utilizing the t9 adjustment signal 17. There is an effect.

Next, another embodiment of the present invention will be described.

FIG. 4 is a block diagram showing another embodiment of the TPT active matrix liquid crystal display circuit according to the present invention, 21
1 is a timing adjustment circuit, and the same reference numerals as in FIG. 1 correspond to the same parts.

In the figure, a TPT liquid crystal module 10 includes a TFT active matrix liquid crystal panel 11, an X driver 3 for horizontal drive, and a Y driver 4 for vertical drive.
Consisting of A TN type liquid crystal controller (LCDC) 12 similar to the conventional one generates data and various timing signals for driving the liquid crystal in this TPT liquid crystal module 10. Timing adjustment to generate data signal latch clock 20 (CLI"), which is a combination of data signal latch timing component and gate line reset timing component for adjusting the ON period of Y driver 4, from data signal latch clock 1 (CLI) It is composed of a circuit 21.

FIG. 5 is a drive timing diagram of FIG. 4, in which the data signal latch clock 20 and the gate line (
The drive timing for turning on Y, to Ya) is shown.

FIG. 6 is an explanatory diagram of the timing adjustment circuit shown in FIG.
) is its block diagram, and (b) is its timing diagram.

As shown in the figure, the data signal latch clock 20 in FIG. 5 is different from the data latch clock 1 (CLI
) is shifted and delayed by the shift register 19, and the shift amount is selected by the selector 18 from the iM integral multiplication signal 17, and the gate cotton reset clock 14 (CLI') is generated.
and the data latch clock 1 (CLI) are synthesized and generated.

The latch timing of the 1-line data signal (
The reset timing of the gate line (gate line on time t9) is generated using the cycle time t, ) and the rising-to-tri component.

FIG. 7 is a block diagram of the Y driver when using the data signal latch clock (CLI'').

In the figure, the on timing of each horizontal line of the liquid crystal panel is determined by the data signal latch clock 20 (CLI).
'') are sequentially shifted in the shift register 16 and driven by the level driver I5 to a voltage for driving the gate lines (Y1 to Y1) of the TPT active matrix liquid crystal panel 11.

However, this gate line ON voltage is reset by the rising edge of CL 1 ″.

According to the above embodiment, there is an effect that the TPT active matrix liquid crystal can be driven by using the conventional TN type liquid crystal controller 12 and adding the timing adjustment circuit 21.

The timing adjustment circuit 13゜21 in each of the above embodiments is
By incorporating it into the PT liquid crystal module IO, the TPT liquid crystal module can be made compatible with the conventional TN type liquid crystal display circuit. This has the effect that a TPT active matrix liquid crystal can be displayed using a conventional TN type liquid crystal drive signal.

FIG. 8 is a block diagram showing still another embodiment of the present invention, in which the timing adjustment circuit 21 shown in the embodiment of FIG. This has the effect of simplifying the configuration by simplifying the control signal lines for use.

〔Effect of the invention〕

As explained above, according to the present invention, the timing signal for driving the TPT active matrix liquid crystal can be changed from the conventional TPT active matrix liquid crystal driving timing signal.
It can be generated from those for N-type liquid crystals, and since the gate on time t9 is variable, the same liquid crystal drive circuit can generate optimal drive signal timing for various TPT active matrix liquid crystals with different charge capacities. Therefore, it is possible to provide a liquid crystal display circuit with excellent functions while eliminating the drawbacks of the prior art.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a drive timing diagram of Fig. 1, Fig. 3 is an explanatory diagram of the main part of Fig. 1, and (a) is a block diagram of the Y driver ( b) is a block diagram of the timing adjustment circuit, FIG. 4 is a block diagram showing another embodiment of the present invention, FIG. 5 is a drive timing diagram of FIG. 4, and FIG. 6 is a block diagram of the timing adjustment circuit of FIG. 4. In the explanatory diagram (a
) is a block diagram (b) is a timing diagram, FIG. 7 is a block diagram of a Y driver, FIG. 8 is a block diagram showing still another embodiment of the present invention, and FIG. 9 is a configuration of a liquid crystal display device and its operation. (a) is a configuration diagram, (b) is an explanatory diagram of the wiring resistance of the gate line, (C) is a gate on/off timing diagram, FIG. 10 is a drive timing diagram of a liquid crystal display device according to the prior art, and Figure 11. FIG. 12 is a drive timing diagram of the X driver and Y driver. ３・・・・・・・・・X driver, ４・・・・・・・・・
・Y driver, 10......T F T t
fft, crystal module, 11...TFT
Active matrix liquid crystal panel, 12...
・・Liquid crystal controller (LCDC), 13...
...Timing adjustment circuit. Fig. 1 Fig. 2 Suriification Fig. 3 (0) Y-dried “life’” front and tide map (b) CLI’7f pano °° mouth and tsuku diagram ×
-11- ♀ J II'＋ 0

Claims (1)

[Scope of Claims] 1. A liquid crystal display circuit comprising an active matrix liquid crystal panel using insulated gate thin film transistors as switching elements, a drive circuit, and a data and timing signal generation circuit, wherein the drain and gate of the insulated gate thin film transistor are 1. A liquid crystal display circuit comprising a switching signal generating circuit for changing a drive phase and configured to eliminate the switching deviation caused by wiring resistance of a liquid crystal panel. 2. The liquid crystal display circuit according to claim 1, wherein the switching signal generation circuit is configured to make the gate-on time of the insulated gate thin film transistor variable.